Summary for Variable csrng_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for csrng_glen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
1904 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T17 |
24 |
glens[1] |
8 |
1 |
|
|
T8 |
1 |
|
T68 |
1 |
|
T103 |
1 |
glens[2] |
4 |
1 |
|
|
T279 |
1 |
|
T280 |
1 |
|
T281 |
1 |
glens[3] |
5 |
1 |
|
|
T282 |
1 |
|
T283 |
1 |
|
T284 |
1 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
1677 |
1 |
|
|
T1 |
1 |
|
T2 |
10 |
|
T17 |
30 |
pass |
1627 |
1 |
|
|
T2 |
9 |
|
T17 |
28 |
|
T20 |
42 |
Summary for Cross csrng_genbits_cross
Samples crossed: csrng_glen csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for csrng_genbits_cross
Bins
csrng_glen | csrng_sts | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
fail |
954 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T17 |
13 |
glens[0] |
pass |
950 |
1 |
|
|
T2 |
4 |
|
T17 |
11 |
|
T20 |
17 |
glens[1] |
fail |
4 |
1 |
|
|
T68 |
1 |
|
T60 |
1 |
|
T285 |
1 |
glens[1] |
pass |
4 |
1 |
|
|
T8 |
1 |
|
T103 |
1 |
|
T64 |
1 |
glens[2] |
fail |
1 |
1 |
|
|
T279 |
1 |
|
- |
- |
|
- |
- |
glens[2] |
pass |
3 |
1 |
|
|
T280 |
1 |
|
T281 |
1 |
|
T286 |
1 |
glens[3] |
fail |
3 |
1 |
|
|
T283 |
1 |
|
T284 |
1 |
|
T287 |
1 |
glens[3] |
pass |
2 |
1 |
|
|
T282 |
1 |
|
T288 |
1 |
|
- |
- |