Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T33,T43,T93
1	1	0	1	Covered	T33,T43,T93
1	1	1	0	Covered	T1,T2,T17
1	1	1	1	Covered	T3,T6,T4

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T43,T93
1	1	Covered	T33,T43,T93

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T6,T10,T29
1	1	Covered	T3,T6,T4

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	54	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T6,T4,T10
AutoCaptGenCnt	162	Covered	T6,T4,T10
AutoCaptReseedCnt	160	Covered	T6,T10,T29
AutoDispatch	142	Covered	T3,T6,T4
AutoFirstAckWait	135	Covered	T3,T6,T4
AutoLoadIns	90	Covered	T3,T6,T4
AutoSendGenCmd	170	Covered	T6,T4,T10
AutoSendReseedCmd	184	Covered	T6,T10,T29
BootCaptGenCnt	106	Covered	T33,T43,T93
BootDone	126	Covered	T33,T43,T93
BootGenAckWait	116	Covered	T33,T43,T93
BootInsAckWait	102	Covered	T33,T43,T93
BootLoadGen	98	Covered	T33,T43,T93
BootLoadIns	88	Covered	T33,T43,T93
BootPulse	121	Covered	T33,T43,T93
BootSendGenCmd	111	Covered	T33,T43,T93
Error	206	Covered	T3,T4,T5
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T2,T17

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T6,T10,T29
AutoAckWait->Error	206	Covered	T4,T11,T44
AutoAckWait->Idle	229	Covered	T6,T10,T29
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T6,T4,T10
AutoCaptGenCnt->Error	206	Covered	T164,T165,T166
AutoCaptGenCnt->Idle	229	Covered	T28,T80,T167
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T6,T10,T29
AutoCaptReseedCnt->Error	206	Covered	T168,T169
AutoCaptReseedCnt->Idle	229	Covered	T34,T82,T170
AutoDispatch->AutoCaptGenCnt	162	Covered	T6,T4,T10
AutoDispatch->AutoCaptReseedCnt	160	Covered	T6,T10,T29
AutoDispatch->Error	206	Covered	T3,T171,T172
AutoDispatch->Idle	157	Covered	T7,T8,T76
AutoFirstAckWait->AutoDispatch	142	Covered	T3,T6,T4
AutoFirstAckWait->Error	206	Covered	T173
AutoFirstAckWait->Idle	229	Covered	T29,T26,T174
AutoLoadIns->AutoFirstAckWait	135	Covered	T3,T6,T4
AutoLoadIns->Error	206	Covered	T113,T175,T176
AutoLoadIns->Idle	229	Covered	T177,T178,T179
AutoSendGenCmd->AutoAckWait	177	Covered	T6,T4,T10
AutoSendGenCmd->Error	206	Covered	T180,T181,T182
AutoSendGenCmd->Idle	229	Covered	T6,T37,T88
AutoSendReseedCmd->AutoAckWait	191	Covered	T6,T10,T29
AutoSendReseedCmd->Error	206	Covered	T46,T183,T184
AutoSendReseedCmd->Idle	229	Covered	T161,T185,T186
BootCaptGenCnt->BootSendGenCmd	111	Covered	T33,T43,T93
BootCaptGenCnt->Error	206	Covered	T187,T188,T189
BootCaptGenCnt->Idle	229	Covered	T109,T79,T190
BootDone->Error	206	Covered	T191,T192,T193
BootDone->Idle	229	Covered	T125,T126,T128
BootGenAckWait->BootPulse	121	Covered	T33,T43,T93
BootGenAckWait->Error	206	Covered	T194,T195,T196
BootGenAckWait->Idle	229	Covered	T43,T89,T133
BootInsAckWait->BootCaptGenCnt	106	Covered	T33,T43,T93
BootInsAckWait->Error	206	Covered	T74,T49,T50
BootInsAckWait->Idle	229	Covered	T121,T122,T197
BootLoadGen->BootInsAckWait	102	Covered	T33,T43,T93
BootLoadGen->Error	206	Covered	T198
BootLoadGen->Idle	229	Covered	T93,T25,T108
BootLoadIns->BootLoadGen	98	Covered	T33,T43,T93
BootLoadIns->Error	206	Covered	T199,T200
BootLoadIns->Idle	229	Covered	T33,T35,T58
BootPulse->BootDone	126	Covered	T33,T43,T93
BootPulse->Error	206	Covered	T48,T201
BootPulse->Idle	229	Covered	T138,T131,T136
BootSendGenCmd->BootGenAckWait	116	Covered	T33,T43,T93
BootSendGenCmd->Error	206	Covered	T202
BootSendGenCmd->Idle	229	Covered	T106,T203,T204
Idle->AutoLoadIns	90	Covered	T3,T6,T4
Idle->BootLoadIns	88	Covered	T33,T43,T93
Idle->Error	206	Covered	T22,T23,T24
Idle->SWPortMode	93	Covered	T1,T2,T17
SWPortMode->Error	206	Covered	T12,T45,T110
SWPortMode->Idle	229	Covered	T1,T2,T17

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T4
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T109,T121,T122
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T43,T93
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T6,T4
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T6,T4
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T6,T4
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T6,T4
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T10,T29
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T6,T4,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T6,T10,T29
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T6,T4
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T4,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T10,T29
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T10,T29
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T10,T29
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T10,T7
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T72,T111

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	238132407	126292	0	0
FpvSecCmErrorStEscalate_A	238132407	127137	0	0
u_state_regs_A	238099810	237964587	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	126292	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1020	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	323	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	127137	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1021	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	324	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238099810	237964587	0	0
T1	341	194	0	0
T2	220160	220150	0	0
T3	634	500	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0