Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T17
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T138,T137
AckPls->Error	99	Covered	T5,T11,T237
AckPls->Idle	85	Covered	T1,T2,T17
DataWait->AckPls	80	Covered	T1,T2,T17
DataWait->Disabled	107	Covered	T6,T37,T80
DataWait->Error	99	Covered	T3,T4,T48
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T3,T4,T5

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T17
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T17
DataWait	-	-	-	0	Covered	T2,T3,T17
AckPls	-	-	-	-	Covered	T1,T2,T17
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T3,T74,T110

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1666926849	895494	0	0
FpvSecCmErrorStEscalate_A	1666926849	901409	0	0
u_state_regs_A	1666894252	1665947691	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1666926849	895494	0	0
T3	5334	2400	0	0
T4	15890	7504	0	0
T5	0	7490	0	0
T6	11893	0	0	0
T11	0	7574	0	0
T12	0	2506	0	0
T16	9744	0	0	0
T17	4453631	0	0	0
T18	6916	0	0	0
T19	7161	0	0	0
T20	778148	0	0	0
T21	94591	0	0	0
T44	0	6454	0	0
T45	0	2653	0	0
T46	0	2821	0	0
T51	84602	0	0	0
T72	0	2611	0	0
T74	0	1581	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1666926849	901409	0	0
T3	5334	2407	0	0
T4	15890	7511	0	0
T5	0	7497	0	0
T6	11893	0	0	0
T11	0	7581	0	0
T12	0	2513	0	0
T16	9744	0	0	0
T17	4453631	0	0	0
T18	6916	0	0	0
T19	7161	0	0	0
T20	778148	0	0	0
T21	94591	0	0	0
T44	0	6461	0	0
T45	0	2660	0	0
T46	0	2828	0	0
T51	84602	0	0	0
T72	0	2618	0	0
T74	0	1588	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1666894252	1665947691	0	0
T1	2471	1442	0	0
T2	1541120	1541050	0	0
T3	5206	4268	0	0
T6	11893	11536	0	0
T16	9744	9079	0	0
T17	4453631	4453554	0	0
T18	6916	6314	0	0
T19	7161	6468	0	0
T20	778148	778141	0	0
T21	94591	89663	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T27,T28
DataWait	75	Covered	T6,T27,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T27,T28
DataWait->AckPls	80	Covered	T6,T27,T28
DataWait->Disabled	107	Covered	T6
DataWait->Error	99	Covered	T181,T172,T238
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T6,T27,T28
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T6,T27,T28
Idle	-	1	0	-	Covered	T6,T27,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T6,T27,T28
DataWait	-	-	-	0	Covered	T6,T27,T28
AckPls	-	-	-	-	Covered	T6,T27,T28
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	128242	0	0
FpvSecCmErrorStEscalate_A	238132407	129087	0	0
u_state_regs_A	238132407	237997184	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	128242	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	129087	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T29,T9,T30
DataWait	75	Covered	T29,T9,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T29,T9,T30
DataWait->AckPls	80	Covered	T29,T9,T30
DataWait->Disabled	107	Covered	T167,T239,T240
DataWait->Error	99	Covered	T49
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T29,T9,T30
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T29,T9,T30
Idle	-	1	0	-	Covered	T29,T9,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T29,T9,T30
DataWait	-	-	-	0	Covered	T29,T9,T30
AckPls	-	-	-	-	Covered	T29,T9,T30
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	128242	0	0
FpvSecCmErrorStEscalate_A	238132407	129087	0	0
u_state_regs_A	238132407	237997184	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	128242	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	129087	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T17,T19
DataWait	75	Covered	T2,T17,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T241,T242
AckPls->Idle	85	Covered	T2,T17,T19
DataWait->AckPls	80	Covered	T2,T17,T19
DataWait->Disabled	107	Covered	T122,T203,T243
DataWait->Error	99	Covered	T4,T244,T245
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T17,T19
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T5,T72,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T17,T19
Idle	-	1	0	-	Covered	T2,T17,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T17,T19
DataWait	-	-	-	0	Covered	T2,T17,T19
AckPls	-	-	-	-	Covered	T2,T17,T19
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T3,T74,T110

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	126042	0	0
FpvSecCmErrorStEscalate_A	238132407	126887	0	0
u_state_regs_A	238099810	237964587	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	126042	0	0
T3	762	300	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	183	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	126887	0	0
T3	762	301	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	184	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238099810	237964587	0	0
T1	341	194	0	0
T2	220160	220150	0	0
T3	634	500	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T5,T34
DataWait	75	Covered	T1,T3,T5
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T5,T11
AckPls->Idle	85	Covered	T1,T34,T35
DataWait->AckPls	80	Covered	T1,T5,T34
DataWait->Disabled	107	Covered	T37,T80,T79
DataWait->Error	99	Covered	T3,T246,T247
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T5
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T4,T72,T74

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T34,T35
Idle	-	1	0	-	Covered	T1,T3,T5
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T5,T34
DataWait	-	-	-	0	Covered	T3,T5,T34
AckPls	-	-	-	-	Covered	T1,T5,T34
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	128242	0	0
FpvSecCmErrorStEscalate_A	238132407	129087	0	0
u_state_regs_A	238132407	237997184	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	128242	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	129087	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T26,T14
DataWait	75	Covered	T25,T26,T14
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T237
AckPls->Idle	85	Covered	T25,T26,T14
DataWait->AckPls	80	Covered	T25,T26,T14
DataWait->Disabled	107	Covered	T121,T248,T249
DataWait->Error	99	Covered	T48,T192,T250
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T26,T14
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T26,T14
Idle	-	1	0	-	Covered	T25,T26,T14
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T26,T14
DataWait	-	-	-	0	Covered	T25,T26,T14
AckPls	-	-	-	-	Covered	T25,T26,T14
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	128242	0	0
FpvSecCmErrorStEscalate_A	238132407	129087	0	0
u_state_regs_A	238132407	237997184	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	128242	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	129087	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T31,T32
DataWait	75	Covered	T7,T31,T32
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T137
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T31,T32
DataWait->AckPls	80	Covered	T7,T31,T32
DataWait->Disabled	107	Covered	T106,T251,T252
DataWait->Error	99	Covered	T253,T165
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T31,T32
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T31,T32
Idle	-	1	0	-	Covered	T7,T31,T32
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T31,T32
DataWait	-	-	-	0	Covered	T7,T31,T32
AckPls	-	-	-	-	Covered	T7,T31,T32
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	128242	0	0
FpvSecCmErrorStEscalate_A	238132407	129087	0	0
u_state_regs_A	238132407	237997184	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	128242	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	129087	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T6,T10,T33
DataWait	75	Covered	T6,T10,T33
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T138
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T6,T10,T33
DataWait->AckPls	80	Covered	T6,T10,T33
DataWait->Disabled	107	Covered	T43,T28,T109
DataWait->Error	99	Covered	T72,T45,T254
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T21,T33,T52
EndPointClear->Error	99	Covered	T113,T22,T63
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T6,T10,T33
Idle->Disabled	107	Covered	T1,T2,T17
Idle->Error	99	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T6,T10,T33
Idle	-	1	0	-	Covered	T6,T10,T33
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T6,T10,T33
DataWait	-	-	-	0	Covered	T6,T10,T33
AckPls	-	-	-	-	Covered	T6,T10,T33
Error	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T1,T6,T10
0	0	Covered	T1,T2,T3

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Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	238132407	128242	0	0
FpvSecCmErrorStEscalate_A	238132407	129087	0	0
u_state_regs_A	238132407	237997184	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	128242	0	0
T3	762	350	0	0
T4	2270	1072	0	0
T5	0	1070	0	0
T6	1699	0	0	0
T11	0	1082	0	0
T12	0	358	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	922	0	0
T45	0	379	0	0
T46	0	403	0	0
T51	12086	0	0	0
T72	0	373	0	0
T74	0	233	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	129087	0	0
T3	762	351	0	0
T4	2270	1073	0	0
T5	0	1071	0	0
T6	1699	0	0	0
T11	0	1083	0	0
T12	0	359	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	923	0	0
T45	0	380	0	0
T46	0	404	0	0
T51	12086	0	0	0
T72	0	374	0	0
T74	0	234	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0