Group : tb.dut.u_edn_cov_if::edn_alert_cg
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Group : tb.dut.u_edn_cov_if::edn_alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_alert_cg 100.00 1 100 1 64 64




Group Instance : edn_alert_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_alert_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00


Variables for Group Instance edn_alert_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_recov_alert_cg 5 0 5 100.00 100 1 1 0


Summary for Variable cp_recov_alert_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_recov_alert_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[edn_enable_field_alert] 13 1 T18 1 T121 1 T255 1
auto[boot_req_mode_field_alert] 13 1 T16 1 T84 1 T76 1
auto[auto_req_mode_field_alert] 15 1 T254 1 T256 1 T47 1
auto[cmd_fifo_rst_field_alert] 9 1 T17 1 T257 1 T258 1
auto[edn_bus_cmp_alert] 50 1 T16 1 T17 1 T18 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%