Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.91	90.91	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	90.91	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.91	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	3	18	85.71

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	3	18	85.71	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	63	1			T21	1		T29	1		T69	1
auto_req_mode	63	1			T8	1		T9	1		T13	1
sw_mode	2780	1			T2	1		T20	9		T60	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

108

1

T2

1

T21

1

T8

1

single

40

1

T29

1

T69

1

T34

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1493	1			T2	1		T20	9		T21	1
auto[2]	91	1			T263	7		T195	81		T74	1
auto[3]	3	1			T264	1		T265	1		T266	1
auto[4]	115	1			T196	41		T267	9		T268	3
auto[5]	14	1			T75	1		T269	4		T270	1
auto[6]	99	1			T38	1		T238	63		T271	5
auto[7]	1091	1			T66	9		T101	14		T102	73

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	3	18	85.71	3

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[3]]	[auto_req_mode]	0	1	1
[auto[4]]	[boot_req_mode]	0	1	1
[auto[6]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	51	1			T21	1		T29	1		T69	1
auto[1]	auto_req_mode	56	1			T8	1		T9	1		T13	1
auto[1]	sw_mode	1386	1			T2	1		T20	9		T60	1
auto[2]	boot_req_mode	2	1			T74	1		T272	1		-	-
auto[2]	auto_req_mode	1	1			T273	1		-	-		-	-
auto[2]	sw_mode	88	1			T263	7		T195	81		-	-
auto[3]	boot_req_mode	2	1			T265	1		T266	1		-	-
auto[3]	sw_mode	1	1			T264	1		-	-		-	-
auto[4]	auto_req_mode	1	1			T274	1		-	-		-	-
auto[4]	sw_mode	114	1			T196	41		T267	9		T268	3
auto[5]	boot_req_mode	2	1			T75	1		T270	1		-	-
auto[5]	auto_req_mode	1	1			T11	1		-	-		-	-
auto[5]	sw_mode	11	1			T269	4		T275	7		-	-
auto[6]	boot_req_mode	2	1			T38	1		T276	1		-	-
auto[6]	sw_mode	97	1			T238	63		T271	5		T277	29
auto[7]	boot_req_mode	4	1			T43	1		T42	1		T278	1
auto[7]	auto_req_mode	4	1			T111	1		T279	1		T12	1
auto[7]	sw_mode	1083	1			T66	9		T101	14		T102	73