Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	597573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5411830

1

T1

3

T2

10

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1552315	1			T1	62		T2	36		T3	18
values[0x0]	2065897	1			T1	3		T2	6		T3	6
values[0x1]	2391191	1			T1	2		T2	4		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	286260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5723143

1

T1

24

T2

25

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23180	1			T20	1		T29	5		T15	1
valid_sources[0x01]	23370	1			T20	1		T52	1		T15	2
valid_sources[0x02]	24128	1			T8	1		T63	3		T24	313
valid_sources[0x03]	23988	1			T20	1		T60	1		T15	1
valid_sources[0x04]	21909	1			T1	1		T5	2		T20	1
valid_sources[0x05]	24250	1			T1	3		T24	334		T66	1
valid_sources[0x06]	24285	1			T20	1		T24	300		T66	5
valid_sources[0x07]	23050	1			T5	1		T8	1		T24	310
valid_sources[0x08]	24278	1			T2	1		T20	9		T69	1
valid_sources[0x09]	24168	1			T5	1		T8	2		T24	311
valid_sources[0x0a]	24620	1			T1	3		T20	2		T24	286
valid_sources[0x0b]	22148	1			T24	304		T66	3		T25	102
valid_sources[0x0c]	23067	1			T5	1		T20	7		T52	1
valid_sources[0x0d]	22781	1			T20	2		T24	296		T66	4
valid_sources[0x0e]	24669	1			T2	1		T20	2		T51	2
valid_sources[0x0f]	23467	1			T5	1		T20	1		T15	1
valid_sources[0x10]	21807	1			T2	1		T5	1		T20	1
valid_sources[0x11]	23601	1			T2	1		T5	1		T16	1
valid_sources[0x12]	23667	1			T5	2		T9	5		T15	2
valid_sources[0x13]	22789	1			T5	2		T20	1		T24	275
valid_sources[0x14]	23686	1			T2	1		T15	1		T24	282
valid_sources[0x15]	23439	1			T20	1		T15	1		T24	321
valid_sources[0x16]	24866	1			T5	5		T20	1		T9	6
valid_sources[0x17]	23834	1			T5	1		T20	1		T52	1
valid_sources[0x18]	24087	1			T1	4		T20	6		T51	1
valid_sources[0x19]	22569	1			T20	3		T15	1		T63	1
valid_sources[0x1a]	24288	1			T1	3		T20	1		T15	2
valid_sources[0x1b]	25741	1			T5	1		T15	1		T24	321
valid_sources[0x1c]	23125	1			T20	1		T8	1		T64	1
valid_sources[0x1d]	22775	1			T20	2		T15	1		T24	293
valid_sources[0x1e]	24153	1			T5	1		T20	1		T52	3
valid_sources[0x1f]	23679	1			T20	5		T15	2		T24	315
valid_sources[0x20]	24264	1			T16	1		T52	3		T8	2
valid_sources[0x21]	24512	1			T5	3		T20	1		T8	1
valid_sources[0x22]	23868	1			T2	2		T5	2		T52	1
valid_sources[0x23]	23505	1			T5	1		T20	2		T8	1
valid_sources[0x24]	24102	1			T20	8		T51	2		T9	19
valid_sources[0x25]	23208	1			T5	1		T20	3		T52	1
valid_sources[0x26]	23970	1			T20	4		T29	1		T24	327
valid_sources[0x27]	24253	1			T16	1		T20	4		T15	2
valid_sources[0x28]	23058	1			T20	2		T15	2		T24	265
valid_sources[0x29]	23492	1			T5	1		T20	3		T24	297
valid_sources[0x2a]	23878	1			T5	4		T20	2		T52	1
valid_sources[0x2b]	23218	1			T20	4		T60	1		T24	290
valid_sources[0x2c]	24146	1			T16	1		T20	2		T64	1
valid_sources[0x2d]	25433	1			T20	1		T15	5		T64	2
valid_sources[0x2e]	24283	1			T1	4		T2	1		T5	3
valid_sources[0x2f]	23916	1			T5	1		T52	1		T64	1
valid_sources[0x30]	23253	1			T20	1		T51	1		T15	2
valid_sources[0x31]	22904	1			T15	1		T24	333		T66	2
valid_sources[0x32]	24201	1			T5	3		T20	1		T8	1
valid_sources[0x33]	23330	1			T20	1		T60	1		T15	2
valid_sources[0x34]	23674	1			T5	2		T20	3		T15	1
valid_sources[0x35]	22911	1			T5	1		T20	4		T8	1
valid_sources[0x36]	23309	1			T20	4		T52	1		T60	1
valid_sources[0x37]	23072	1			T5	1		T8	2		T64	2
valid_sources[0x38]	23890	1			T5	1		T16	1		T19	4
valid_sources[0x39]	23130	1			T5	1		T20	3		T15	2
valid_sources[0x3a]	23799	1			T1	1		T5	2		T59	51
valid_sources[0x3b]	21881	1			T24	301		T66	3		T25	116
valid_sources[0x3c]	24700	1			T20	2		T15	1		T64	1
valid_sources[0x3d]	23181	1			T5	1		T20	1		T15	3
valid_sources[0x3e]	24103	1			T5	1		T60	3		T8	1
valid_sources[0x3f]	22933	1			T1	1		T2	1		T20	1
valid_sources[0x40]	23823	1			T2	1		T5	2		T15	1
valid_sources[0x41]	22504	1			T5	1		T15	1		T24	278
valid_sources[0x42]	22638	1			T60	1		T64	1		T24	285
valid_sources[0x43]	22335	1			T5	1		T16	1		T20	4
valid_sources[0x44]	23204	1			T5	1		T20	2		T8	2
valid_sources[0x45]	23405	1			T24	348		T66	3		T25	122
valid_sources[0x46]	24323	1			T5	2		T15	2		T24	301
valid_sources[0x47]	23134	1			T5	1		T15	1		T24	278
valid_sources[0x48]	23218	1			T2	1		T5	1		T16	1
valid_sources[0x49]	23823	1			T5	2		T20	1		T51	1
valid_sources[0x4a]	22894	1			T3	2		T20	1		T15	1
valid_sources[0x4b]	24022	1			T5	1		T60	1		T15	2
valid_sources[0x4c]	23867	1			T15	3		T24	275		T66	1
valid_sources[0x4d]	23148	1			T16	3		T52	2		T15	3
valid_sources[0x4e]	22221	1			T3	4		T20	3		T15	1
valid_sources[0x4f]	24677	1			T2	2		T16	1		T20	2
valid_sources[0x50]	24630	1			T1	2		T5	1		T68	1
valid_sources[0x51]	23393	1			T16	1		T20	5		T68	1
valid_sources[0x52]	23153	1			T5	1		T20	5		T24	283
valid_sources[0x53]	24084	1			T1	4		T2	1		T5	1
valid_sources[0x54]	23349	1			T5	1		T20	3		T24	280
valid_sources[0x55]	24323	1			T3	1		T5	1		T20	3
valid_sources[0x56]	22931	1			T1	2		T20	4		T21	5
valid_sources[0x57]	23096	1			T16	1		T20	2		T68	1
valid_sources[0x58]	24379	1			T1	1		T9	8		T69	1
valid_sources[0x59]	23884	1			T16	2		T20	1		T52	3
valid_sources[0x5a]	22004	1			T2	1		T5	1		T20	1
valid_sources[0x5b]	23299	1			T1	1		T20	1		T24	317
valid_sources[0x5c]	23624	1			T8	2		T15	1		T24	280
valid_sources[0x5d]	22732	1			T20	2		T52	2		T15	2
valid_sources[0x5e]	22444	1			T20	3		T9	2		T15	2
valid_sources[0x5f]	23747	1			T2	1		T52	2		T8	3
valid_sources[0x60]	23492	1			T69	1		T64	1		T24	297
valid_sources[0x61]	23907	1			T20	2		T24	312		T66	1
valid_sources[0x62]	22910	1			T20	1		T24	264		T66	2
valid_sources[0x63]	22743	1			T16	1		T15	1		T41	10
valid_sources[0x64]	23707	1			T5	2		T28	4		T52	1
valid_sources[0x65]	22923	1			T15	3		T24	294		T66	2
valid_sources[0x66]	21888	1			T16	1		T52	2		T24	284
valid_sources[0x67]	22990	1			T2	2		T20	3		T15	3
valid_sources[0x68]	22756	1			T2	1		T3	1		T16	1
valid_sources[0x69]	24659	1			T14	16		T5	1		T24	322
valid_sources[0x6a]	22438	1			T20	4		T60	1		T15	1
valid_sources[0x6b]	23909	1			T20	3		T15	3		T24	341
valid_sources[0x6c]	23962	1			T5	2		T24	308		T66	1
valid_sources[0x6d]	23028	1			T2	1		T24	271		T66	2
valid_sources[0x6e]	23969	1			T5	1		T19	5		T20	2
valid_sources[0x6f]	22586	1			T9	1		T15	2		T24	295
valid_sources[0x70]	24121	1			T16	1		T20	1		T52	1
valid_sources[0x71]	22804	1			T20	1		T68	3		T9	3
valid_sources[0x72]	22459	1			T15	1		T63	2		T24	280
valid_sources[0x73]	23734	1			T2	1		T64	1		T24	286
valid_sources[0x74]	23453	1			T20	3		T52	2		T15	2
valid_sources[0x75]	22618	1			T1	1		T68	12		T24	278
valid_sources[0x76]	23442	1			T2	2		T15	3		T24	274
valid_sources[0x77]	22606	1			T1	2		T4	6		T20	8
valid_sources[0x78]	23808	1			T20	5		T52	2		T15	2
valid_sources[0x79]	23645	1			T5	1		T20	8		T28	3
valid_sources[0x7a]	22195	1			T16	1		T8	1		T15	4
valid_sources[0x7b]	22658	1			T5	2		T52	1		T15	1
valid_sources[0x7c]	23949	1			T5	1		T20	6		T8	1
valid_sources[0x7d]	23996	1			T5	3		T24	323		T66	3
valid_sources[0x7e]	23545	1			T20	3		T24	307		T25	117
valid_sources[0x7f]	23467	1			T3	6		T24	308		T66	2
valid_sources[0x80]	23247	1			T20	6		T64	1		T24	313

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1363895

1

T1

2

T2

2

T3

1

values[0x0]

all_enables

biggest_size

2024619

1

T1

1

T2

6

T3

2

values[0x1]

all_enables

biggest_size

2023316

1

T2

2

T3

2

T14

2