Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	0	40	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	0	40	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1502	1			T2	1		T20	4		T8	6
non_zero_bins[1]	1153	1			T20	5		T24	7		T66	4
zero	6878	1			T2	2		T3	2		T4	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	2776	1			T2	1		T20	9		T60	1
gen	3380	1			T2	1		T3	1		T14	2
res	187	1			T8	4		T9	2		T13	3
ins	3190	1			T2	1		T3	1		T4	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6831

1

T2

1

T3

2

T4

1

mubi_true

2702

1

T2

2

T14

1

T16

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

4817

1

T2

3

T3

2

T14

2

pass

4716

1

T4

1

T14

2

T20

14

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	0	40	100.00
Automatically Generated Cross Bins	40	0	40	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	1061	1			T2	1		T20	3		T68	1
uni	zero	fail	mubi_true	330	1			T20	2		T60	1		T64	1
uni	zero	pass	mubi_false	1039	1			T20	4		T24	12		T66	6
uni	zero	pass	mubi_true	346	1			T24	5		T25	1		T79	4
gen	non_zero_bins[0]	fail	mubi_false	192	1			T20	1		T9	1		T24	1
gen	non_zero_bins[0]	fail	mubi_true	186	1			T2	1		T8	1		T24	1
gen	non_zero_bins[0]	pass	mubi_false	205	1			T20	2		T9	1		T79	2
gen	non_zero_bins[0]	pass	mubi_true	161	1			T8	1		T24	2		T137	1
gen	non_zero_bins[1]	fail	mubi_false	139	1			T24	1		T79	1		T70	1
gen	non_zero_bins[1]	fail	mubi_true	144	1			T66	2		T79	1		T39	1
gen	non_zero_bins[1]	pass	mubi_false	152	1			T20	2		T24	2		T66	1
gen	non_zero_bins[1]	pass	mubi_true	138	1			T79	1		T39	1		T31	2
gen	zero	fail	mubi_false	857	1			T3	1		T14	1		T20	2
gen	zero	fail	mubi_true	193	1			T16	2		T28	1		T63	2
gen	zero	pass	mubi_false	837	1			T14	1		T20	2		T52	1
gen	zero	pass	mubi_true	176	1			T24	1		T17	2		T34	1
res	non_zero_bins[0]	fail	mubi_false	12	1			T8	2		T98	2		T10	2
res	non_zero_bins[0]	fail	mubi_true	27	1			T9	1		T13	2		T44	3
res	non_zero_bins[0]	pass	mubi_false	19	1			T8	2		T98	3		T140	3
res	non_zero_bins[0]	pass	mubi_true	26	1			T9	1		T13	1		T44	1
res	non_zero_bins[1]	fail	mubi_false	7	1			T31	1		T99	1		T284	2
res	non_zero_bins[1]	fail	mubi_true	15	1			T37	1		T33	1		T138	2
res	non_zero_bins[1]	pass	mubi_false	14	1			T144	3		T31	1		T99	1
res	non_zero_bins[1]	pass	mubi_true	24	1			T37	1		T33	2		T91	2
res	zero	fail	mubi_false	8	1			T39	2		T37	1		T119	1
res	zero	fail	mubi_true	17	1			T33	1		T40	2		T85	3
res	zero	pass	mubi_false	6	1			T39	3		T37	1		T119	1
res	zero	pass	mubi_true	12	1			T163	3		T120	1		T105	1
ins	non_zero_bins[0]	fail	mubi_false	172	1			T24	1		T66	1		T13	1
ins	non_zero_bins[0]	fail	mubi_true	170	1			T20	1		T9	1		T24	1
ins	non_zero_bins[0]	pass	mubi_false	169	1			T24	2		T66	1		T79	1
ins	non_zero_bins[0]	pass	mubi_true	163	1			T79	1		T31	1		T33	1
ins	non_zero_bins[1]	fail	mubi_false	114	1			T20	1		T24	2		T79	2
ins	non_zero_bins[1]	fail	mubi_true	143	1			T20	1		T24	1		T79	1
ins	non_zero_bins[1]	pass	mubi_false	130	1			T24	1		T13	1		T37	1
ins	non_zero_bins[1]	pass	mubi_true	133	1			T20	1		T66	1		T70	2
ins	zero	fail	mubi_false	886	1			T3	1		T14	1		T20	2
ins	zero	fail	mubi_true	144	1			T2	1		T16	1		T28	1
ins	zero	pass	mubi_false	812	1			T4	1		T20	2		T59	1
ins	zero	pass	mubi_true	154	1			T14	1		T20	1		T28	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded