Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00		94.44	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.89	100.00	100.00		94.44	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00		94.44	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00		94.44	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T14,T21,T28
1	1	0	1	Covered	T14,T21,T28
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T3,T4

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T29,T69
1	1	Covered	T14,T21,T28

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T13
1	1	Covered	T5,T8,T9

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	51	94.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T8,T9,T13
AutoCaptGenCnt	162	Covered	T8,T9,T13
AutoCaptReseedCnt	160	Covered	T8,T9,T13
AutoDispatch	142	Covered	T8,T9,T13
AutoFirstAckWait	135	Covered	T8,T9,T13
AutoLoadIns	90	Covered	T5,T8,T9
AutoSendGenCmd	170	Covered	T8,T9,T13
AutoSendReseedCmd	184	Covered	T8,T9,T13
BootCaptGenCnt	106	Covered	T14,T21,T28
BootDone	126	Covered	T14,T21,T28
BootGenAckWait	116	Covered	T14,T21,T28
BootInsAckWait	102	Covered	T14,T21,T28
BootLoadGen	98	Covered	T14,T21,T28
BootLoadIns	88	Covered	T14,T21,T28
BootPulse	121	Covered	T14,T21,T28
BootSendGenCmd	111	Covered	T14,T21,T28
Error	206	Covered	T1,T3,T4
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T8,T9,T13
AutoAckWait->Error	206	Covered	T48,T154,T155
AutoAckWait->Idle	229	Covered	T8,T9,T13
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T8,T9,T13
AutoCaptGenCnt->Error	206	Not Covered
AutoCaptGenCnt->Idle	229	Covered	T37,T33,T40
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T8,T9,T13
AutoCaptReseedCnt->Error	206	Covered	T156
AutoCaptReseedCnt->Idle	229	Covered	T106,T157
AutoDispatch->AutoCaptGenCnt	162	Covered	T8,T9,T13
AutoDispatch->AutoCaptReseedCnt	160	Covered	T8,T9,T13
AutoDispatch->Error	206	Covered	T158,T159,T160
AutoDispatch->Idle	157	Covered	T13,T144,T91
AutoFirstAckWait->AutoDispatch	142	Covered	T8,T9,T13
AutoFirstAckWait->Error	206	Not Covered
AutoFirstAckWait->Idle	229	Covered	T39,T97,T161
AutoLoadIns->AutoFirstAckWait	135	Covered	T8,T9,T13
AutoLoadIns->Error	206	Covered	T5,T6,T162
AutoLoadIns->Idle	229	Covered	T49,T163,T164
AutoSendGenCmd->AutoAckWait	177	Covered	T8,T9,T13
AutoSendGenCmd->Error	206	Covered	T165
AutoSendGenCmd->Idle	229	Covered	T120,T166
AutoSendReseedCmd->AutoAckWait	191	Covered	T8,T9,T13
AutoSendReseedCmd->Error	206	Covered	T167,T168
AutoSendReseedCmd->Idle	229	Covered	T8,T9,T99
BootCaptGenCnt->BootSendGenCmd	111	Covered	T14,T21,T28
BootCaptGenCnt->Error	206	Covered	T53,T169,T170
BootCaptGenCnt->Idle	229	Covered	T95,T171,T172
BootDone->Error	206	Covered	T92,T55,T173
BootDone->Idle	229	Covered	T21,T35,T118
BootGenAckWait->BootPulse	121	Covered	T14,T21,T28
BootGenAckWait->Error	206	Covered	T174,T175
BootGenAckWait->Idle	229	Covered	T29,T50,T77
BootInsAckWait->BootCaptGenCnt	106	Covered	T14,T21,T28
BootInsAckWait->Error	206	Covered	T28,T58,T176
BootInsAckWait->Idle	229	Covered	T103,T110,T177
BootLoadGen->BootInsAckWait	102	Covered	T14,T21,T28
BootLoadGen->Error	206	Not Covered
BootLoadGen->Idle	229	Covered	T178,T179
BootLoadIns->BootLoadGen	98	Covered	T14,T21,T28
BootLoadIns->Error	206	Covered	T180,T56,T181
BootLoadIns->Idle	229	Covered	T34,T86,T82
BootPulse->BootDone	126	Covered	T14,T21,T28
BootPulse->Error	206	Covered	T14,T182,T183
BootPulse->Idle	229	Covered	T69,T116
BootSendGenCmd->BootGenAckWait	116	Covered	T14,T21,T28
BootSendGenCmd->Error	206	Covered	T184,T185,T186
BootSendGenCmd->Idle	229	Covered	T32,T187,T188
Idle->AutoLoadIns	90	Covered	T5,T8,T9
Idle->BootLoadIns	88	Covered	T14,T21,T28
Idle->Error	206	Covered	T15,T22,T23
Idle->SWPortMode	93	Covered	T1,T2,T3
SWPortMode->Error	206	Covered	T1,T3,T4
SWPortMode->Idle	229	Covered	T20,T27,T15

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T32,T103,T95
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T21,T28
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T13
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T13
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T13
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T13
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T91,T138,T139
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T13
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T63,T36

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	217412720	123687	0	0
FpvSecCmErrorStEscalate_A	217412720	124352	0	0
u_state_regs_A	217374283	217252418	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	123687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1060	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	124352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1061	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217374283	217252418	0	0
T1	562	420	0	0
T2	1474	1413	0	0
T3	612	495	0	0
T4	1661	1537	0	0
T5	1373	1201	0	0
T14	1801	1626	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0