Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T16
DataWait	75	Covered	T2,T3,T14
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T116
AckPls->Error	99	Covered	T7,T232,T45
AckPls->Idle	85	Covered	T2,T3,T16
DataWait->AckPls	80	Covered	T2,T3,T16
DataWait->Disabled	107	Covered	T32,T33,T40
DataWait->Error	99	Covered	T14,T63,T53
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T14
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T16
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T16
DataWait	-	-	-	0	Covered	T2,T14,T16
AckPls	-	-	-	-	Covered	T2,T3,T16
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1521889040	877509	0	0
FpvSecCmErrorStEscalate_A	1521889040	882164	0	0
u_state_regs_A	1521850603	1520997548	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521889040	877509	0	0
T1	5110	2883	0	0
T2	10318	0	0	0
T3	5285	2148	0	0
T4	12971	8154	0	0
T5	10976	4879	0	0
T14	14091	7861	0	0
T15	0	42707	0	0
T16	9394	0	0	0
T19	11732	0	0	0
T20	90405	0	0	0
T21	7861	0	0	0
T28	0	5830	0	0
T52	0	1966	0	0
T59	0	7706	0	0
T63	0	7770	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521889040	882164	0	0
T1	5110	2890	0	0
T2	10318	0	0	0
T3	5285	2155	0	0
T4	12971	8161	0	0
T5	10976	4886	0	0
T14	14091	7868	0	0
T15	0	43337	0	0
T16	9394	0	0	0
T19	11732	0	0	0
T20	90405	0	0	0
T21	7861	0	0	0
T28	0	5837	0	0
T52	0	1973	0	0
T59	0	7713	0	0
T63	0	7777	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521850603	1520997548	0	0
T1	4942	3948	0	0
T2	10318	9891	0	0
T3	5142	4323	0	0
T4	12779	11911	0	0
T5	10781	9577	0	0
T14	13879	12654	0	0
T16	9394	9009	0	0
T19	11732	11067	0	0
T20	90405	86135	0	0
T21	7861	7399	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T41,T13
DataWait	75	Covered	T27,T41,T13
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T41,T13
DataWait->AckPls	80	Covered	T27,T41,T13
DataWait->Disabled	107	Covered	T33,T120,T233
DataWait->Error	99	Covered	T234
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T41,T13
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T41,T13
Idle	-	1	0	-	Covered	T4,T27,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T41,T13
DataWait	-	-	-	0	Covered	T13,T33,T18
AckPls	-	-	-	-	Covered	T27,T41,T13
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T15,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	125687	0	0
FpvSecCmErrorStEscalate_A	217412720	126352	0	0
u_state_regs_A	217412720	217290855	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	125687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	126352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T16
DataWait	75	Covered	T2,T3,T14
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T232,T235,T236
AckPls->Idle	85	Covered	T2,T3,T16
DataWait->AckPls	80	Covered	T2,T3,T16
DataWait->Disabled	107	Covered	T237,T238,T239
DataWait->Error	99	Covered	T14,T63,T240
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T5,T15,T241
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T14
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T36,T30,T53

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T16
Idle	-	1	0	-	Covered	T2,T3,T14
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T16
DataWait	-	-	-	0	Covered	T2,T14,T16
AckPls	-	-	-	-	Covered	T2,T3,T16
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	123387	0	0
FpvSecCmErrorStEscalate_A	217412720	124052	0	0
u_state_regs_A	217374283	217252418	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	123387	0	0
T1	730	369	0	0
T2	1474	0	0	0
T3	755	264	0	0
T4	1853	1122	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	790	0	0
T52	0	238	0	0
T59	0	1058	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	124052	0	0
T1	730	370	0	0
T2	1474	0	0	0
T3	755	265	0	0
T4	1853	1123	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	791	0	0
T52	0	239	0	0
T59	0	1059	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217374283	217252418	0	0
T1	562	420	0	0
T2	1474	1413	0	0
T3	612	495	0	0
T4	1661	1537	0	0
T5	1373	1201	0	0
T14	1801	1626	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T29,T30,T44
DataWait	75	Covered	T29,T30,T53
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T242
AckPls->Idle	85	Covered	T29,T30,T44
DataWait->AckPls	80	Covered	T29,T30,T44
DataWait->Disabled	107	Covered	T87,T95,T188
DataWait->Error	99	Covered	T53,T173,T243
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T29,T30,T53
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T29,T30,T44
Idle	-	1	0	-	Covered	T28,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T29,T30,T44
DataWait	-	-	-	0	Covered	T29,T53,T44
AckPls	-	-	-	-	Covered	T29,T30,T44
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T15,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	125687	0	0
FpvSecCmErrorStEscalate_A	217412720	126352	0	0
u_state_regs_A	217412720	217290855	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	125687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	126352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T31,T32,T33
DataWait	75	Covered	T31,T32,T33
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T45,T244,T245
AckPls->Idle	85	Covered	T31,T32,T33
DataWait->AckPls	80	Covered	T31,T32,T33
DataWait->Disabled	107	Covered	T32,T150,T187
DataWait->Error	99	Covered	T182
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T31,T32,T33
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T31,T32,T33
Idle	-	1	0	-	Covered	T31,T32,T33
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T31,T32,T33
DataWait	-	-	-	0	Covered	T31,T32,T33
AckPls	-	-	-	-	Covered	T31,T32,T33
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T15,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	125687	0	0
FpvSecCmErrorStEscalate_A	217412720	126352	0	0
u_state_regs_A	217412720	217290855	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	125687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	126352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T34,T7,T35
DataWait	75	Covered	T34,T7,T35
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T7
AckPls->Idle	85	Covered	T34,T35,T40
DataWait->AckPls	80	Covered	T34,T7,T35
DataWait->Disabled	107	Covered	T40,T119,T110
DataWait->Error	99	Covered	T246,T48,T184
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T34,T7,T35
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T34,T35,T40
Idle	-	1	0	-	Covered	T34,T7,T35
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T34,T7,T35
DataWait	-	-	-	0	Covered	T34,T7,T35
AckPls	-	-	-	-	Covered	T34,T7,T35
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T15,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	125687	0	0
FpvSecCmErrorStEscalate_A	217412720	126352	0	0
u_state_regs_A	217412720	217290855	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	125687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	126352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T8,T39
DataWait	75	Covered	T21,T8,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T247
AckPls->Idle	85	Covered	T21,T8,T39
DataWait->AckPls	80	Covered	T21,T8,T39
DataWait->Disabled	107	Covered	T50,T122,T248
DataWait->Error	99	Covered	T92,T249,T250
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T21,T8,T39
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T8,T39
Idle	-	1	0	-	Covered	T21,T8,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T8,T39
DataWait	-	-	-	0	Covered	T21,T8,T39
AckPls	-	-	-	-	Covered	T21,T8,T39
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T15,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	125687	0	0
FpvSecCmErrorStEscalate_A	217412720	126352	0	0
u_state_regs_A	217412720	217290855	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	125687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	126352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T8,T27

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T37,T38,T43
DataWait	75	Covered	T36,T37,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T3,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T116
AckPls->Error	99	Covered	T153
AckPls->Idle	85	Covered	T37,T38,T43
DataWait->AckPls	80	Covered	T37,T38,T43
DataWait->Disabled	107	Covered	T251
DataWait->Error	99	Covered	T36,T252,T253
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T22,T23
EndPointClear->Disabled	107	Covered	T34,T72,T89
EndPointClear->Error	99	Covered	T1,T5,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T36,T37,T38
Idle->Disabled	107	Covered	T20,T21,T8
Idle->Error	99	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T37,T38,T43
Idle	-	1	0	-	Covered	T36,T37,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T37,T38,T43
DataWait	-	-	-	0	Covered	T36,T37,T38
AckPls	-	-	-	-	Covered	T37,T38,T43
Error	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	Covered	T15,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T21,T8,T27
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217412720	125687	0	0
FpvSecCmErrorStEscalate_A	217412720	126352	0	0
u_state_regs_A	217412720	217290855	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	125687	0	0
T1	730	419	0	0
T2	1474	0	0	0
T3	755	314	0	0
T4	1853	1172	0	0
T5	1568	697	0	0
T14	2013	1123	0	0
T15	0	6101	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	840	0	0
T52	0	288	0	0
T59	0	1108	0	0
T63	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	126352	0	0
T1	730	420	0	0
T2	1474	0	0	0
T3	755	315	0	0
T4	1853	1173	0	0
T5	1568	698	0	0
T14	2013	1124	0	0
T15	0	6191	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	0	841	0	0
T52	0	289	0	0
T59	0	1109	0	0
T63	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0