Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T16 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T16 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T3,T16 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T3,T16 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T3,T16 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T13 |
1 | 1 | Covered | T2,T3,T16 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T2,T3,T16 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T16,T20 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T16,T20 |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T16,T20 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T16,T20 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T16 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T3,T16 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T29,T69,T35 |
1 | 1 | Covered | T2,T3,T16 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T2,T3,T16 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T16 |
0 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1739301760 |
193970454 |
0 |
4504 |
T2 |
1474 |
1213 |
0 |
1 |
T3 |
755 |
324 |
0 |
1 |
T4 |
1853 |
0 |
0 |
1 |
T5 |
1568 |
0 |
0 |
1 |
T9 |
2288 |
1190 |
0 |
1 |
T13 |
1950 |
944 |
0 |
1 |
T14 |
2013 |
0 |
0 |
1 |
T16 |
1342 |
903 |
0 |
1 |
T18 |
0 |
1272 |
0 |
0 |
T19 |
1676 |
0 |
0 |
1 |
T20 |
12915 |
3622 |
0 |
1 |
T21 |
1123 |
0 |
0 |
1 |
T24 |
227829 |
0 |
0 |
1 |
T27 |
538 |
134 |
0 |
1 |
T28 |
1407 |
0 |
0 |
1 |
T29 |
1744 |
63 |
0 |
2 |
T30 |
708 |
0 |
0 |
1 |
T33 |
0 |
628 |
0 |
0 |
T38 |
0 |
1541 |
0 |
0 |
T40 |
0 |
694 |
0 |
0 |
T41 |
1433 |
631 |
0 |
1 |
T42 |
0 |
2537 |
0 |
0 |
T51 |
1023 |
0 |
0 |
1 |
T52 |
0 |
293 |
0 |
0 |
T59 |
0 |
1113 |
0 |
0 |
T60 |
0 |
794 |
0 |
0 |
T64 |
1126 |
0 |
0 |
1 |
T65 |
1455 |
0 |
0 |
1 |
T66 |
10451 |
0 |
0 |
1 |
T68 |
0 |
731 |
0 |
0 |
T69 |
0 |
72 |
0 |
0 |
T73 |
0 |
821 |
0 |
0 |
T74 |
0 |
1382 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1739301760 |
193970454 |
0 |
0 |
T2 |
1474 |
1213 |
0 |
0 |
T3 |
755 |
324 |
0 |
0 |
T4 |
1853 |
0 |
0 |
0 |
T5 |
1568 |
0 |
0 |
0 |
T9 |
2288 |
1190 |
0 |
0 |
T13 |
1950 |
944 |
0 |
0 |
T14 |
2013 |
0 |
0 |
0 |
T16 |
1342 |
903 |
0 |
0 |
T18 |
0 |
1272 |
0 |
0 |
T19 |
1676 |
0 |
0 |
0 |
T20 |
12915 |
3622 |
0 |
0 |
T21 |
1123 |
0 |
0 |
0 |
T24 |
227829 |
0 |
0 |
0 |
T27 |
538 |
134 |
0 |
0 |
T28 |
1407 |
0 |
0 |
0 |
T29 |
1744 |
63 |
0 |
0 |
T30 |
708 |
0 |
0 |
0 |
T33 |
0 |
628 |
0 |
0 |
T38 |
0 |
1541 |
0 |
0 |
T40 |
0 |
694 |
0 |
0 |
T41 |
1433 |
631 |
0 |
0 |
T42 |
0 |
2537 |
0 |
0 |
T51 |
1023 |
0 |
0 |
0 |
T52 |
0 |
293 |
0 |
0 |
T59 |
0 |
1113 |
0 |
0 |
T60 |
0 |
794 |
0 |
0 |
T64 |
1126 |
0 |
0 |
0 |
T65 |
1455 |
0 |
0 |
0 |
T66 |
10451 |
0 |
0 |
0 |
T68 |
0 |
731 |
0 |
0 |
T69 |
0 |
72 |
0 |
0 |
T73 |
0 |
821 |
0 |
0 |
T74 |
0 |
1382 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T16 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T16 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T2,T3,T16 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T3,T16 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T3,T16 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T13 |
1 | 1 | Covered | T2,T3,T16 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T2,T3,T16 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
12 |
85.71 |
TERNARY |
141 |
4 |
3 |
75.00 |
TERNARY |
146 |
3 |
2 |
66.67 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T16 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
59806 |
0 |
563 |
T2 |
1474 |
40 |
0 |
1 |
T3 |
755 |
29 |
0 |
1 |
T4 |
1853 |
0 |
0 |
1 |
T5 |
1568 |
0 |
0 |
1 |
T8 |
0 |
705 |
0 |
0 |
T9 |
0 |
680 |
0 |
0 |
T14 |
2013 |
0 |
0 |
1 |
T16 |
1342 |
65 |
0 |
1 |
T19 |
1676 |
0 |
0 |
1 |
T20 |
12915 |
0 |
0 |
1 |
T21 |
1123 |
876 |
0 |
1 |
T27 |
0 |
26 |
0 |
0 |
T28 |
1407 |
0 |
0 |
1 |
T29 |
0 |
614 |
0 |
0 |
T52 |
0 |
40 |
0 |
0 |
T59 |
0 |
12 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
59806 |
0 |
0 |
T2 |
1474 |
40 |
0 |
0 |
T3 |
755 |
29 |
0 |
0 |
T4 |
1853 |
0 |
0 |
0 |
T5 |
1568 |
0 |
0 |
0 |
T8 |
0 |
705 |
0 |
0 |
T9 |
0 |
680 |
0 |
0 |
T14 |
2013 |
0 |
0 |
0 |
T16 |
1342 |
65 |
0 |
0 |
T19 |
1676 |
0 |
0 |
0 |
T20 |
12915 |
0 |
0 |
0 |
T21 |
1123 |
876 |
0 |
0 |
T27 |
0 |
26 |
0 |
0 |
T28 |
1407 |
0 |
0 |
0 |
T29 |
0 |
614 |
0 |
0 |
T52 |
0 |
40 |
0 |
0 |
T59 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T16,T20 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T16,T20 |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T16,T20 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T16,T20 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T16 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T16 |
1 | 1 | Covered | T2,T3,T16 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T16 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T69 |
1 | 1 | Covered | T2,T3,T16 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T2,T3,T16 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T16 |
0 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T16 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
193687319 |
0 |
563 |
T2 |
1474 |
1213 |
0 |
1 |
T3 |
755 |
324 |
0 |
1 |
T4 |
1853 |
0 |
0 |
1 |
T5 |
1568 |
0 |
0 |
1 |
T9 |
0 |
1190 |
0 |
0 |
T14 |
2013 |
0 |
0 |
1 |
T16 |
1342 |
903 |
0 |
1 |
T19 |
1676 |
0 |
0 |
1 |
T20 |
12915 |
3622 |
0 |
1 |
T21 |
1123 |
0 |
0 |
1 |
T28 |
1407 |
0 |
0 |
1 |
T52 |
0 |
293 |
0 |
0 |
T59 |
0 |
1113 |
0 |
0 |
T60 |
0 |
794 |
0 |
0 |
T68 |
0 |
731 |
0 |
0 |
T69 |
0 |
72 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
193687319 |
0 |
0 |
T2 |
1474 |
1213 |
0 |
0 |
T3 |
755 |
324 |
0 |
0 |
T4 |
1853 |
0 |
0 |
0 |
T5 |
1568 |
0 |
0 |
0 |
T9 |
0 |
1190 |
0 |
0 |
T14 |
2013 |
0 |
0 |
0 |
T16 |
1342 |
903 |
0 |
0 |
T19 |
1676 |
0 |
0 |
0 |
T20 |
12915 |
3622 |
0 |
0 |
T21 |
1123 |
0 |
0 |
0 |
T28 |
1407 |
0 |
0 |
0 |
T52 |
0 |
293 |
0 |
0 |
T59 |
0 |
1113 |
0 |
0 |
T60 |
0 |
794 |
0 |
0 |
T68 |
0 |
731 |
0 |
0 |
T69 |
0 |
72 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T18,T40 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T18,T40 |
1 | 0 | Covered | T27,T41,T13 |
1 | 1 | Covered | T13,T18,T40 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T18,T40 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T27,T41,T13 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T27,T41,T13 |
1 | 1 | Covered | T27,T41,T13 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T41,T13 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T41,T13 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T41,T13 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T41,T13 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T27,T41,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T77,T145,T146 |
1 | 1 | Covered | T27,T41,T13 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T27,T41,T13 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T27,T41,T13 |
0 |
0 |
1 |
Covered |
T27,T41,T13 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T27,T41,T13 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T27,T41,T13 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
46337 |
0 |
563 |
T9 |
2288 |
0 |
0 |
1 |
T13 |
1950 |
944 |
0 |
1 |
T18 |
0 |
1272 |
0 |
0 |
T24 |
227829 |
0 |
0 |
1 |
T27 |
538 |
134 |
0 |
1 |
T29 |
872 |
0 |
0 |
1 |
T33 |
0 |
628 |
0 |
0 |
T38 |
0 |
792 |
0 |
0 |
T40 |
0 |
694 |
0 |
0 |
T41 |
1433 |
631 |
0 |
1 |
T42 |
0 |
1280 |
0 |
0 |
T51 |
1023 |
0 |
0 |
1 |
T64 |
1126 |
0 |
0 |
1 |
T65 |
1455 |
0 |
0 |
1 |
T66 |
10451 |
0 |
0 |
1 |
T73 |
0 |
821 |
0 |
0 |
T74 |
0 |
1382 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
46337 |
0 |
0 |
T9 |
2288 |
0 |
0 |
0 |
T13 |
1950 |
944 |
0 |
0 |
T18 |
0 |
1272 |
0 |
0 |
T24 |
227829 |
0 |
0 |
0 |
T27 |
538 |
134 |
0 |
0 |
T29 |
872 |
0 |
0 |
0 |
T33 |
0 |
628 |
0 |
0 |
T38 |
0 |
792 |
0 |
0 |
T40 |
0 |
694 |
0 |
0 |
T41 |
1433 |
631 |
0 |
0 |
T42 |
0 |
1280 |
0 |
0 |
T51 |
1023 |
0 |
0 |
0 |
T64 |
1126 |
0 |
0 |
0 |
T65 |
1455 |
0 |
0 |
0 |
T66 |
10451 |
0 |
0 |
0 |
T73 |
0 |
821 |
0 |
0 |
T74 |
0 |
1382 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T29,T44,T38 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T29,T44,T38 |
1 | 0 | Covered | T29,T30,T44 |
1 | 1 | Covered | T29,T44,T38 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T29,T44,T38 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T29,T30,T44 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T29,T30,T44 |
1 | 1 | Covered | T29,T30,T44 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T29,T30,T44 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T29,T30,T44 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T29,T30,T44 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T29,T30,T44 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T29,T30,T44 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T29,T87,T147 |
1 | 1 | Covered | T29,T30,T44 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T29,T30,T44 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T29,T30,T44 |
0 |
0 |
1 |
Covered |
T29,T30,T44 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T29,T30,T44 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T29,T30,T44 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
37672 |
0 |
563 |
T18 |
1776 |
0 |
0 |
1 |
T29 |
872 |
63 |
0 |
1 |
T30 |
708 |
294 |
0 |
1 |
T38 |
0 |
749 |
0 |
0 |
T42 |
0 |
1257 |
0 |
0 |
T43 |
0 |
1284 |
0 |
0 |
T44 |
1825 |
826 |
0 |
1 |
T53 |
1887 |
0 |
0 |
1 |
T79 |
19420 |
0 |
0 |
1 |
T84 |
0 |
1127 |
0 |
0 |
T85 |
0 |
1002 |
0 |
0 |
T86 |
0 |
578 |
0 |
0 |
T89 |
13522 |
0 |
0 |
1 |
T90 |
1065 |
0 |
0 |
1 |
T91 |
1410 |
0 |
0 |
1 |
T107 |
1198 |
0 |
0 |
1 |
T148 |
0 |
333 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
37672 |
0 |
0 |
T18 |
1776 |
0 |
0 |
0 |
T29 |
872 |
63 |
0 |
0 |
T30 |
708 |
294 |
0 |
0 |
T38 |
0 |
749 |
0 |
0 |
T42 |
0 |
1257 |
0 |
0 |
T43 |
0 |
1284 |
0 |
0 |
T44 |
1825 |
826 |
0 |
0 |
T53 |
1887 |
0 |
0 |
0 |
T79 |
19420 |
0 |
0 |
0 |
T84 |
0 |
1127 |
0 |
0 |
T85 |
0 |
1002 |
0 |
0 |
T86 |
0 |
578 |
0 |
0 |
T89 |
13522 |
0 |
0 |
0 |
T90 |
1065 |
0 |
0 |
0 |
T91 |
1410 |
0 |
0 |
0 |
T107 |
1198 |
0 |
0 |
0 |
T148 |
0 |
333 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T31,T32,T33 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T32,T33 |
1 | 0 | Covered | T31,T32,T33 |
1 | 1 | Covered | T31,T32,T33 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T31,T32,T33 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T31,T32,T33 |
1 | 1 | Covered | T31,T32,T33 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T32,T33 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T149,T150,T151 |
1 | 1 | Covered | T31,T32,T33 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T31,T32,T33 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T31,T32,T33 |
0 |
0 |
1 |
Covered |
T31,T32,T33 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T31,T32,T33 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T31,T32,T33 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
39064 |
0 |
563 |
T7 |
2785 |
0 |
0 |
1 |
T26 |
728064 |
0 |
0 |
1 |
T31 |
2306 |
1062 |
0 |
1 |
T32 |
767 |
513 |
0 |
1 |
T33 |
2402 |
549 |
0 |
1 |
T37 |
2319 |
0 |
0 |
1 |
T38 |
0 |
998 |
0 |
0 |
T43 |
0 |
1517 |
0 |
0 |
T45 |
0 |
1153 |
0 |
0 |
T46 |
0 |
993 |
0 |
0 |
T50 |
689 |
0 |
0 |
1 |
T97 |
0 |
797 |
0 |
0 |
T98 |
0 |
623 |
0 |
0 |
T99 |
0 |
627 |
0 |
0 |
T100 |
9284 |
0 |
0 |
1 |
T101 |
19502 |
0 |
0 |
1 |
T102 |
580552 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
39064 |
0 |
0 |
T7 |
2785 |
0 |
0 |
0 |
T26 |
728064 |
0 |
0 |
0 |
T31 |
2306 |
1062 |
0 |
0 |
T32 |
767 |
513 |
0 |
0 |
T33 |
2402 |
549 |
0 |
0 |
T37 |
2319 |
0 |
0 |
0 |
T38 |
0 |
998 |
0 |
0 |
T43 |
0 |
1517 |
0 |
0 |
T45 |
0 |
1153 |
0 |
0 |
T46 |
0 |
993 |
0 |
0 |
T50 |
689 |
0 |
0 |
0 |
T97 |
0 |
797 |
0 |
0 |
T98 |
0 |
623 |
0 |
0 |
T99 |
0 |
627 |
0 |
0 |
T100 |
9284 |
0 |
0 |
0 |
T101 |
19502 |
0 |
0 |
0 |
T102 |
580552 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T34,T35,T47 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T34,T35,T47 |
1 | 0 | Covered | T34,T35,T40 |
1 | 1 | Covered | T34,T35,T47 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T34,T35,T47 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T34,T7,T35 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T34,T7,T35 |
1 | 1 | Covered | T34,T35,T40 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T34,T7,T35 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T34,T35,T40 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T34,T35,T40 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T34,T7,T35 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T34,T7,T35 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T35,T104,T152 |
1 | 1 | Covered | T34,T7,T35 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T34,T7,T35 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T34,T7,T35 |
0 |
0 |
1 |
Covered |
T34,T35,T40 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T34,T35,T40 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T34,T7,T35 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
35577 |
0 |
563 |
T7 |
2785 |
1072 |
0 |
1 |
T30 |
708 |
0 |
0 |
1 |
T34 |
776 |
598 |
0 |
1 |
T35 |
0 |
86 |
0 |
0 |
T40 |
0 |
750 |
0 |
0 |
T42 |
0 |
1418 |
0 |
0 |
T47 |
0 |
823 |
0 |
0 |
T48 |
0 |
566 |
0 |
0 |
T50 |
689 |
0 |
0 |
1 |
T53 |
1887 |
0 |
0 |
1 |
T75 |
0 |
939 |
0 |
0 |
T79 |
19420 |
0 |
0 |
1 |
T101 |
19502 |
0 |
0 |
1 |
T102 |
580552 |
0 |
0 |
1 |
T104 |
0 |
100 |
0 |
0 |
T107 |
1198 |
0 |
0 |
1 |
T115 |
1219 |
0 |
0 |
1 |
T119 |
0 |
992 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
35577 |
0 |
0 |
T7 |
2785 |
1072 |
0 |
0 |
T30 |
708 |
0 |
0 |
0 |
T34 |
776 |
598 |
0 |
0 |
T35 |
0 |
86 |
0 |
0 |
T40 |
0 |
750 |
0 |
0 |
T42 |
0 |
1418 |
0 |
0 |
T47 |
0 |
823 |
0 |
0 |
T48 |
0 |
566 |
0 |
0 |
T50 |
689 |
0 |
0 |
0 |
T53 |
1887 |
0 |
0 |
0 |
T75 |
0 |
939 |
0 |
0 |
T79 |
19420 |
0 |
0 |
0 |
T101 |
19502 |
0 |
0 |
0 |
T102 |
580552 |
0 |
0 |
0 |
T104 |
0 |
100 |
0 |
0 |
T107 |
1198 |
0 |
0 |
0 |
T115 |
1219 |
0 |
0 |
0 |
T119 |
0 |
992 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T37,T38,T43 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T37,T38,T43 |
1 | 0 | Covered | T37,T38,T43 |
1 | 1 | Covered | T37,T38,T43 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T37,T38,T43 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T37,T38,T43 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T37,T38,T43 |
1 | 1 | Covered | T37,T38,T43 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T37,T38,T43 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T37,T38,T43 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T37,T38,T43 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T37,T38,T43 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T37,T38,T43 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T113,T114,T116 |
1 | 1 | Covered | T37,T38,T43 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T37,T38,T43 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T37,T38,T43 |
0 |
0 |
1 |
Covered |
T37,T38,T43 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T37,T38,T43 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T37,T38,T43 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
37271 |
0 |
563 |
T7 |
2785 |
0 |
0 |
1 |
T26 |
728064 |
0 |
0 |
1 |
T32 |
767 |
0 |
0 |
1 |
T33 |
2402 |
0 |
0 |
1 |
T37 |
2319 |
720 |
0 |
1 |
T38 |
0 |
722 |
0 |
0 |
T42 |
0 |
1240 |
0 |
0 |
T43 |
0 |
1446 |
0 |
0 |
T46 |
0 |
987 |
0 |
0 |
T49 |
0 |
906 |
0 |
0 |
T50 |
689 |
0 |
0 |
1 |
T80 |
0 |
918 |
0 |
0 |
T100 |
9284 |
0 |
0 |
1 |
T101 |
19502 |
0 |
0 |
1 |
T102 |
580552 |
0 |
0 |
1 |
T113 |
0 |
223 |
0 |
0 |
T114 |
0 |
215 |
0 |
0 |
T115 |
1219 |
0 |
0 |
1 |
T153 |
0 |
284 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
37271 |
0 |
0 |
T7 |
2785 |
0 |
0 |
0 |
T26 |
728064 |
0 |
0 |
0 |
T32 |
767 |
0 |
0 |
0 |
T33 |
2402 |
0 |
0 |
0 |
T37 |
2319 |
720 |
0 |
0 |
T38 |
0 |
722 |
0 |
0 |
T42 |
0 |
1240 |
0 |
0 |
T43 |
0 |
1446 |
0 |
0 |
T46 |
0 |
987 |
0 |
0 |
T49 |
0 |
906 |
0 |
0 |
T50 |
689 |
0 |
0 |
0 |
T80 |
0 |
918 |
0 |
0 |
T100 |
9284 |
0 |
0 |
0 |
T101 |
19502 |
0 |
0 |
0 |
T102 |
580552 |
0 |
0 |
0 |
T113 |
0 |
223 |
0 |
0 |
T114 |
0 |
215 |
0 |
0 |
T115 |
1219 |
0 |
0 |
0 |
T153 |
0 |
284 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T21,T8,T39 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T21,T8,T39 |
1 | 0 | Covered | T21,T8,T39 |
1 | 1 | Covered | T21,T8,T39 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T8,T39 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T21,T8,T39 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T21,T8,T39 |
1 | 1 | Covered | T21,T8,T39 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T8,T39 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T8,T39 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T8,T39 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T8,T39 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T21,T8,T39 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T21,T50,T118 |
1 | 1 | Covered | T21,T8,T39 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T21,T8,T39 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T21,T8,T39 |
0 |
0 |
1 |
Covered |
T21,T8,T39 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T21,T8,T39 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T21,T8,T39 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
27408 |
0 |
563 |
T8 |
2409 |
1257 |
0 |
1 |
T9 |
2288 |
0 |
0 |
1 |
T21 |
1123 |
70 |
0 |
1 |
T27 |
538 |
0 |
0 |
1 |
T28 |
1407 |
0 |
0 |
1 |
T39 |
0 |
798 |
0 |
0 |
T43 |
0 |
1214 |
0 |
0 |
T46 |
0 |
1172 |
0 |
0 |
T50 |
0 |
509 |
0 |
0 |
T51 |
1023 |
0 |
0 |
1 |
T52 |
711 |
0 |
0 |
1 |
T59 |
1908 |
0 |
0 |
1 |
T60 |
1026 |
0 |
0 |
1 |
T68 |
940 |
0 |
0 |
1 |
T88 |
0 |
1296 |
0 |
0 |
T118 |
0 |
123 |
0 |
0 |
T119 |
0 |
957 |
0 |
0 |
T120 |
0 |
733 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217412720 |
27408 |
0 |
0 |
T8 |
2409 |
1257 |
0 |
0 |
T9 |
2288 |
0 |
0 |
0 |
T21 |
1123 |
70 |
0 |
0 |
T27 |
538 |
0 |
0 |
0 |
T28 |
1407 |
0 |
0 |
0 |
T39 |
0 |
798 |
0 |
0 |
T43 |
0 |
1214 |
0 |
0 |
T46 |
0 |
1172 |
0 |
0 |
T50 |
0 |
509 |
0 |
0 |
T51 |
1023 |
0 |
0 |
0 |
T52 |
711 |
0 |
0 |
0 |
T59 |
1908 |
0 |
0 |
0 |
T60 |
1026 |
0 |
0 |
0 |
T68 |
940 |
0 |
0 |
0 |
T88 |
0 |
1296 |
0 |
0 |
T118 |
0 |
123 |
0 |
0 |
T119 |
0 |
957 |
0 |
0 |
T120 |
0 |
733 |
0 |
0 |