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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.90 97.11 83.08 80.69 50.66 90.48 95.24 76.08


Total test records in report: 729
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T505 /workspace/coverage/default/43.edn_alert.90116091249900599250407444282608691056414474998028861814792394432204885576086 Oct 18 01:31:03 PM PDT 23 Oct 18 01:31:06 PM PDT 23 32330757 ps
T506 /workspace/coverage/default/23.edn_alert_test.102071298958395204255660630017316823846353158944987589986244691517222503041993 Oct 18 01:30:54 PM PDT 23 Oct 18 01:30:55 PM PDT 23 16111390 ps
T507 /workspace/coverage/default/46.edn_genbits.91612965490048440332516174243785740093551131252296553066547043965744380278850 Oct 18 01:31:16 PM PDT 23 Oct 18 01:31:18 PM PDT 23 22643412 ps
T508 /workspace/coverage/default/4.edn_alert.50541414030394270357259161152900395254075619849802794363667533541794708611484 Oct 18 01:30:25 PM PDT 23 Oct 18 01:30:27 PM PDT 23 32330757 ps
T509 /workspace/coverage/default/45.edn_genbits.34002109460311972155582776836287855151168778075443642319249032131425516517933 Oct 18 01:31:01 PM PDT 23 Oct 18 01:31:02 PM PDT 23 22643412 ps
T510 /workspace/coverage/default/1.edn_intr.79675436629341420116782512115149723411517387188325730150053135735619007135715 Oct 18 01:30:03 PM PDT 23 Oct 18 01:30:05 PM PDT 23 22372583 ps
T511 /workspace/coverage/default/18.edn_stress_all.85242520958398100099460797412954208904276384379430933971930246574115762999015 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:23 PM PDT 23 299451483 ps
T512 /workspace/coverage/default/61.edn_err.14820282210312676517137699787661908717744715266524786521959787073403875153435 Oct 18 01:31:03 PM PDT 23 Oct 18 01:31:04 PM PDT 23 29871889 ps
T513 /workspace/coverage/default/2.edn_regwen.68503895569337736433034709226176434521811147438207156957879155710712303852671 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:20 PM PDT 23 19018470 ps
T514 /workspace/coverage/default/30.edn_disable.73483829751747535711662535871170885213661316486419691250849020427801155733665 Oct 18 01:30:25 PM PDT 23 Oct 18 01:30:31 PM PDT 23 19976788 ps
T515 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.7882268333315329676845810209723851247462589543778239855789799245465066084626 Oct 18 01:30:23 PM PDT 23 Oct 18 01:48:14 PM PDT 23 86880545330 ps
T516 /workspace/coverage/default/29.edn_disable_auto_req_mode.91955557071602819626290069862007025629361320388946955232277303758169377480991 Oct 18 01:30:32 PM PDT 23 Oct 18 01:30:43 PM PDT 23 30622451 ps
T517 /workspace/coverage/default/67.edn_err.108941919769066828490217227915094933311755058380214886737460432406823970679238 Oct 18 01:31:23 PM PDT 23 Oct 18 01:31:25 PM PDT 23 29871889 ps
T518 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.64437580566440791823917280128817192135997690347764323227299424465667880699694 Oct 18 01:29:45 PM PDT 23 Oct 18 01:46:55 PM PDT 23 86880545330 ps
T519 /workspace/coverage/default/43.edn_alert_test.37894240514196871792899619291495347038420034857585642019666316239414643433246 Oct 18 01:31:08 PM PDT 23 Oct 18 01:31:10 PM PDT 23 16111390 ps
T520 /workspace/coverage/default/26.edn_genbits.101029236639447178289405532803324112584643836819907711232619138698814994192580 Oct 18 01:30:50 PM PDT 23 Oct 18 01:30:51 PM PDT 23 22643412 ps
T521 /workspace/coverage/default/26.edn_disable_auto_req_mode.36225601922977675321946847414780417399773343374580865124090915272407928022600 Oct 18 01:30:38 PM PDT 23 Oct 18 01:30:39 PM PDT 23 30622451 ps
T522 /workspace/coverage/default/26.edn_disable.55087096310899772124484128640850560046139735743948192665742431012808061520535 Oct 18 01:30:18 PM PDT 23 Oct 18 01:30:20 PM PDT 23 19976788 ps
T523 /workspace/coverage/default/25.edn_disable.2264480112303573134078513143608527948279430370954233650351573423267803548602 Oct 18 01:30:43 PM PDT 23 Oct 18 01:30:44 PM PDT 23 19976788 ps
T524 /workspace/coverage/default/44.edn_alert_test.100966754581908190095255006166930726754821456095124096816417122631057826515588 Oct 18 01:31:16 PM PDT 23 Oct 18 01:31:18 PM PDT 23 16111390 ps
T525 /workspace/coverage/default/3.edn_disable_auto_req_mode.48267331942046223870263103184949743739344473490559916591384880396630924322755 Oct 18 01:29:48 PM PDT 23 Oct 18 01:29:50 PM PDT 23 30622451 ps
T526 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.25949673362868668579607233946198556527604808573539985486194032832810410862518 Oct 18 01:30:38 PM PDT 23 Oct 18 01:48:58 PM PDT 23 86880545330 ps
T527 /workspace/coverage/default/36.edn_smoke.46137913054484526537695995609778857705958586774126704523209253416067286938566 Oct 18 01:30:43 PM PDT 23 Oct 18 01:30:44 PM PDT 23 21768426 ps
T528 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.90746188018786361617475159488679810784562646728583227118304223012564030540008 Oct 18 01:30:29 PM PDT 23 Oct 18 01:48:48 PM PDT 23 86880545330 ps
T529 /workspace/coverage/default/38.edn_disable_auto_req_mode.3397126262041619428521371454132380557639462304020026834697910263949457369135 Oct 18 01:30:55 PM PDT 23 Oct 18 01:30:56 PM PDT 23 30622451 ps
T530 /workspace/coverage/default/32.edn_stress_all_with_rand_reset.8154670459789622329500056425342029079231861645513818329942520327423791193873 Oct 18 01:30:21 PM PDT 23 Oct 18 01:49:06 PM PDT 23 86880545330 ps
T531 /workspace/coverage/default/31.edn_genbits.74195130068379615972563283403252505900589363415234177141475025221538931351950 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:22 PM PDT 23 22643412 ps
T532 /workspace/coverage/default/15.edn_disable_auto_req_mode.65543022843942358649328820404535524760076964243611787370533520030155457001710 Oct 18 01:29:48 PM PDT 23 Oct 18 01:29:50 PM PDT 23 30622451 ps
T533 /workspace/coverage/default/34.edn_err.4819315702039261687979926048514385369387696052461921692760190142993044609011 Oct 18 01:30:27 PM PDT 23 Oct 18 01:30:28 PM PDT 23 29871889 ps
T534 /workspace/coverage/default/8.edn_regwen.17863748225820920588364874758829067893676684437870032628160863905557422999268 Oct 18 01:30:07 PM PDT 23 Oct 18 01:30:08 PM PDT 23 19018470 ps
T535 /workspace/coverage/default/17.edn_alert.35664450616874875453502777097675706863899678951202582324144207296147224443629 Oct 18 01:29:44 PM PDT 23 Oct 18 01:29:45 PM PDT 23 32330757 ps
T536 /workspace/coverage/default/47.edn_genbits.60117104949808998934849132680933868022030365909794770391619216044224908563473 Oct 18 01:31:10 PM PDT 23 Oct 18 01:31:12 PM PDT 23 22643412 ps
T537 /workspace/coverage/default/39.edn_genbits.96343351274312325035880201658834280259689668488313016540420472399594912577719 Oct 18 01:30:30 PM PDT 23 Oct 18 01:30:31 PM PDT 23 22643412 ps
T538 /workspace/coverage/default/39.edn_disable_auto_req_mode.109153044230527856638435522963416415120080114430332965503836453667391217269023 Oct 18 01:30:26 PM PDT 23 Oct 18 01:30:27 PM PDT 23 30622451 ps
T539 /workspace/coverage/default/48.edn_err.63612676702934331859711403115954112156864891173720608585218783875470586333809 Oct 18 01:31:06 PM PDT 23 Oct 18 01:31:07 PM PDT 23 29871889 ps
T540 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.57081745407151647315049753582751243993157218466163676942882447641213763886891 Oct 18 01:31:26 PM PDT 23 Oct 18 01:49:52 PM PDT 23 86880545330 ps
T541 /workspace/coverage/default/48.edn_genbits.76007117344687293405261513812968157661627194688696157375994804879844639892910 Oct 18 01:31:24 PM PDT 23 Oct 18 01:31:26 PM PDT 23 22643412 ps
T542 /workspace/coverage/default/35.edn_alert.18052583602371475735766470614625621621932831727032073618977841344058703529894 Oct 18 01:30:42 PM PDT 23 Oct 18 01:30:43 PM PDT 23 32330757 ps
T543 /workspace/coverage/default/19.edn_stress_all.54205494106377361564500110862769870556620382755718331457614252168526566069076 Oct 18 01:30:20 PM PDT 23 Oct 18 01:30:24 PM PDT 23 299451483 ps
T544 /workspace/coverage/default/44.edn_smoke.87902861683800555353659158615932874310289726043062702743601984490390986595510 Oct 18 01:30:56 PM PDT 23 Oct 18 01:30:58 PM PDT 23 21768426 ps
T545 /workspace/coverage/default/11.edn_disable_auto_req_mode.52123901475882547076850802447656923882500836197890032075610738266450909805888 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:22 PM PDT 23 30622451 ps
T546 /workspace/coverage/default/47.edn_alert_test.94461496283445827248315730315891136694922907792917796376439511470431722759968 Oct 18 01:31:18 PM PDT 23 Oct 18 01:31:20 PM PDT 23 16111390 ps
T547 /workspace/coverage/default/32.edn_disable.47085333526124260867448712294380476935243898136853922194005271876177535638588 Oct 18 01:30:22 PM PDT 23 Oct 18 01:30:24 PM PDT 23 19976788 ps
T548 /workspace/coverage/default/31.edn_smoke.84312028556855788684908756435673274346585341675619834462263870234659117031922 Oct 18 01:30:34 PM PDT 23 Oct 18 01:30:35 PM PDT 23 21768426 ps
T549 /workspace/coverage/default/24.edn_err.97387049787935296712715026033863877161802454010863527175559205523562209120441 Oct 18 01:30:16 PM PDT 23 Oct 18 01:30:17 PM PDT 23 29871889 ps
T550 /workspace/coverage/default/4.edn_smoke.50638125566328909137141859910755674384656779058715537097129206034194387333728 Oct 18 01:29:36 PM PDT 23 Oct 18 01:29:37 PM PDT 23 21768426 ps
T551 /workspace/coverage/default/13.edn_genbits.94355565124930146556513052364937394090695256842301871111573109732085522108634 Oct 18 01:30:46 PM PDT 23 Oct 18 01:30:48 PM PDT 23 22643412 ps
T552 /workspace/coverage/default/28.edn_disable_auto_req_mode.65813703451519581888897809687315852233818155895353857771785714212129962792786 Oct 18 01:30:26 PM PDT 23 Oct 18 01:30:28 PM PDT 23 30622451 ps
T553 /workspace/coverage/default/24.edn_genbits.34561389009011727043330064272483762610919704839045729620769656076489676582927 Oct 18 01:30:30 PM PDT 23 Oct 18 01:30:32 PM PDT 23 22643412 ps
T554 /workspace/coverage/default/24.edn_smoke.8274364340085986923993102974460920233601598202925132450423632601450938983971 Oct 18 01:30:47 PM PDT 23 Oct 18 01:30:48 PM PDT 23 21768426 ps
T555 /workspace/coverage/default/6.edn_err.15392215342784887084717911803563795949204606161207662454598602837462094714380 Oct 18 01:31:01 PM PDT 23 Oct 18 01:31:02 PM PDT 23 29871889 ps
T556 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.56842653316537170966709243198952397643003944126423818539229462526469549813024 Oct 18 01:29:43 PM PDT 23 Oct 18 01:48:24 PM PDT 23 86880545330 ps
T26 /workspace/coverage/default/3.edn_sec_cm.40682291132528626417784567404862527794144239797438503236834703997401468705793 Oct 18 01:29:53 PM PDT 23 Oct 18 01:29:59 PM PDT 23 359808016 ps
T557 /workspace/coverage/default/3.edn_err.68006219398038130993014288817631861578389130692024143685733239285437283961728 Oct 18 01:29:38 PM PDT 23 Oct 18 01:29:39 PM PDT 23 29871889 ps
T558 /workspace/coverage/default/43.edn_stress_all.98277270377169499346232752814485494149736570924602647322015627722701850272265 Oct 18 01:31:07 PM PDT 23 Oct 18 01:31:11 PM PDT 23 299451483 ps
T559 /workspace/coverage/default/7.edn_err.34505352891491836395454074074221579826645452689342289783514276451269268141944 Oct 18 01:30:46 PM PDT 23 Oct 18 01:30:48 PM PDT 23 29871889 ps
T560 /workspace/coverage/default/87.edn_err.99491774554775524326686059529935393607103707783663047991511627750586010225107 Oct 18 01:31:22 PM PDT 23 Oct 18 01:31:23 PM PDT 23 29871889 ps
T561 /workspace/coverage/default/28.edn_intr.82362671449206968806565663638694386102388495243507355755822702919881168287691 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:21 PM PDT 23 22372583 ps
T562 /workspace/coverage/default/48.edn_intr.38916246090507914598468168687137583082957908965022818955389050239623636916337 Oct 18 01:31:16 PM PDT 23 Oct 18 01:31:17 PM PDT 23 22372583 ps
T563 /workspace/coverage/default/25.edn_disable_auto_req_mode.28649229564460265786306207790042207506769671418465667870971922620709861025897 Oct 18 01:30:34 PM PDT 23 Oct 18 01:30:35 PM PDT 23 30622451 ps
T564 /workspace/coverage/default/26.edn_stress_all.26740420873048648501891060575709118016333716608427706734583100872773763925041 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:23 PM PDT 23 299451483 ps
T565 /workspace/coverage/default/19.edn_alert.80313539429168842145080965969752697276911683163790457359527117383153951648409 Oct 18 01:30:36 PM PDT 23 Oct 18 01:30:37 PM PDT 23 32330757 ps
T566 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.100835363399444136902157868489770810352771559017457724150424499315817727712141 Oct 18 01:30:49 PM PDT 23 Oct 18 01:49:29 PM PDT 23 86880545330 ps
T567 /workspace/coverage/default/33.edn_stress_all.22028457175212342192021023153391929460926837036937137355395594126678108239706 Oct 18 01:30:50 PM PDT 23 Oct 18 01:30:54 PM PDT 23 299451483 ps
T568 /workspace/coverage/default/7.edn_smoke.35125606947901715765233920372918485943553724691578236878180467533049997517785 Oct 18 01:30:46 PM PDT 23 Oct 18 01:30:52 PM PDT 23 21768426 ps
T569 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.99055289291020346901882021772192691780219449879658476926662539640374986550741 Oct 18 01:30:12 PM PDT 23 Oct 18 01:48:59 PM PDT 23 86880545330 ps
T570 /workspace/coverage/default/5.edn_alert_test.5548639831427795704198417618533445324332888171188740007608710461716498043454 Oct 18 01:30:32 PM PDT 23 Oct 18 01:30:34 PM PDT 23 16111390 ps
T571 /workspace/coverage/default/76.edn_err.100092150206172578870980021310835106664051991111774175870026713431787801262210 Oct 18 01:31:09 PM PDT 23 Oct 18 01:31:10 PM PDT 23 29871889 ps
T572 /workspace/coverage/default/4.edn_disable_auto_req_mode.22368589477902122344748293825921097115668379632144683115204111971018102138252 Oct 18 01:29:44 PM PDT 23 Oct 18 01:29:51 PM PDT 23 30622451 ps
T573 /workspace/coverage/default/22.edn_alert.61122259431305754335181504748588054836167307009605862827363538157491069625722 Oct 18 01:30:10 PM PDT 23 Oct 18 01:30:11 PM PDT 23 32330757 ps
T574 /workspace/coverage/default/9.edn_regwen.85200546932303094816056204224650350036433769445457492373515550116086848210224 Oct 18 01:29:37 PM PDT 23 Oct 18 01:29:38 PM PDT 23 19018470 ps
T575 /workspace/coverage/default/31.edn_alert.84470868608568111686696738292875899665761585296338015246975887668483821978472 Oct 18 01:30:23 PM PDT 23 Oct 18 01:30:24 PM PDT 23 32330757 ps
T576 /workspace/coverage/default/2.edn_alert_test.47028991802046689279795095045541375030610214597194086250009559281097626833707 Oct 18 01:30:45 PM PDT 23 Oct 18 01:30:46 PM PDT 23 16111390 ps
T577 /workspace/coverage/default/30.edn_smoke.55184863918108393196709954609156583082266007770374327913003284561942177732876 Oct 18 01:30:13 PM PDT 23 Oct 18 01:30:14 PM PDT 23 21768426 ps
T578 /workspace/coverage/default/42.edn_alert.52960600795108685655481669196232922418783027835297860670638233256862754381930 Oct 18 01:31:19 PM PDT 23 Oct 18 01:31:20 PM PDT 23 32330757 ps
T579 /workspace/coverage/default/34.edn_intr.12289785729850847854476505088837106362319288711686162458199366553915125506423 Oct 18 01:30:23 PM PDT 23 Oct 18 01:30:24 PM PDT 23 22372583 ps
T580 /workspace/coverage/default/0.edn_intr.39084453305677977085991033800908215066024734082696801154280660338420552416693 Oct 18 01:30:10 PM PDT 23 Oct 18 01:30:12 PM PDT 23 22372583 ps
T581 /workspace/coverage/default/24.edn_stress_all.107252783220208721410213590458650740710003871514659551168816389395579866893094 Oct 18 01:30:27 PM PDT 23 Oct 18 01:30:31 PM PDT 23 299451483 ps
T582 /workspace/coverage/default/2.edn_disable_auto_req_mode.63797563277220497843380919695195536144682636314821190871522792552829190471230 Oct 18 01:30:22 PM PDT 23 Oct 18 01:30:23 PM PDT 23 30622451 ps
T583 /workspace/coverage/default/38.edn_genbits.115614702003574279853686944128893173158438577174801415359813138611869918747946 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:23 PM PDT 23 22643412 ps
T584 /workspace/coverage/default/45.edn_disable_auto_req_mode.94375062729952244493156976471256531566264223998029316851184379235586002965833 Oct 18 01:31:15 PM PDT 23 Oct 18 01:31:16 PM PDT 23 30622451 ps
T585 /workspace/coverage/default/18.edn_alert.30689345726783389431770551922260099640187508146023058853471190789936858263802 Oct 18 01:30:10 PM PDT 23 Oct 18 01:30:11 PM PDT 23 32330757 ps
T586 /workspace/coverage/default/22.edn_stress_all.47613365458402173339892418755941215395565673704698632528107540305939516507101 Oct 18 01:31:00 PM PDT 23 Oct 18 01:31:04 PM PDT 23 299451483 ps
T587 /workspace/coverage/default/40.edn_genbits.14316500202199142808553979325288834264928547692400908886285293116188466394151 Oct 18 01:30:36 PM PDT 23 Oct 18 01:30:38 PM PDT 23 22643412 ps
T588 /workspace/coverage/default/16.edn_disable_auto_req_mode.22943098325027695076132196713103241748622087877043764397494464257388625467575 Oct 18 01:29:46 PM PDT 23 Oct 18 01:29:47 PM PDT 23 30622451 ps
T589 /workspace/coverage/default/10.edn_smoke.47262576737268140952412264507067282088990345789920858446517857946021233022739 Oct 18 01:30:42 PM PDT 23 Oct 18 01:30:44 PM PDT 23 21768426 ps
T590 /workspace/coverage/default/5.edn_alert.48433301542940655437399471656669301158560633397051848220843883043196191020899 Oct 18 01:30:28 PM PDT 23 Oct 18 01:30:30 PM PDT 23 32330757 ps
T27 /workspace/coverage/default/0.edn_sec_cm.97420998124253391460603776595753062083933603613516245992010608658805679840309 Oct 18 01:30:10 PM PDT 23 Oct 18 01:30:17 PM PDT 23 359808016 ps
T591 /workspace/coverage/default/17.edn_disable.21378589033263136537051473303517448539499629020470987408571283400200179955374 Oct 18 01:30:18 PM PDT 23 Oct 18 01:30:24 PM PDT 23 19976788 ps
T592 /workspace/coverage/default/49.edn_smoke.42179116550928892735395843026253245080140191913056101021349032006841623752432 Oct 18 01:31:01 PM PDT 23 Oct 18 01:31:02 PM PDT 23 21768426 ps
T593 /workspace/coverage/default/46.edn_smoke.3023483887901484597824479991746934216701709630677273190457011967510050653709 Oct 18 01:31:19 PM PDT 23 Oct 18 01:31:20 PM PDT 23 21768426 ps
T594 /workspace/coverage/default/81.edn_err.102995166562285471523937241516267135303047907936768360286297215770158196018544 Oct 18 01:31:12 PM PDT 23 Oct 18 01:31:13 PM PDT 23 29871889 ps
T595 /workspace/coverage/default/11.edn_disable.84197333136811302615904945714271493524640033332287911755002857884690673749294 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:23 PM PDT 23 19976788 ps
T596 /workspace/coverage/default/44.edn_disable.115370052589446143037350439552683330684281351921585169662133020404863025548367 Oct 18 01:31:03 PM PDT 23 Oct 18 01:31:04 PM PDT 23 19976788 ps
T597 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.16184026114571091279168427621617546396202658225088605356162550504210438861150 Oct 18 01:31:03 PM PDT 23 Oct 18 01:49:31 PM PDT 23 86880545330 ps
T598 /workspace/coverage/default/21.edn_alert_test.74014399141885351301844040367246770014501149573933638964407771549629448124704 Oct 18 01:31:32 PM PDT 23 Oct 18 01:31:33 PM PDT 23 16111390 ps
T599 /workspace/coverage/default/37.edn_disable.71273362716387355477353656519601250967080756664698261922098746326939340839880 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:23 PM PDT 23 19976788 ps
T600 /workspace/coverage/default/8.edn_genbits.73078365834791792296963814736021817012374996704061560771942276824561811908368 Oct 18 01:30:45 PM PDT 23 Oct 18 01:30:48 PM PDT 23 22643412 ps
T601 /workspace/coverage/default/12.edn_smoke.44949636713560377759022295132278370974212994611900564344328657933696803022539 Oct 18 01:30:20 PM PDT 23 Oct 18 01:30:22 PM PDT 23 21768426 ps
T602 /workspace/coverage/default/9.edn_disable_auto_req_mode.79603339189508583074372752887072278158469651159203359784020169064374153966226 Oct 18 01:30:14 PM PDT 23 Oct 18 01:30:15 PM PDT 23 30622451 ps
T603 /workspace/coverage/default/58.edn_err.37264537868043142356508497069934355363231108468364641895127141221800608411626 Oct 18 01:31:30 PM PDT 23 Oct 18 01:31:31 PM PDT 23 29871889 ps
T604 /workspace/coverage/default/45.edn_stress_all.107519096977261891355562789401469258155003875257679600936909415504015458812794 Oct 18 01:31:06 PM PDT 23 Oct 18 01:31:11 PM PDT 23 299451483 ps
T605 /workspace/coverage/default/11.edn_intr.111939398085965476067726892426539638313540763056219096705068052083976778745439 Oct 18 01:30:37 PM PDT 23 Oct 18 01:30:39 PM PDT 23 22372583 ps
T606 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.70675861140472779308563806381804789451012588760426043532148404124013435905845 Oct 18 01:30:24 PM PDT 23 Oct 18 01:48:37 PM PDT 23 86880545330 ps
T607 /workspace/coverage/default/24.edn_intr.67590674604530973407023046735973067854568509353144310568778906281389802185152 Oct 18 01:30:20 PM PDT 23 Oct 18 01:30:21 PM PDT 23 22372583 ps
T608 /workspace/coverage/default/1.edn_alert.85711107023189080975414021892226730006289896435925161454681174579532483237642 Oct 18 01:30:42 PM PDT 23 Oct 18 01:30:43 PM PDT 23 32330757 ps
T609 /workspace/coverage/default/28.edn_smoke.15096507489133902023545744954593287239602831680943171630445096698046954189273 Oct 18 01:31:09 PM PDT 23 Oct 18 01:31:11 PM PDT 23 21768426 ps
T610 /workspace/coverage/default/31.edn_stress_all.36680657686647584243220078581801392060067874495975448803067267471326965296385 Oct 18 01:30:33 PM PDT 23 Oct 18 01:30:37 PM PDT 23 299451483 ps
T611 /workspace/coverage/default/27.edn_alert.73850042991430665422102098557592371384318739159104191825162718027507974309602 Oct 18 01:30:34 PM PDT 23 Oct 18 01:30:35 PM PDT 23 32330757 ps
T612 /workspace/coverage/default/1.edn_disable.5986131540610670548929935114317924522895717698588248016269794321297819769324 Oct 18 01:30:27 PM PDT 23 Oct 18 01:30:29 PM PDT 23 19976788 ps
T37 /workspace/coverage/default/1.edn_sec_cm.35496648772939562191059904748993874802850728340427773385711871649901729495753 Oct 18 01:30:09 PM PDT 23 Oct 18 01:30:15 PM PDT 23 359808016 ps
T613 /workspace/coverage/default/15.edn_intr.91631391411847092231430791271514501276693272143127761366163378215751645638016 Oct 18 01:29:45 PM PDT 23 Oct 18 01:29:46 PM PDT 23 22372583 ps
T614 /workspace/coverage/default/28.edn_err.52396871672157013620321831121888948320686679476669668472713474937662957934563 Oct 18 01:30:36 PM PDT 23 Oct 18 01:30:38 PM PDT 23 29871889 ps
T615 /workspace/coverage/default/48.edn_stress_all_with_rand_reset.26738610943647652633235783589353674083651573102891268469660099740903729198802 Oct 18 01:31:02 PM PDT 23 Oct 18 01:49:19 PM PDT 23 86880545330 ps
T616 /workspace/coverage/default/18.edn_disable_auto_req_mode.87500127203682938245252952656290375252194772880413178076943914894261968325287 Oct 18 01:30:16 PM PDT 23 Oct 18 01:30:17 PM PDT 23 30622451 ps
T617 /workspace/coverage/default/24.edn_disable_auto_req_mode.11292039768452269561457828868295283063852401574313574226465130228866059572001 Oct 18 01:30:38 PM PDT 23 Oct 18 01:30:39 PM PDT 23 30622451 ps
T618 /workspace/coverage/default/12.edn_stress_all.109006555057008897361371217103766166504616710069464538338140222291105495508648 Oct 18 01:30:55 PM PDT 23 Oct 18 01:30:59 PM PDT 23 299451483 ps
T619 /workspace/coverage/default/7.edn_disable_auto_req_mode.16714138887044478097907887127426193906655231585810541908209840551589697138455 Oct 18 01:31:00 PM PDT 23 Oct 18 01:31:13 PM PDT 23 30622451 ps
T620 /workspace/coverage/default/18.edn_smoke.98933376618044020620308720125683948562616594814246190527833739555521288663269 Oct 18 01:30:07 PM PDT 23 Oct 18 01:30:08 PM PDT 23 21768426 ps
T621 /workspace/coverage/default/24.edn_alert.71343255442618592061339435556526826411290625647306860136103697596495386806586 Oct 18 01:30:36 PM PDT 23 Oct 18 01:30:38 PM PDT 23 32330757 ps
T622 /workspace/coverage/default/49.edn_intr.91121610951274936516731585659498653246701997612089249625236375830390949906308 Oct 18 01:31:16 PM PDT 23 Oct 18 01:31:17 PM PDT 23 22372583 ps
T623 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.44105448185604566741011409457151905695956896766785673944568199395832446626902 Oct 18 01:30:30 PM PDT 23 Oct 18 01:49:09 PM PDT 23 86880545330 ps
T624 /workspace/coverage/default/45.edn_intr.8710079759191495951512458135615331289635436273525281092031903492956009096293 Oct 18 01:31:16 PM PDT 23 Oct 18 01:31:18 PM PDT 23 22372583 ps
T625 /workspace/coverage/default/42.edn_err.95740198700213363527103418582218693323501024038137224604550378512228160468355 Oct 18 01:31:14 PM PDT 23 Oct 18 01:31:15 PM PDT 23 29871889 ps
T626 /workspace/coverage/default/33.edn_intr.31173044294207966005405549032873410048744934003813764584847261080353282902725 Oct 18 01:30:16 PM PDT 23 Oct 18 01:30:17 PM PDT 23 22372583 ps
T627 /workspace/coverage/default/44.edn_stress_all.95759133453048143963092830025681944903111603829949302253110706159515521203636 Oct 18 01:31:11 PM PDT 23 Oct 18 01:31:16 PM PDT 23 299451483 ps
T628 /workspace/coverage/default/70.edn_err.9098736686452399901050413116030131515397358557457416586688246532610766927982 Oct 18 01:31:14 PM PDT 23 Oct 18 01:31:15 PM PDT 23 29871889 ps
T629 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.60070036396575299590932380080672460832630586123307238708545960673611928660835 Oct 18 01:31:16 PM PDT 23 Oct 18 01:49:55 PM PDT 23 86880545330 ps
T630 /workspace/coverage/default/32.edn_intr.63250090641687531931174035791560928262455392243252897692955186531859041276934 Oct 18 01:30:50 PM PDT 23 Oct 18 01:30:51 PM PDT 23 22372583 ps
T631 /workspace/coverage/default/6.edn_intr.47673344237387573975154511267186621584355989570975734946824117810683698697101 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:21 PM PDT 23 22372583 ps
T632 /workspace/coverage/default/30.edn_stress_all.87394271031627702413315205678306441663877208976789912102214448196876904790590 Oct 18 01:30:29 PM PDT 23 Oct 18 01:30:34 PM PDT 23 299451483 ps
T633 /workspace/coverage/default/20.edn_smoke.76476949389749143510681698686695530680630500141112762533541757539109335563081 Oct 18 01:30:29 PM PDT 23 Oct 18 01:30:31 PM PDT 23 21768426 ps
T634 /workspace/coverage/default/9.edn_alert.17358978666512258462761212023322501252114780358692104069813611596726815494078 Oct 18 01:29:45 PM PDT 23 Oct 18 01:29:47 PM PDT 23 32330757 ps
T635 /workspace/coverage/default/46.edn_stress_all.45853056490586254985513524509731140423847898758068078883371453114679358737846 Oct 18 01:31:07 PM PDT 23 Oct 18 01:31:11 PM PDT 23 299451483 ps
T636 /workspace/coverage/default/84.edn_err.52603349804186981035705551554575997523125158638316259488823034134504547026101 Oct 18 01:31:29 PM PDT 23 Oct 18 01:31:30 PM PDT 23 29871889 ps
T637 /workspace/coverage/default/43.edn_smoke.49121418993083394103454658182514803867212311816649358412306335518310740855764 Oct 18 01:31:08 PM PDT 23 Oct 18 01:31:09 PM PDT 23 21768426 ps
T638 /workspace/coverage/default/33.edn_disable_auto_req_mode.26712623965118141768043675167042643097028107134649873966349466779819529651415 Oct 18 01:30:46 PM PDT 23 Oct 18 01:30:48 PM PDT 23 30622451 ps
T639 /workspace/coverage/default/20.edn_disable.15634897630261895660217163477309727662415077236838893101671095235490809370238 Oct 18 01:30:20 PM PDT 23 Oct 18 01:30:21 PM PDT 23 19976788 ps
T640 /workspace/coverage/default/43.edn_genbits.32585081563730040621347838719648861552695158423942003307559569524478674185684 Oct 18 01:31:07 PM PDT 23 Oct 18 01:31:08 PM PDT 23 22643412 ps
T641 /workspace/coverage/default/0.edn_err.81502778410033174602191303188604833743480001554408092686678957509364625835933 Oct 18 01:29:51 PM PDT 23 Oct 18 01:29:53 PM PDT 23 29871889 ps
T642 /workspace/coverage/default/38.edn_alert_test.94341922966113349347041491602272542292250628314610354996030267792444322807325 Oct 18 01:31:00 PM PDT 23 Oct 18 01:31:02 PM PDT 23 16111390 ps
T643 /workspace/coverage/default/30.edn_disable_auto_req_mode.58576723730560285927741452757917449749864010402514812851616104370149219899873 Oct 18 01:30:17 PM PDT 23 Oct 18 01:30:20 PM PDT 23 30622451 ps
T644 /workspace/coverage/default/6.edn_stress_all.113967174319500427361866540025232928229801382230078743619397020319894913270947 Oct 18 01:30:40 PM PDT 23 Oct 18 01:30:45 PM PDT 23 299451483 ps
T645 /workspace/coverage/default/33.edn_alert_test.22913173699854122948505903335049965810557139232692383010821088580794136379949 Oct 18 01:30:48 PM PDT 23 Oct 18 01:30:50 PM PDT 23 16111390 ps
T646 /workspace/coverage/default/40.edn_alert.42142380945177247498095838778327918445441853832169016141071732140071905353644 Oct 18 01:31:04 PM PDT 23 Oct 18 01:31:06 PM PDT 23 32330757 ps
T647 /workspace/coverage/default/7.edn_alert_test.108812400982300421761748919284189121778513774806175433115269950790198256205719 Oct 18 01:31:20 PM PDT 23 Oct 18 01:31:27 PM PDT 23 16111390 ps
T648 /workspace/coverage/default/4.edn_genbits.95410652365375214590347270493539449806156619838450906577827855820066524400079 Oct 18 01:29:34 PM PDT 23 Oct 18 01:29:41 PM PDT 23 22643412 ps
T649 /workspace/coverage/default/17.edn_smoke.18339446060480022090628223460952959942932842377233381864076073235980125453712 Oct 18 01:30:08 PM PDT 23 Oct 18 01:30:09 PM PDT 23 21768426 ps
T650 /workspace/coverage/default/44.edn_alert.61559170116674344910206473099744327374792648935486805054416262058131999948726 Oct 18 01:31:07 PM PDT 23 Oct 18 01:31:09 PM PDT 23 32330757 ps
T651 /workspace/coverage/default/11.edn_alert_test.71300086361308019516252141461102451849456279023032362932748064360155180535140 Oct 18 01:30:51 PM PDT 23 Oct 18 01:30:52 PM PDT 23 16111390 ps
T652 /workspace/coverage/default/12.edn_alert.70278095064512810607122683181020030805107600797887770990841759196272734650921 Oct 18 01:31:01 PM PDT 23 Oct 18 01:31:02 PM PDT 23 32330757 ps
T653 /workspace/coverage/default/29.edn_alert.72932446032529081623451464835809509949228613309747944579332673500981385155921 Oct 18 01:30:14 PM PDT 23 Oct 18 01:30:15 PM PDT 23 32330757 ps
T654 /workspace/coverage/default/37.edn_stress_all.112368891633495442022363664027191723332281589655016169911252736924610748950792 Oct 18 01:31:31 PM PDT 23 Oct 18 01:31:35 PM PDT 23 299451483 ps
T655 /workspace/coverage/default/28.edn_alert_test.27167371246183033865086897992577711464713290766269657613408749896127506104153 Oct 18 01:30:26 PM PDT 23 Oct 18 01:30:28 PM PDT 23 16111390 ps
T656 /workspace/coverage/default/91.edn_err.2134213602198588350247842674290646811339409009910685506101378846222936930701 Oct 18 01:31:27 PM PDT 23 Oct 18 01:31:29 PM PDT 23 29871889 ps
T657 /workspace/coverage/default/45.edn_err.108873375932824629509585530409891677417609121926991359482372931491672773194458 Oct 18 01:31:16 PM PDT 23 Oct 18 01:31:18 PM PDT 23 29871889 ps
T658 /workspace/coverage/default/50.edn_err.20800757149582584812412206460299474425297584440725858908793186866412278048219 Oct 18 01:31:11 PM PDT 23 Oct 18 01:31:13 PM PDT 23 29871889 ps
T659 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.46041761652733828179743214319476805614038751800344608476953032228532975191084 Oct 18 01:29:44 PM PDT 23 Oct 18 01:48:09 PM PDT 23 86880545330 ps
T660 /workspace/coverage/default/6.edn_alert_test.32013626352126830805549970333837912678966819605416622444787899643161268669598 Oct 18 01:30:13 PM PDT 23 Oct 18 01:30:14 PM PDT 23 16111390 ps
T661 /workspace/coverage/default/20.edn_disable_auto_req_mode.114306962172859603889141567474947745134187181636817168459188652630178351586458 Oct 18 01:30:23 PM PDT 23 Oct 18 01:30:24 PM PDT 23 30622451 ps
T662 /workspace/coverage/default/20.edn_stress_all.108683056676404750289469255942890237515075013006747545310459704139403571355910 Oct 18 01:30:37 PM PDT 23 Oct 18 01:30:41 PM PDT 23 299451483 ps
T663 /workspace/coverage/default/36.edn_alert_test.51844893688810009973164250554535471888559943841395466134821324238186345867265 Oct 18 01:31:06 PM PDT 23 Oct 18 01:31:08 PM PDT 23 16111390 ps
T664 /workspace/coverage/default/13.edn_stress_all.43283362565685182557434545214594213519051741115597536466305696180484956533080 Oct 18 01:29:37 PM PDT 23 Oct 18 01:29:40 PM PDT 23 299451483 ps
T665 /workspace/coverage/default/39.edn_disable.109470347396332260719350337405921594188859920741775766941651428731939607763458 Oct 18 01:30:58 PM PDT 23 Oct 18 01:31:00 PM PDT 23 19976788 ps
T666 /workspace/coverage/default/3.edn_alert_test.96242532585969411508865831991548357464465971278270616352953804179960461744615 Oct 18 01:29:42 PM PDT 23 Oct 18 01:29:43 PM PDT 23 16111390 ps
T667 /workspace/coverage/default/0.edn_disable_auto_req_mode.16504798353631498904995080378851426043566982869032583289807604799303327665311 Oct 18 01:29:49 PM PDT 23 Oct 18 01:29:50 PM PDT 23 30622451 ps
T668 /workspace/coverage/default/97.edn_err.78738348705107974556649940807022524136152356489923663928370070455754670030160 Oct 18 01:31:27 PM PDT 23 Oct 18 01:31:28 PM PDT 23 29871889 ps
T669 /workspace/coverage/default/27.edn_err.88806516479333147707608520506164130750185612900007578950478736828045178508179 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:20 PM PDT 23 29871889 ps
T670 /workspace/coverage/default/41.edn_alert.93152229623635567245264743706727127154585159059025954499421649307286037852786 Oct 18 01:31:10 PM PDT 23 Oct 18 01:31:13 PM PDT 23 32330757 ps
T671 /workspace/coverage/default/30.edn_alert_test.78815533925363793880480720428547942110402098543530977427268073357217819412674 Oct 18 01:30:37 PM PDT 23 Oct 18 01:30:39 PM PDT 23 16111390 ps
T672 /workspace/coverage/default/10.edn_err.92916240257540444364433432638110848280638149695768633584269352548010171975638 Oct 18 01:30:30 PM PDT 23 Oct 18 01:30:31 PM PDT 23 29871889 ps
T673 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.107454616575651262669195510984555505618771567162851737491643847713403895629049 Oct 18 01:30:30 PM PDT 23 Oct 18 01:49:01 PM PDT 23 86880545330 ps
T674 /workspace/coverage/default/14.edn_intr.34112151447765387422821928305789569766809149346073186295440548977987266213323 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:22 PM PDT 23 22372583 ps
T675 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.108809869487094428139600898708053051145676419999630931151548743861451492067575 Oct 18 01:31:15 PM PDT 23 Oct 18 01:49:46 PM PDT 23 86880545330 ps
T676 /workspace/coverage/default/13.edn_err.111231668151436213351307326812862169988660678283197465923335671048129724607570 Oct 18 01:29:51 PM PDT 23 Oct 18 01:29:53 PM PDT 23 29871889 ps
T677 /workspace/coverage/default/46.edn_intr.47306677314474260328755431514409654452352761322041936625324772567879392943036 Oct 18 01:31:17 PM PDT 23 Oct 18 01:31:18 PM PDT 23 22372583 ps
T678 /workspace/coverage/default/7.edn_genbits.35010028341882837811175322628211838619179239425791077847118974963922852399737 Oct 18 01:29:32 PM PDT 23 Oct 18 01:29:33 PM PDT 23 22643412 ps
T679 /workspace/coverage/default/41.edn_disable_auto_req_mode.65962823528896093080910549291133332260155549895351479740250988565782945325182 Oct 18 01:31:39 PM PDT 23 Oct 18 01:31:41 PM PDT 23 30622451 ps
T680 /workspace/coverage/default/39.edn_smoke.16397778525279388417186570389229788923561509871176888812053563770237134558679 Oct 18 01:30:37 PM PDT 23 Oct 18 01:30:38 PM PDT 23 21768426 ps
T681 /workspace/coverage/default/5.edn_disable.72370743363778358030293122669310248920052020509628666649631264908090357868804 Oct 18 01:30:34 PM PDT 23 Oct 18 01:30:35 PM PDT 23 19976788 ps
T682 /workspace/coverage/default/23.edn_stress_all.41595402109999199495504828264906009529262077908540979259052726399483901696882 Oct 18 01:30:07 PM PDT 23 Oct 18 01:30:11 PM PDT 23 299451483 ps
T683 /workspace/coverage/default/72.edn_err.29041209639409638794038380921683423239612566509524607830769018916191433794354 Oct 18 01:31:06 PM PDT 23 Oct 18 01:31:07 PM PDT 23 29871889 ps
T684 /workspace/coverage/default/79.edn_err.32230247234938166811902476918033484588088082709829695891825714407554160809869 Oct 18 01:31:10 PM PDT 23 Oct 18 01:31:12 PM PDT 23 29871889 ps
T685 /workspace/coverage/default/1.edn_stress_all.9855064426107022882643590178990749961579795747003727085035550211134294477218 Oct 18 01:29:38 PM PDT 23 Oct 18 01:29:43 PM PDT 23 299451483 ps
T686 /workspace/coverage/default/12.edn_err.44882724844924060193406059154621009800708752006049302362745375120926690762202 Oct 18 01:29:39 PM PDT 23 Oct 18 01:29:40 PM PDT 23 29871889 ps
T687 /workspace/coverage/default/22.edn_err.8691761376520813985364019505981821731176460044325009447187728180531620410271 Oct 18 01:30:16 PM PDT 23 Oct 18 01:30:17 PM PDT 23 29871889 ps
T688 /workspace/coverage/default/19.edn_err.32559231610909933494270766495497806250029021986092606623175111415318345715916 Oct 18 01:30:42 PM PDT 23 Oct 18 01:30:45 PM PDT 23 29871889 ps
T38 /workspace/coverage/default/4.edn_sec_cm.78703351626391858916925442505818593283024643026843491116652828086077084413890 Oct 18 01:30:29 PM PDT 23 Oct 18 01:30:35 PM PDT 23 359808016 ps
T689 /workspace/coverage/default/4.edn_regwen.76713470340704302608987533548307785541888293015097016496820622640447889057066 Oct 18 01:29:42 PM PDT 23 Oct 18 01:29:44 PM PDT 23 19018470 ps
T690 /workspace/coverage/default/12.edn_disable_auto_req_mode.60536669427533809939792166082433207589609245415079651210439977979366735349882 Oct 18 01:30:34 PM PDT 23 Oct 18 01:30:35 PM PDT 23 30622451 ps
T691 /workspace/coverage/default/6.edn_disable.47230327874398597784150791091549891958352872728832724403980257871736528653666 Oct 18 01:30:24 PM PDT 23 Oct 18 01:30:26 PM PDT 23 19976788 ps
T692 /workspace/coverage/default/29.edn_intr.95916937749530198616203809549923571478644984589376889380594234648784555659198 Oct 18 01:30:26 PM PDT 23 Oct 18 01:30:28 PM PDT 23 22372583 ps
T693 /workspace/coverage/default/48.edn_smoke.35580141167714166019011674761738488614458743061725209001373988178701840442257 Oct 18 01:31:22 PM PDT 23 Oct 18 01:31:23 PM PDT 23 21768426 ps
T694 /workspace/coverage/default/29.edn_genbits.63058040353290230795690904633309978031435372443786736985241502202426568978770 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:23 PM PDT 23 22643412 ps
T695 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.50946765571331788197680424275116843170484571388420455982332992194864955638939 Oct 18 01:30:21 PM PDT 23 Oct 18 01:48:47 PM PDT 23 86880545330 ps
T696 /workspace/coverage/default/96.edn_err.5067520036578616176712495478567301301835676323834105234308612119939590878053 Oct 18 01:31:34 PM PDT 23 Oct 18 01:31:40 PM PDT 23 29871889 ps
T697 /workspace/coverage/default/36.edn_disable_auto_req_mode.80181097221287295300898489110621568173131789996764446748094387147273554608724 Oct 18 01:31:11 PM PDT 23 Oct 18 01:31:13 PM PDT 23 30622451 ps
T698 /workspace/coverage/default/27.edn_disable.75475136893223759156631651083694040950544833303033479511823101437795337959761 Oct 18 01:30:21 PM PDT 23 Oct 18 01:30:27 PM PDT 23 19976788 ps
T699 /workspace/coverage/default/0.edn_stress_all.94716001511499936064067723385582684838846634121046787854942563075493536202239 Oct 18 01:29:32 PM PDT 23 Oct 18 01:29:36 PM PDT 23 299451483 ps
T700 /workspace/coverage/default/38.edn_stress_all.98338641485078222342709415802462339212459394049348726756467967986749879866774 Oct 18 01:30:25 PM PDT 23 Oct 18 01:30:29 PM PDT 23 299451483 ps
T701 /workspace/coverage/default/29.edn_err.81029559401067583479341777590355705895877625496161508583080744689010941692165 Oct 18 01:30:33 PM PDT 23 Oct 18 01:30:35 PM PDT 23 29871889 ps
T702 /workspace/coverage/default/30.edn_alert.102770154425414862573842575370126563233315354611792472434181987214164169040311 Oct 18 01:30:16 PM PDT 23 Oct 18 01:30:17 PM PDT 23 32330757 ps
T703 /workspace/coverage/default/22.edn_disable.64215523706055398101703417026353668465811462251497591312396581853879450470263 Oct 18 01:30:17 PM PDT 23 Oct 18 01:30:18 PM PDT 23 19976788 ps
T704 /workspace/coverage/default/13.edn_alert_test.107967196850391191106054406821969356623771544542090844228107241435913031964720 Oct 18 01:29:57 PM PDT 23 Oct 18 01:29:58 PM PDT 23 16111390 ps
T705 /workspace/coverage/default/16.edn_genbits.75688490950116036330004499434009759549078888406980513388415053462753186594591 Oct 18 01:30:12 PM PDT 23 Oct 18 01:30:13 PM PDT 23 22643412 ps
T706 /workspace/coverage/default/6.edn_alert.45653686024265393042294429307805789484466801097353388744347975083204363954642 Oct 18 01:30:28 PM PDT 23 Oct 18 01:30:29 PM PDT 23 32330757 ps
T707 /workspace/coverage/default/25.edn_alert.84302986494457489647030055293282913033760265747457617862452557185135210772096 Oct 18 01:30:22 PM PDT 23 Oct 18 01:30:23 PM PDT 23 32330757 ps
T708 /workspace/coverage/default/37.edn_disable_auto_req_mode.107685832655549172007367495187106941847660403454609663616691513118315210197767 Oct 18 01:30:26 PM PDT 23 Oct 18 01:30:27 PM PDT 23 30622451 ps
T709 /workspace/coverage/default/14.edn_smoke.28599710551683038996356578423072405402972181360384932528234825249616174361154 Oct 18 01:30:16 PM PDT 23 Oct 18 01:30:17 PM PDT 23 21768426 ps
T710 /workspace/coverage/default/3.edn_alert.16796344641812047928297481178385576420159436785480619622723474292674015571914 Oct 18 01:30:58 PM PDT 23 Oct 18 01:30:59 PM PDT 23 32330757 ps
T711 /workspace/coverage/default/5.edn_stress_all.104928015748889824561053363407240839715815633590152910968857397642853505342285 Oct 18 01:30:30 PM PDT 23 Oct 18 01:30:34 PM PDT 23 299451483 ps
T712 /workspace/coverage/default/27.edn_alert_test.112473080159941336321096423209762523901121555173948838425808808981322305555347 Oct 18 01:30:35 PM PDT 23 Oct 18 01:30:36 PM PDT 23 16111390 ps
T713 /workspace/coverage/default/34.edn_smoke.61538882006756597395998391000652439211088820080056275558849714770429695074529 Oct 18 01:30:53 PM PDT 23 Oct 18 01:30:54 PM PDT 23 21768426 ps
T714 /workspace/coverage/default/37.edn_intr.64995013391421583789727267723564369283383275372051223100433156209683392191530 Oct 18 01:31:04 PM PDT 23 Oct 18 01:31:06 PM PDT 23 22372583 ps
T715 /workspace/coverage/default/95.edn_err.77253873084927295188142281861858626361348047114036823687554274163765074687997 Oct 18 01:31:19 PM PDT 23 Oct 18 01:31:21 PM PDT 23 29871889 ps
T716 /workspace/coverage/default/85.edn_err.31551000533323294454898072209748566113632450678904833379674653573003192334876 Oct 18 01:31:34 PM PDT 23 Oct 18 01:31:35 PM PDT 23 29871889 ps
T717 /workspace/coverage/default/41.edn_err.106585814766001767403657109792191245737852770864149833599563552072998451010697 Oct 18 01:31:17 PM PDT 23 Oct 18 01:31:19 PM PDT 23 29871889 ps
T718 /workspace/coverage/default/33.edn_alert.99830218344263729296147108980961735803747357507301927161727183435515068348296 Oct 18 01:30:11 PM PDT 23 Oct 18 01:30:12 PM PDT 23 32330757 ps
T719 /workspace/coverage/default/5.edn_smoke.101612211356986909561174278371319864431983195410654695052228566741411380490882 Oct 18 01:30:28 PM PDT 23 Oct 18 01:30:29 PM PDT 23 21768426 ps
T720 /workspace/coverage/default/21.edn_disable_auto_req_mode.21772058720270611265355721370584384450058770430888443411271268535252987406384 Oct 18 01:30:35 PM PDT 23 Oct 18 01:30:37 PM PDT 23 30622451 ps
T721 /workspace/coverage/default/2.edn_intr.14775721372700256890599981031477382530232935698151616878845235082027043209996 Oct 18 01:30:45 PM PDT 23 Oct 18 01:30:46 PM PDT 23 22372583 ps
T722 /workspace/coverage/default/34.edn_disable_auto_req_mode.14160086069838037071342208882126462755825439248713266480759478644475267017716 Oct 18 01:30:31 PM PDT 23 Oct 18 01:30:33 PM PDT 23 30622451 ps
T723 /workspace/coverage/default/17.edn_err.97382120367000372033953500286930358250522257100907962079393918263381672550404 Oct 18 01:30:19 PM PDT 23 Oct 18 01:30:20 PM PDT 23 29871889 ps
T724 /workspace/coverage/default/14.edn_alert.70625393283880396645216032378479035908341811963053758744258767925696042701614 Oct 18 01:31:12 PM PDT 23 Oct 18 01:31:14 PM PDT 23 32330757 ps
T725 /workspace/coverage/default/31.edn_alert_test.34676963789065939088522694688946718469425220152072800079979641184158131409612 Oct 18 01:30:20 PM PDT 23 Oct 18 01:30:21 PM PDT 23 16111390 ps
T726 /workspace/coverage/default/25.edn_alert_test.8561583774477684679513779486210289244810382837568304013009603866531841553768 Oct 18 01:30:35 PM PDT 23 Oct 18 01:30:36 PM PDT 23 16111390 ps
T727 /workspace/coverage/default/49.edn_stress_all.72507811434364417908860195343740700169044783898798045228333198726291897940633 Oct 18 01:31:14 PM PDT 23 Oct 18 01:31:18 PM PDT 23 299451483 ps
T728 /workspace/coverage/default/39.edn_alert_test.31131637971016000865025270136813573800605646781388703196802649948240300564932 Oct 18 01:30:41 PM PDT 23 Oct 18 01:30:42 PM PDT 23 16111390 ps
T729 /workspace/coverage/default/74.edn_err.114173177813786490442228126570273920011580945270239393574657554342895070049173 Oct 18 01:31:15 PM PDT 23 Oct 18 01:31:16 PM PDT 23 29871889 ps

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.69501696425425842206941821395587360221283494345700369381652858741240826194415
Short name T1
Test name
Test status
Simulation time 86880545330 ps
CPU time 1108.67 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:48:55 PM PDT 23
Peak memory 218648 kb
Host smart-19532edd-b396-4daa-95f4-87a2636d6b3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695016964254258422069418213
95587360221283494345700369381652858741240826194415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.69501696425
425842206941821395587360221283494345700369381652858741240826194415
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_err.9044039849704628575622996454156058841248627860160240460259418376113098352320
Short name T14
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:49 PM PDT 23
Peak memory 215280 kb
Host smart-1918133d-78c2-46a6-9d75-c13d5b4acf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9044039849704628575622996454156058841248627860160240460259418376113098352320 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
edn_err.9044039849704628575622996454156058841248627860160240460259418376113098352320
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.7672039641544654440583113158173879912395851732062992099388029433092130997807
Short name T25
Test name
Test status
Simulation time 359808016 ps
CPU time 5.81 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:41 PM PDT 23
Peak memory 235476 kb
Host smart-0233f29d-308a-4cbb-af9b-400879d43318
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7672039641544654440583113158173879912395851732062992099388029433092130997807 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_sec_cm.7672039641544654440583113158173879912395851732062992099388029433092130997807
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.104569809093584503629775765072028777842628513077182934899323873645938795811788
Short name T29
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:32 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 215280 kb
Host smart-374496fd-6e48-4fcf-a1af-0027b9993e18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104569809093584503629775765072028777842628513077182934899323873645938795811788 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.104569809093584503629775765072028777842628513077182934899
323873645938795811788
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_disable.86723671100132634197937690090155685572109353439381440809959986309464087122462
Short name T65
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:29:45 PM PDT 23
Finished Oct 18 01:29:46 PM PDT 23
Peak memory 215052 kb
Host smart-c8cea330-6108-45b7-a603-afe824bd1b49
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86723671100132634197937690090155685572109353439381440809959986309464087122462 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_disable.86723671100132634197937690090155685572109353439381440809959986309464087122462
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert.2938957120536457392257308241449087653488009415265967973938508666014693800897
Short name T23
Test name
Test status
Simulation time 32330757 ps
CPU time 1 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 205984 kb
Host smart-c0aea1f0-084b-4c09-9b23-e06c5bd34560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938957120536457392257308241449087653488009415265967973938508666014693800897 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.edn_alert.2938957120536457392257308241449087653488009415265967973938508666014693800897
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/6.edn_regwen.5938559569748225952230469841845284191129241565590970144201854023385092619351
Short name T46
Test name
Test status
Simulation time 19018470 ps
CPU time 0.84 seconds
Started Oct 18 01:30:51 PM PDT 23
Finished Oct 18 01:30:52 PM PDT 23
Peak memory 205636 kb
Host smart-54dfa425-30e2-4457-9e38-6eff870a5f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5938559569748225952230469841845284191129241565590970144201854023385092619351 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_regwen.5938559569748225952230469841845284191129241565590970144201854023385092619351
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.54227957425293161188748996073693199978424120371552690165733404656833232837947
Short name T112
Test name
Test status
Simulation time 87151723 ps
CPU time 2.54 seconds
Started Oct 18 12:22:09 PM PDT 23
Finished Oct 18 12:22:12 PM PDT 23
Peak memory 206752 kb
Host smart-6e6ebea8-08ba-4d15-abef-aca4b0e978c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54227957425293161188748996073693199978424120371552690165733404656833232837947 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.54227957425293161188748996073693199978424120371552690165733404656833232837947
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.50010256005500778139580694969545805900497723726560013429247108175218325920370
Short name T88
Test name
Test status
Simulation time 31808344 ps
CPU time 1.36 seconds
Started Oct 18 12:26:02 PM PDT 23
Finished Oct 18 12:26:03 PM PDT 23
Peak memory 206208 kb
Host smart-7d443403-da1d-4fcc-afb4-ad5738b6ca82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50010256005500778139580694969545805900497723726560013429247108175218325920370 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.50010256005500778139580694969545805900497723726560013429247108175218325920370
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/10.edn_intr.23777638569894307048640504830025104905485178338111662919450702781479463082652
Short name T15
Test name
Test status
Simulation time 22372583 ps
CPU time 1.04 seconds
Started Oct 18 01:30:32 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 222752 kb
Host smart-29f364ed-b508-415b-87b4-4957daefbac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23777638569894307048640504830025104905485178338111662919450702781479463082652 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.edn_intr.23777638569894307048640504830025104905485178338111662919450702781479463082652
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/11.edn_genbits.18697887679728965255975164298565889344927206115430525482378199530131716973162
Short name T51
Test name
Test status
Simulation time 22643412 ps
CPU time 0.91 seconds
Started Oct 18 01:30:08 PM PDT 23
Finished Oct 18 01:30:10 PM PDT 23
Peak memory 205768 kb
Host smart-f15df8fc-95d7-4967-ad6e-dc65a0973aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18697887679728965255975164298565889344927206115430525482378199530131716973162 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.edn_genbits.18697887679728965255975164298565889344927206115430525482378199530131716973162
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.26826600689479511526042825929541938735215820859044052325966564690579514862720
Short name T43
Test name
Test status
Simulation time 16111390 ps
CPU time 0.88 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 206004 kb
Host smart-d5a02b44-185f-433c-9a39-59fced7e9264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826600689479511526042825929541938735215820859044052325966564690579514862720 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_alert_test.26826600689479511526042825929541938735215820859044052325966564690579514862720
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.56092250877361331978910634401969420209948219239124605139721720129326941574543
Short name T98
Test name
Test status
Simulation time 32384101 ps
CPU time 1.24 seconds
Started Oct 18 12:25:54 PM PDT 23
Finished Oct 18 12:25:55 PM PDT 23
Peak memory 206224 kb
Host smart-38a686c9-d22a-45b6-a9eb-887adc3c3cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56092250877361331978910634401969420209948219239124605139721720129326941574543
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.56092250877361331978910634401969420209948219239124605139721720129326941574543
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.edn_smoke.4045486794431952222613618938945116729931536568296855798737698302485487952643
Short name T75
Test name
Test status
Simulation time 21768426 ps
CPU time 0.88 seconds
Started Oct 18 01:29:40 PM PDT 23
Finished Oct 18 01:29:42 PM PDT 23
Peak memory 205640 kb
Host smart-8616f4ce-4371-450b-bdc0-b1baa0c783f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045486794431952222613618938945116729931536568296855798737698302485487952643 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.edn_smoke.4045486794431952222613618938945116729931536568296855798737698302485487952643
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.12752246286038612784839962408701840413512603719389276013565109380199358647558
Short name T327
Test name
Test status
Simulation time 175969816 ps
CPU time 4.92 seconds
Started Oct 18 12:26:02 PM PDT 23
Finished Oct 18 12:26:08 PM PDT 23
Peak memory 206316 kb
Host smart-6f05f2a7-9baa-4191-98e3-4b64914db206
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12752246286038612784839962408701840413512603719389276013565109380199358647558 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.12752246286038612784839962408701840413512603719389276013565109380199358647558
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.53995338926303344794014443333239036370286592784552199498274734150432892773030
Short name T291
Test name
Test status
Simulation time 15899269 ps
CPU time 0.85 seconds
Started Oct 18 12:27:31 PM PDT 23
Finished Oct 18 12:27:32 PM PDT 23
Peak memory 206420 kb
Host smart-f5cc2012-31d0-465a-9d20-3d9245d24e34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53995338926303344794014443333239036370286592784552199498274734150432892773030 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.53995338926303344794014443333239036370286592784552199498274734150432892773030
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.93910765553489055886442168970552805195185127190641464681344718995099174684986
Short name T299
Test name
Test status
Simulation time 27767944 ps
CPU time 1.33 seconds
Started Oct 18 12:25:54 PM PDT 23
Finished Oct 18 12:25:57 PM PDT 23
Peak memory 213936 kb
Host smart-52c630d2-77da-4b9e-ada3-be4543b3976e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9391076555348905588644216897055280519518512
7190641464681344718995099174684986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.9391076555348905588644216897
0552805195185127190641464681344718995099174684986
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.44809578070102175781907113841995593406703543395573355788858553260200026286456
Short name T288
Test name
Test status
Simulation time 14091190 ps
CPU time 0.89 seconds
Started Oct 18 12:23:51 PM PDT 23
Finished Oct 18 12:23:53 PM PDT 23
Peak memory 206436 kb
Host smart-af5762eb-d1c0-4950-9e05-9319692445fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44809578070102175781907113841995593406703543395573355788858553260200026286456 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.44809578070102175781907113841995593406703543395573355788858553260200026286456
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.43197683561726817765136890375230003307092997600572347136918672853488963544726
Short name T247
Test name
Test status
Simulation time 15333613 ps
CPU time 0.9 seconds
Started Oct 18 12:26:02 PM PDT 23
Finished Oct 18 12:26:03 PM PDT 23
Peak memory 205996 kb
Host smart-caf641af-e969-4d93-b676-ff9b17eea2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43197683561726817765136890375230003307092997600572347136918672853488963544726 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.edn_intr_test.43197683561726817765136890375230003307092997600572347136918672853488963544726
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.73825538838493657868271485616033970450288107134207020089371424314656253300027
Short name T219
Test name
Test status
Simulation time 100515346 ps
CPU time 3.63 seconds
Started Oct 18 12:26:01 PM PDT 23
Finished Oct 18 12:26:05 PM PDT 23
Peak memory 214340 kb
Host smart-e4d43f95-630c-4f27-a287-ebd890018847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73825538838493657868271485616033970450288107134207020089371424314656253300027 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.edn_tl_errors.73825538838493657868271485616033970450288107134207020089371424314656253300027
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.72810137957493123754002305356994382135781397679865161762946392153725467782979
Short name T81
Test name
Test status
Simulation time 87151723 ps
CPU time 2.51 seconds
Started Oct 18 12:20:46 PM PDT 23
Finished Oct 18 12:20:49 PM PDT 23
Peak memory 204752 kb
Host smart-3bd78560-7be9-44b6-ad92-1a695ac07061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72810137957493123754002305356994382135781397679865161762946392153725467782979 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.72810137957493123754002305356994382135781397679865161762946392153725467782979
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.58402881836250534719193569757981221946671960664088874086999778561316219306598
Short name T80
Test name
Test status
Simulation time 31808344 ps
CPU time 1.42 seconds
Started Oct 18 12:22:15 PM PDT 23
Finished Oct 18 12:22:16 PM PDT 23
Peak memory 206432 kb
Host smart-15576dcc-5eed-42a5-9fde-73e4a0232a71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58402881836250534719193569757981221946671960664088874086999778561316219306598 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.58402881836250534719193569757981221946671960664088874086999778561316219306598
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.101110530868277483059063772129419228471603888142007217143197739012287726174167
Short name T96
Test name
Test status
Simulation time 175969816 ps
CPU time 5.07 seconds
Started Oct 18 12:25:53 PM PDT 23
Finished Oct 18 12:25:58 PM PDT 23
Peak memory 206564 kb
Host smart-9951585d-bd65-42c0-88fb-72f9f067cd04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101110530868277483059063772129419228471603888142007217143197739012287726174167 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.101110530868277483059063772129419228471603888142007217143197739012287726174167
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.42979932876226680975669461853376419709634090879576617950523795014815266483625
Short name T283
Test name
Test status
Simulation time 15899269 ps
CPU time 0.87 seconds
Started Oct 18 12:28:24 PM PDT 23
Finished Oct 18 12:28:25 PM PDT 23
Peak memory 206428 kb
Host smart-d7e45bf7-dee9-40cc-ba1b-84e64f020941
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42979932876226680975669461853376419709634090879576617950523795014815266483625 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.42979932876226680975669461853376419709634090879576617950523795014815266483625
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.30772910839268161472772875372126322919420506455920463166414378015846585963936
Short name T256
Test name
Test status
Simulation time 27767944 ps
CPU time 1.26 seconds
Started Oct 18 12:28:24 PM PDT 23
Finished Oct 18 12:28:25 PM PDT 23
Peak memory 214692 kb
Host smart-b65f871f-3197-4166-ac38-5b615bc684dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077291083926816147277287537212632291942050
6455920463166414378015846585963936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3077291083926816147277287537
2126322919420506455920463166414378015846585963936
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.60972621432174887424409114674900690688022795900780394801791398590840755462681
Short name T223
Test name
Test status
Simulation time 14091190 ps
CPU time 0.88 seconds
Started Oct 18 12:25:05 PM PDT 23
Finished Oct 18 12:25:07 PM PDT 23
Peak memory 206396 kb
Host smart-0f96ac40-f0cd-4bb2-b565-6a95f2900bf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60972621432174887424409114674900690688022795900780394801791398590840755462681 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.60972621432174887424409114674900690688022795900780394801791398590840755462681
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.106342698637338960689357443575652238857264352487123068484133672067636122447615
Short name T298
Test name
Test status
Simulation time 15333613 ps
CPU time 0.91 seconds
Started Oct 18 12:22:45 PM PDT 23
Finished Oct 18 12:22:46 PM PDT 23
Peak memory 206256 kb
Host smart-83479d6f-a045-45d2-b711-529fde410418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106342698637338960689357443575652238857264352487123068484133672067636122447615 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.edn_intr_test.106342698637338960689357443575652238857264352487123068484133672067636122447615
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.80897376169466889298005151821194999458426320343068020602062912868740202623574
Short name T260
Test name
Test status
Simulation time 32384101 ps
CPU time 1.4 seconds
Started Oct 18 12:28:10 PM PDT 23
Finished Oct 18 12:28:12 PM PDT 23
Peak memory 205048 kb
Host smart-95daae41-a3e0-4e45-b8d4-a17fe90fb351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80897376169466889298005151821194999458426320343068020602062912868740202623574
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.80897376169466889298005151821194999458426320343068020602062912868740202623574
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.115711645484075281594031550769549798646080939635306700680787739951581015038393
Short name T276
Test name
Test status
Simulation time 100515346 ps
CPU time 3.56 seconds
Started Oct 18 12:26:05 PM PDT 23
Finished Oct 18 12:26:10 PM PDT 23
Peak memory 214648 kb
Host smart-d2ca5a31-bf21-4330-85a0-36433e2103db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115711645484075281594031550769549798646080939635306700680787739951581015038393 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.edn_tl_errors.115711645484075281594031550769549798646080939635306700680787739951581015038393
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.30342339075533208046077813308378717884748336849963150564935926021360234818504
Short name T285
Test name
Test status
Simulation time 27767944 ps
CPU time 1.3 seconds
Started Oct 18 12:25:33 PM PDT 23
Finished Oct 18 12:25:34 PM PDT 23
Peak memory 214732 kb
Host smart-2ea48a8c-7493-488b-9b89-a6b90aa772de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034233907553320804607781330837871788474833
6849963150564935926021360234818504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.303423390755332080460778133
08378717884748336849963150564935926021360234818504
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.90858865869647541908013397683575137207536893637619353385821042766578524910464
Short name T271
Test name
Test status
Simulation time 14091190 ps
CPU time 0.87 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:07 PM PDT 23
Peak memory 206280 kb
Host smart-666ccb69-7d4d-4523-a9d7-2084deb505d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90858865869647541908013397683575137207536893637619353385821042766578524910464 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.90858865869647541908013397683575137207536893637619353385821042766578524910464
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.10520828833024106841141753753372507509138563518621178623162546944956783515046
Short name T201
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:27:58 PM PDT 23
Finished Oct 18 12:28:00 PM PDT 23
Peak memory 205928 kb
Host smart-5dfd2b4b-d741-453e-b33f-5c0bc79944eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520828833024106841141753753372507509138563518621178623162546944956783515046 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_intr_test.10520828833024106841141753753372507509138563518621178623162546944956783515046
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.8962579400445987909491414716252697521021704392602219128489214389197591739718
Short name T100
Test name
Test status
Simulation time 32384101 ps
CPU time 1.24 seconds
Started Oct 18 12:26:05 PM PDT 23
Finished Oct 18 12:26:06 PM PDT 23
Peak memory 206216 kb
Host smart-0fb4d3d2-13ac-41c3-a9f1-c9f686af7e81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8962579400445987909491414716252697521021704392602219128489214389197591739718 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.8962579400445987909491414716252697521021704392602219128489214389197591739718
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.81959696378869802400457864133573245677266420175709940275515998339254751063443
Short name T249
Test name
Test status
Simulation time 100515346 ps
CPU time 3.68 seconds
Started Oct 18 12:25:44 PM PDT 23
Finished Oct 18 12:25:49 PM PDT 23
Peak memory 214660 kb
Host smart-fb14f64a-ce79-4f2c-83e7-d9277e66d4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81959696378869802400457864133573245677266420175709940275515998339254751063443 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_tl_errors.81959696378869802400457864133573245677266420175709940275515998339254751063443
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2372137623371802427675764886419454154210693590125853745667555654479538470515
Short name T284
Test name
Test status
Simulation time 87151723 ps
CPU time 2.29 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:32 PM PDT 23
Peak memory 206408 kb
Host smart-877c9e08-6f0b-43e3-8d0b-848b9500d854
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372137623371802427675764886419454154210693590125853745667555654479538470515 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2372137623371802427675764886419454154210693590125853745667555654479538470515
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.10265565340266669829776834422562014671329664846300134272006127544596768881291
Short name T289
Test name
Test status
Simulation time 27767944 ps
CPU time 1.34 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:14 PM PDT 23
Peak memory 213896 kb
Host smart-698dfd0b-be5d-464b-b24b-2ac40d9814bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026556534026666982977683442256201467132966
4846300134272006127544596768881291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.102655653402666698297768344
22562014671329664846300134272006127544596768881291
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.44511196799940989948086246410023533437506716041227567148216792383278402219988
Short name T324
Test name
Test status
Simulation time 14091190 ps
CPU time 0.87 seconds
Started Oct 18 12:26:26 PM PDT 23
Finished Oct 18 12:26:27 PM PDT 23
Peak memory 206400 kb
Host smart-ddda938c-db06-4cd6-bc09-1550702080c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44511196799940989948086246410023533437506716041227567148216792383278402219988 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.44511196799940989948086246410023533437506716041227567148216792383278402219988
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.74951628677032524941957652520231391410007908881780365372150833270975583073140
Short name T231
Test name
Test status
Simulation time 15333613 ps
CPU time 1.05 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:14 PM PDT 23
Peak memory 204800 kb
Host smart-8717d2eb-c30f-49a7-a246-70981c449624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74951628677032524941957652520231391410007908881780365372150833270975583073140 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_intr_test.74951628677032524941957652520231391410007908881780365372150833270975583073140
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.38515993991730388112613638007099996655582802299983292300549261849548488150073
Short name T273
Test name
Test status
Simulation time 32384101 ps
CPU time 1.32 seconds
Started Oct 18 12:22:33 PM PDT 23
Finished Oct 18 12:22:36 PM PDT 23
Peak memory 206380 kb
Host smart-c333d15c-a911-477b-acb9-68a32732e340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515993991730388112613638007099996655582802299983292300549261849548488150073
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.38515993991730388112613638007099996655582802299983292300549261849548488150073
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.42746712945693549768219860814816783782567657370562374906181494544900925271248
Short name T323
Test name
Test status
Simulation time 100515346 ps
CPU time 3.54 seconds
Started Oct 18 12:28:34 PM PDT 23
Finished Oct 18 12:28:38 PM PDT 23
Peak memory 214428 kb
Host smart-5df90321-4525-43a4-af8a-e7d64a0ff1da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746712945693549768219860814816783782567657370562374906181494544900925271248 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_tl_errors.42746712945693549768219860814816783782567657370562374906181494544900925271248
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.85317694628325725728325482563946999322928155912425393338426983554367954439367
Short name T93
Test name
Test status
Simulation time 87151723 ps
CPU time 2.32 seconds
Started Oct 18 12:27:19 PM PDT 23
Finished Oct 18 12:27:22 PM PDT 23
Peak memory 206428 kb
Host smart-195c11b4-2a00-43c7-9539-90da38337e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85317694628325725728325482563946999322928155912425393338426983554367954439367 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.85317694628325725728325482563946999322928155912425393338426983554367954439367
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.41184271851225640276995741056664579383036162496841827725379648442654779758263
Short name T281
Test name
Test status
Simulation time 27767944 ps
CPU time 1.3 seconds
Started Oct 18 12:27:55 PM PDT 23
Finished Oct 18 12:27:57 PM PDT 23
Peak memory 214732 kb
Host smart-90ce015d-4830-4cb3-8fc7-653977a193d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118427185122564027699574105666457938303616
2496841827725379648442654779758263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.411842718512256402769957410
56664579383036162496841827725379648442654779758263
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.98699709686356081615066837592109121498329374184825872603074598054592762587640
Short name T222
Test name
Test status
Simulation time 14091190 ps
CPU time 0.93 seconds
Started Oct 18 12:28:15 PM PDT 23
Finished Oct 18 12:28:17 PM PDT 23
Peak memory 205228 kb
Host smart-8e37526e-1bc9-4022-ba05-ca2db83b4033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98699709686356081615066837592109121498329374184825872603074598054592762587640 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.98699709686356081615066837592109121498329374184825872603074598054592762587640
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.40734142930642101777869083083925002216687204458711124310366384636689508299020
Short name T334
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:25:44 PM PDT 23
Finished Oct 18 12:25:46 PM PDT 23
Peak memory 206272 kb
Host smart-e7df84cb-eab8-4727-890b-8588a46cfa58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734142930642101777869083083925002216687204458711124310366384636689508299020 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_intr_test.40734142930642101777869083083925002216687204458711124310366384636689508299020
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.97904867000853399830860100821876121585082393914417800403360874564641806127640
Short name T282
Test name
Test status
Simulation time 32384101 ps
CPU time 1.3 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:23 PM PDT 23
Peak memory 205716 kb
Host smart-c8283eef-c3d3-4178-a630-f24d840c28b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97904867000853399830860100821876121585082393914417800403360874564641806127640
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.97904867000853399830860100821876121585082393914417800403360874564641806127640
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.62617602695905659761677302261773296214966639674576067296042981898022797486914
Short name T217
Test name
Test status
Simulation time 100515346 ps
CPU time 3.75 seconds
Started Oct 18 12:21:11 PM PDT 23
Finished Oct 18 12:21:15 PM PDT 23
Peak memory 214728 kb
Host smart-577a3dc3-5eee-4c78-80e7-f066fcc5a81c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62617602695905659761677302261773296214966639674576067296042981898022797486914 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_tl_errors.62617602695905659761677302261773296214966639674576067296042981898022797486914
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.112837821482681708937150424151244710219702431202467090099906310112367063432926
Short name T113
Test name
Test status
Simulation time 87151723 ps
CPU time 2.26 seconds
Started Oct 18 12:28:29 PM PDT 23
Finished Oct 18 12:28:32 PM PDT 23
Peak memory 206392 kb
Host smart-e31c0724-d3e4-4e81-bfd8-eda948a3d93b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112837821482681708937150424151244710219702431202467090099906310112367063432926 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.112837821482681708937150424151244710219702431202467090099906310112367063432926
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.10470929672476579252434009698299944974925356276280056445572168367791738705862
Short name T259
Test name
Test status
Simulation time 27767944 ps
CPU time 1.32 seconds
Started Oct 18 12:27:58 PM PDT 23
Finished Oct 18 12:28:00 PM PDT 23
Peak memory 214752 kb
Host smart-49b0a521-7fea-46cc-b47a-1e76c53d2399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047092967247657925243400969829994497492535
6276280056445572168367791738705862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.104709296724765792524340096
98299944974925356276280056445572168367791738705862
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.11064000259186640923819713182947627210041186232645225362152498728758240786283
Short name T317
Test name
Test status
Simulation time 14091190 ps
CPU time 0.85 seconds
Started Oct 18 12:25:31 PM PDT 23
Finished Oct 18 12:25:33 PM PDT 23
Peak memory 206068 kb
Host smart-a581099d-f115-4d74-b421-1fec3daf012b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064000259186640923819713182947627210041186232645225362152498728758240786283 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.11064000259186640923819713182947627210041186232645225362152498728758240786283
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.64838205609831456243811272698738742421027613831797303195630062575324532019451
Short name T92
Test name
Test status
Simulation time 15333613 ps
CPU time 0.87 seconds
Started Oct 18 12:22:33 PM PDT 23
Finished Oct 18 12:22:35 PM PDT 23
Peak memory 206244 kb
Host smart-c98dd7c7-1795-4028-bebe-f17d9511b8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64838205609831456243811272698738742421027613831797303195630062575324532019451 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.edn_intr_test.64838205609831456243811272698738742421027613831797303195630062575324532019451
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.22170025396844720660698537566698742510889766081764681553409138371790143508534
Short name T90
Test name
Test status
Simulation time 32384101 ps
CPU time 1.27 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 206076 kb
Host smart-d4bea4ee-c28a-4ddd-8a87-38488f53df18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22170025396844720660698537566698742510889766081764681553409138371790143508534
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.22170025396844720660698537566698742510889766081764681553409138371790143508534
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.63964369424811817373423930143655492710567102241572962836989248747024026442240
Short name T241
Test name
Test status
Simulation time 100515346 ps
CPU time 3.69 seconds
Started Oct 18 12:25:28 PM PDT 23
Finished Oct 18 12:25:32 PM PDT 23
Peak memory 213748 kb
Host smart-9f1b1d9b-6174-45ea-b2b8-bfbc1025aef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63964369424811817373423930143655492710567102241572962836989248747024026442240 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.edn_tl_errors.63964369424811817373423930143655492710567102241572962836989248747024026442240
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.55594063787776785650514674344374957804145582231007205585701273929503246041084
Short name T272
Test name
Test status
Simulation time 87151723 ps
CPU time 2.47 seconds
Started Oct 18 12:21:19 PM PDT 23
Finished Oct 18 12:21:22 PM PDT 23
Peak memory 206636 kb
Host smart-7fc6a383-9116-489c-8bd9-f5ea1c03bf42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55594063787776785650514674344374957804145582231007205585701273929503246041084 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.55594063787776785650514674344374957804145582231007205585701273929503246041084
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.35636101356892760698746592663871285390540901663827305587129365248661749323193
Short name T253
Test name
Test status
Simulation time 27767944 ps
CPU time 1.31 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:14 PM PDT 23
Peak memory 214676 kb
Host smart-cfa055c4-d544-487f-b646-175587399a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563610135689276069874659266387128539054090
1663827305587129365248661749323193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.356361013568927606987465926
63871285390540901663827305587129365248661749323193
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.67652693295885541363375567232996071446976710057409038169950744855444498747014
Short name T319
Test name
Test status
Simulation time 14091190 ps
CPU time 0.88 seconds
Started Oct 18 12:23:21 PM PDT 23
Finished Oct 18 12:23:22 PM PDT 23
Peak memory 206500 kb
Host smart-35d9f85f-96bb-4a5c-bfe4-25a831eeb2ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67652693295885541363375567232996071446976710057409038169950744855444498747014 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.67652693295885541363375567232996071446976710057409038169950744855444498747014
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.70920693383452116664595396664535517613336493808671808380974906871249743812489
Short name T230
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:26:46 PM PDT 23
Finished Oct 18 12:26:47 PM PDT 23
Peak memory 206232 kb
Host smart-faae217f-3fbc-4924-847c-db68cef9cd8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70920693383452116664595396664535517613336493808671808380974906871249743812489 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.edn_intr_test.70920693383452116664595396664535517613336493808671808380974906871249743812489
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.91829374741285921831429265336708855188000209959251022709741006263252515312148
Short name T95
Test name
Test status
Simulation time 32384101 ps
CPU time 1.37 seconds
Started Oct 18 12:22:20 PM PDT 23
Finished Oct 18 12:22:22 PM PDT 23
Peak memory 206476 kb
Host smart-5c07b071-7d1e-4630-9efc-ef732544dec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91829374741285921831429265336708855188000209959251022709741006263252515312148
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.91829374741285921831429265336708855188000209959251022709741006263252515312148
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.69883903212255237955042264266569711223677600369355532320583549792586849653847
Short name T233
Test name
Test status
Simulation time 100515346 ps
CPU time 3.63 seconds
Started Oct 18 12:28:12 PM PDT 23
Finished Oct 18 12:28:16 PM PDT 23
Peak memory 214636 kb
Host smart-d8c72dc0-8686-4bc0-b6f4-bdb4e180af9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69883903212255237955042264266569711223677600369355532320583549792586849653847 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.edn_tl_errors.69883903212255237955042264266569711223677600369355532320583549792586849653847
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.47032557056009375541223522846692631836305153050683551298646503156436583492798
Short name T329
Test name
Test status
Simulation time 87151723 ps
CPU time 2.35 seconds
Started Oct 18 12:26:46 PM PDT 23
Finished Oct 18 12:26:49 PM PDT 23
Peak memory 206376 kb
Host smart-fe0e3136-763f-4ba2-b93f-655cee8035cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47032557056009375541223522846692631836305153050683551298646503156436583492798 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.47032557056009375541223522846692631836305153050683551298646503156436583492798
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.84402871056634227651959639698609668697108058022157728366086507929968035985953
Short name T250
Test name
Test status
Simulation time 27767944 ps
CPU time 1.27 seconds
Started Oct 18 12:28:04 PM PDT 23
Finished Oct 18 12:28:05 PM PDT 23
Peak memory 214468 kb
Host smart-9313a8f5-95c2-4844-97e1-dcaf13b4d4eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8440287105663422765195963969860966869710805
8022157728366086507929968035985953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.844028710566342276519596396
98609668697108058022157728366086507929968035985953
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.55941795265338549301152809422139637552029563480930476866861744936410338491599
Short name T84
Test name
Test status
Simulation time 14091190 ps
CPU time 0.89 seconds
Started Oct 18 12:28:43 PM PDT 23
Finished Oct 18 12:28:44 PM PDT 23
Peak memory 206424 kb
Host smart-d70aee3a-2f1f-48fe-a8d5-b1880e640146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55941795265338549301152809422139637552029563480930476866861744936410338491599 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.55941795265338549301152809422139637552029563480930476866861744936410338491599
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.55901645390662917074591959780933682612203670632661571532429312776918164728960
Short name T266
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:28:04 PM PDT 23
Finished Oct 18 12:28:05 PM PDT 23
Peak memory 205968 kb
Host smart-34d52c1b-14d3-44ad-b0ee-c2ee48574fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55901645390662917074591959780933682612203670632661571532429312776918164728960 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.edn_intr_test.55901645390662917074591959780933682612203670632661571532429312776918164728960
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.41566052506253932073921269277604650310220938231493378695948032274785669539996
Short name T101
Test name
Test status
Simulation time 32384101 ps
CPU time 1.33 seconds
Started Oct 18 12:26:35 PM PDT 23
Finished Oct 18 12:26:36 PM PDT 23
Peak memory 206436 kb
Host smart-fc98d00f-8beb-4f07-b1c9-50d0dcb0bc0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41566052506253932073921269277604650310220938231493378695948032274785669539996
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.41566052506253932073921269277604650310220938231493378695948032274785669539996
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.111320696003303974667595908577229039655065161505418595000006375918092448796570
Short name T270
Test name
Test status
Simulation time 100515346 ps
CPU time 3.73 seconds
Started Oct 18 12:27:30 PM PDT 23
Finished Oct 18 12:27:35 PM PDT 23
Peak memory 213848 kb
Host smart-87c28c83-914e-4ae5-852d-2a4adcac2a40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111320696003303974667595908577229039655065161505418595000006375918092448796570 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.edn_tl_errors.111320696003303974667595908577229039655065161505418595000006375918092448796570
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.13023042366495886258877678613992510995735420665976202807114249766448074960026
Short name T320
Test name
Test status
Simulation time 87151723 ps
CPU time 2.46 seconds
Started Oct 18 12:21:08 PM PDT 23
Finished Oct 18 12:21:11 PM PDT 23
Peak memory 206412 kb
Host smart-d0c22a5b-d9cb-4fb0-9bcf-cf43bf3ff0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13023042366495886258877678613992510995735420665976202807114249766448074960026 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.13023042366495886258877678613992510995735420665976202807114249766448074960026
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.82647671783186472657560844403422837124030011747761338927471345254521073385383
Short name T206
Test name
Test status
Simulation time 27767944 ps
CPU time 1.34 seconds
Started Oct 18 12:30:15 PM PDT 23
Finished Oct 18 12:30:17 PM PDT 23
Peak memory 214816 kb
Host smart-943f56c6-0a18-4a7c-a919-595efe86c1ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8264767178318647265756084440342283712403001
1747761338927471345254521073385383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.826476717831864726575608444
03422837124030011747761338927471345254521073385383
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.8988677951266701917128744205921321328365382862457053745058172605159459002292
Short name T205
Test name
Test status
Simulation time 14091190 ps
CPU time 0.9 seconds
Started Oct 18 12:22:09 PM PDT 23
Finished Oct 18 12:22:11 PM PDT 23
Peak memory 206648 kb
Host smart-0c450341-0f3b-4a5d-ac3d-a3b75a854ec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8988677951266701917128744205921321328365382862457053745058172605159459002292 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.8988677951266701917128744205921321328365382862457053745058172605159459002292
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.18892455262629697145991524901360055211997876846891954405022742294294672993213
Short name T305
Test name
Test status
Simulation time 15333613 ps
CPU time 0.88 seconds
Started Oct 18 12:21:23 PM PDT 23
Finished Oct 18 12:21:25 PM PDT 23
Peak memory 206612 kb
Host smart-ac0fd517-96cb-4e55-a092-f3be23f58683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18892455262629697145991524901360055211997876846891954405022742294294672993213 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.edn_intr_test.18892455262629697145991524901360055211997876846891954405022742294294672993213
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.65067762574002210645595021245533986547643432863195621614469932726864250556373
Short name T99
Test name
Test status
Simulation time 32384101 ps
CPU time 1.32 seconds
Started Oct 18 12:28:18 PM PDT 23
Finished Oct 18 12:28:20 PM PDT 23
Peak memory 206384 kb
Host smart-f60fff15-f144-489c-8375-9aa432c1689e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65067762574002210645595021245533986547643432863195621614469932726864250556373
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.65067762574002210645595021245533986547643432863195621614469932726864250556373
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.109177346018481198757290419420072877177837966204220526373914569654031252871818
Short name T267
Test name
Test status
Simulation time 100515346 ps
CPU time 3.61 seconds
Started Oct 18 12:26:38 PM PDT 23
Finished Oct 18 12:26:42 PM PDT 23
Peak memory 214648 kb
Host smart-e9043d6c-c923-48e5-a100-d64bc772c329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109177346018481198757290419420072877177837966204220526373914569654031252871818 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.edn_tl_errors.109177346018481198757290419420072877177837966204220526373914569654031252871818
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.29507916851963008632611876044702116992668559509861753712181656196104346049429
Short name T111
Test name
Test status
Simulation time 87151723 ps
CPU time 2.2 seconds
Started Oct 18 12:28:17 PM PDT 23
Finished Oct 18 12:28:20 PM PDT 23
Peak memory 206416 kb
Host smart-6af2a6ac-fe62-4ea1-9384-7379eec89dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507916851963008632611876044702116992668559509861753712181656196104346049429 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.29507916851963008632611876044702116992668559509861753712181656196104346049429
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.66902519387057136289720587277736986884728816924543645796365545908744015068488
Short name T297
Test name
Test status
Simulation time 27767944 ps
CPU time 1.31 seconds
Started Oct 18 12:24:09 PM PDT 23
Finished Oct 18 12:24:10 PM PDT 23
Peak memory 214892 kb
Host smart-c010bbcd-30b2-445d-92c7-44f3502f2130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6690251938705713628972058727773698688472881
6924543645796365545908744015068488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.669025193870571362897205872
77736986884728816924543645796365545908744015068488
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.55753804798822463076562102041733299658561461216756700511732795055619751366814
Short name T214
Test name
Test status
Simulation time 14091190 ps
CPU time 0.85 seconds
Started Oct 18 12:27:54 PM PDT 23
Finished Oct 18 12:27:55 PM PDT 23
Peak memory 206412 kb
Host smart-5fddfed0-02c3-4ff5-af92-c1f273948a4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55753804798822463076562102041733299658561461216756700511732795055619751366814 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.55753804798822463076562102041733299658561461216756700511732795055619751366814
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.18236690709439176784036354870387435148259261144385915762575633333428800656421
Short name T292
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:28:21 PM PDT 23
Finished Oct 18 12:28:22 PM PDT 23
Peak memory 206052 kb
Host smart-908ba28a-618f-4474-9957-76ae9d3d6ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236690709439176784036354870387435148259261144385915762575633333428800656421 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_intr_test.18236690709439176784036354870387435148259261144385915762575633333428800656421
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.63874582132877172615785819268303194258589007635232733132979108438600284117499
Short name T102
Test name
Test status
Simulation time 32384101 ps
CPU time 1.31 seconds
Started Oct 18 12:27:26 PM PDT 23
Finished Oct 18 12:27:28 PM PDT 23
Peak memory 205584 kb
Host smart-a2a2e927-485b-4718-b960-bf03f21f3c07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63874582132877172615785819268303194258589007635232733132979108438600284117499
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.63874582132877172615785819268303194258589007635232733132979108438600284117499
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.95450587470731375784066111134610039412382527463853979994520161802263314767856
Short name T242
Test name
Test status
Simulation time 100515346 ps
CPU time 3.66 seconds
Started Oct 18 12:27:36 PM PDT 23
Finished Oct 18 12:27:40 PM PDT 23
Peak memory 213860 kb
Host smart-24c211db-c0b2-4c4c-aab0-b89b65c3c82a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95450587470731375784066111134610039412382527463853979994520161802263314767856 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_tl_errors.95450587470731375784066111134610039412382527463853979994520161802263314767856
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.74642625281690075481418390529714282970070248294329603843934950272455217503503
Short name T240
Test name
Test status
Simulation time 87151723 ps
CPU time 2.29 seconds
Started Oct 18 12:25:56 PM PDT 23
Finished Oct 18 12:25:59 PM PDT 23
Peak memory 205572 kb
Host smart-98dee640-94d1-4082-932f-a49a0b02a0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74642625281690075481418390529714282970070248294329603843934950272455217503503 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.74642625281690075481418390529714282970070248294329603843934950272455217503503
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.90623714998173271112571548912671286003953075796300725590765980040443357108885
Short name T318
Test name
Test status
Simulation time 27767944 ps
CPU time 1.25 seconds
Started Oct 18 12:29:49 PM PDT 23
Finished Oct 18 12:29:51 PM PDT 23
Peak memory 214536 kb
Host smart-05e43479-e98a-4a83-819e-8e8d8d61621a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9062371499817327111257154891267128600395307
5796300725590765980040443357108885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.906237149981732711125715489
12671286003953075796300725590765980040443357108885
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.13928581695700361156881446006483702801241324101775906919629662765152401763623
Short name T208
Test name
Test status
Simulation time 14091190 ps
CPU time 0.87 seconds
Started Oct 18 12:27:39 PM PDT 23
Finished Oct 18 12:27:40 PM PDT 23
Peak memory 206084 kb
Host smart-74fcee9e-3212-4bf7-a192-011e6d24c0e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13928581695700361156881446006483702801241324101775906919629662765152401763623 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.13928581695700361156881446006483702801241324101775906919629662765152401763623
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.6556129101067148310618856711839828389128525647565750827638018107785537292701
Short name T308
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:25:58 PM PDT 23
Finished Oct 18 12:25:59 PM PDT 23
Peak memory 206268 kb
Host smart-19b49aa3-4c84-46e0-bee3-f9603bd1eb93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6556129101067148310618856711839828389128525647565750827638018107785537292701 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.edn_intr_test.6556129101067148310618856711839828389128525647565750827638018107785537292701
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.12954596421998222623953505720760820821630340207427891765635138720107876698384
Short name T251
Test name
Test status
Simulation time 32384101 ps
CPU time 1.29 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:08 PM PDT 23
Peak memory 205872 kb
Host smart-a6d0b5e6-cd0e-4d43-ab0c-d4d57081f6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12954596421998222623953505720760820821630340207427891765635138720107876698384
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.12954596421998222623953505720760820821630340207427891765635138720107876698384
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.61806357935280041515011776686661750587723710497444604960139074775757949843687
Short name T202
Test name
Test status
Simulation time 100515346 ps
CPU time 3.5 seconds
Started Oct 18 12:28:11 PM PDT 23
Finished Oct 18 12:28:15 PM PDT 23
Peak memory 214672 kb
Host smart-c3f27076-89fc-41de-b652-743a723746f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61806357935280041515011776686661750587723710497444604960139074775757949843687 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.edn_tl_errors.61806357935280041515011776686661750587723710497444604960139074775757949843687
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.89870853639584455118647041076144262850500010162222731940224492353928120138051
Short name T265
Test name
Test status
Simulation time 87151723 ps
CPU time 2.25 seconds
Started Oct 18 12:28:17 PM PDT 23
Finished Oct 18 12:28:20 PM PDT 23
Peak memory 206440 kb
Host smart-f447efb6-edbb-45d0-9fe7-1ffc1d97f0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89870853639584455118647041076144262850500010162222731940224492353928120138051 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.89870853639584455118647041076144262850500010162222731940224492353928120138051
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.64700379107426586181502657761940140731058439178401782819388224060448208223686
Short name T255
Test name
Test status
Simulation time 27767944 ps
CPU time 1.33 seconds
Started Oct 18 12:21:51 PM PDT 23
Finished Oct 18 12:21:53 PM PDT 23
Peak memory 214752 kb
Host smart-bea30f5c-aff7-4d66-9a10-692c1e03458e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6470037910742658618150265776194014073105843
9178401782819388224060448208223686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.647003791074265861815026577
61940140731058439178401782819388224060448208223686
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2147860914386519731641028284480459131434759342238128367345275186347236169928
Short name T312
Test name
Test status
Simulation time 14091190 ps
CPU time 0.87 seconds
Started Oct 18 12:26:18 PM PDT 23
Finished Oct 18 12:26:20 PM PDT 23
Peak memory 206372 kb
Host smart-72c3efaa-8b70-49e5-8d11-f30a6811f617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147860914386519731641028284480459131434759342238128367345275186347236169928 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2147860914386519731641028284480459131434759342238128367345275186347236169928
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.44034656894681679241350772838306664059042158679883358473788803267808885045004
Short name T210
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:27:16 PM PDT 23
Finished Oct 18 12:27:17 PM PDT 23
Peak memory 206208 kb
Host smart-86667d1c-f185-4a2f-b466-5186d5f100a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44034656894681679241350772838306664059042158679883358473788803267808885045004 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_intr_test.44034656894681679241350772838306664059042158679883358473788803267808885045004
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.56904858071567001434761344033999757851290586682151627411743934413230711410417
Short name T304
Test name
Test status
Simulation time 32384101 ps
CPU time 1.26 seconds
Started Oct 18 12:25:16 PM PDT 23
Finished Oct 18 12:25:17 PM PDT 23
Peak memory 205948 kb
Host smart-d81057bb-5599-47cd-9ae1-69265903db15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56904858071567001434761344033999757851290586682151627411743934413230711410417
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.56904858071567001434761344033999757851290586682151627411743934413230711410417
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.78431802335471106309500992348659134420827661728392384438990468454921287946341
Short name T280
Test name
Test status
Simulation time 100515346 ps
CPU time 3.56 seconds
Started Oct 18 12:26:04 PM PDT 23
Finished Oct 18 12:26:08 PM PDT 23
Peak memory 214440 kb
Host smart-8747520a-5518-4fc7-ba90-d0465b0a717e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78431802335471106309500992348659134420827661728392384438990468454921287946341 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_tl_errors.78431802335471106309500992348659134420827661728392384438990468454921287946341
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.97202960425134977820440934412017457697166109277133614744140939915606964183695
Short name T315
Test name
Test status
Simulation time 87151723 ps
CPU time 2.47 seconds
Started Oct 18 12:24:22 PM PDT 23
Finished Oct 18 12:24:25 PM PDT 23
Peak memory 206440 kb
Host smart-1ad433d2-6418-47e7-9d2a-b4c83c9c256d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97202960425134977820440934412017457697166109277133614744140939915606964183695 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.97202960425134977820440934412017457697166109277133614744140939915606964183695
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.89470725666322843045740015709627273178106530543593361193113753058709126012623
Short name T77
Test name
Test status
Simulation time 31808344 ps
CPU time 1.42 seconds
Started Oct 18 12:25:54 PM PDT 23
Finished Oct 18 12:25:56 PM PDT 23
Peak memory 206564 kb
Host smart-32306f1b-55dd-4cb8-9a2e-57687c8e91e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89470725666322843045740015709627273178106530543593361193113753058709126012623 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.89470725666322843045740015709627273178106530543593361193113753058709126012623
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.76990044985507470691353276602062644170432419807576093930177587334777732095771
Short name T296
Test name
Test status
Simulation time 175969816 ps
CPU time 5.18 seconds
Started Oct 18 12:22:08 PM PDT 23
Finished Oct 18 12:22:14 PM PDT 23
Peak memory 206480 kb
Host smart-10e68fe3-920f-4e16-a561-8e9e025e70f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76990044985507470691353276602062644170432419807576093930177587334777732095771 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.76990044985507470691353276602062644170432419807576093930177587334777732095771
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.53298424782975395410602370358849267746315184450421142302000513146421587799657
Short name T209
Test name
Test status
Simulation time 15899269 ps
CPU time 0.91 seconds
Started Oct 18 12:23:59 PM PDT 23
Finished Oct 18 12:24:00 PM PDT 23
Peak memory 206748 kb
Host smart-f00f6ae8-af4f-4459-a797-5a13cd0663e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53298424782975395410602370358849267746315184450421142302000513146421587799657 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.53298424782975395410602370358849267746315184450421142302000513146421587799657
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.92495600069331442788153358832428055849777237458337911536291843142510967758510
Short name T269
Test name
Test status
Simulation time 27767944 ps
CPU time 1.36 seconds
Started Oct 18 12:25:20 PM PDT 23
Finished Oct 18 12:25:22 PM PDT 23
Peak memory 214792 kb
Host smart-6adbe94d-daff-401a-b722-20560207d74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9249560006933144278815335883242805584977723
7458337911536291843142510967758510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.9249560006933144278815335883
2428055849777237458337911536291843142510967758510
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.31721517170907454882407043754738129687207601958790481693120286119544752158787
Short name T257
Test name
Test status
Simulation time 14091190 ps
CPU time 0.88 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:13 PM PDT 23
Peak memory 206628 kb
Host smart-fdbed584-6b10-489c-bdce-2a87f46ea185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31721517170907454882407043754738129687207601958790481693120286119544752158787 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.31721517170907454882407043754738129687207601958790481693120286119544752158787
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.107153618325322372317438514722130031789764714374278955747292763843921214078917
Short name T328
Test name
Test status
Simulation time 15333613 ps
CPU time 0.84 seconds
Started Oct 18 12:28:31 PM PDT 23
Finished Oct 18 12:28:34 PM PDT 23
Peak memory 206228 kb
Host smart-2ca249b0-e0cc-4852-aab3-f0ecd7886fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107153618325322372317438514722130031789764714374278955747292763843921214078917 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.edn_intr_test.107153618325322372317438514722130031789764714374278955747292763843921214078917
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.58963868940616591712746632490847306706387439907600476441977934458285809403071
Short name T333
Test name
Test status
Simulation time 32384101 ps
CPU time 1.38 seconds
Started Oct 18 12:28:10 PM PDT 23
Finished Oct 18 12:28:12 PM PDT 23
Peak memory 204844 kb
Host smart-5d3e861a-4044-43a9-bd19-8a317343ec54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58963868940616591712746632490847306706387439907600476441977934458285809403071
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.58963868940616591712746632490847306706387439907600476441977934458285809403071
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.18343245865063953113217003348813015507233840817939436559084343221590588247897
Short name T83
Test name
Test status
Simulation time 100515346 ps
CPU time 3.78 seconds
Started Oct 18 12:25:53 PM PDT 23
Finished Oct 18 12:25:57 PM PDT 23
Peak memory 214744 kb
Host smart-35417cc4-f733-4982-bf8c-4fbd580319a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18343245865063953113217003348813015507233840817939436559084343221590588247897 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.edn_tl_errors.18343245865063953113217003348813015507233840817939436559084343221590588247897
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.44591464138432819923623708821181267026551404887899003735584052987446292784707
Short name T268
Test name
Test status
Simulation time 87151723 ps
CPU time 2.29 seconds
Started Oct 18 12:25:54 PM PDT 23
Finished Oct 18 12:25:56 PM PDT 23
Peak memory 206160 kb
Host smart-34923781-7244-4f19-aff8-16bd586bd6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44591464138432819923623708821181267026551404887899003735584052987446292784707 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.44591464138432819923623708821181267026551404887899003735584052987446292784707
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.59309787972669490264402989224877351523463863319336872788458178412077195481235
Short name T227
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:25:29 PM PDT 23
Finished Oct 18 12:25:30 PM PDT 23
Peak memory 205928 kb
Host smart-d51881af-64b6-49eb-8037-860d9093212f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59309787972669490264402989224877351523463863319336872788458178412077195481235 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 20.edn_intr_test.59309787972669490264402989224877351523463863319336872788458178412077195481235
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.89668801043157004364976582679053991240442983216265525374597070014891076335641
Short name T200
Test name
Test status
Simulation time 15333613 ps
CPU time 0.89 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:12 PM PDT 23
Peak memory 205152 kb
Host smart-70d3f5db-48dc-4e68-a139-aa6a1d57fd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89668801043157004364976582679053991240442983216265525374597070014891076335641 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 21.edn_intr_test.89668801043157004364976582679053991240442983216265525374597070014891076335641
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.85905273065553762858995455026051923351880464588563506548042388798399660889650
Short name T78
Test name
Test status
Simulation time 15333613 ps
CPU time 0.89 seconds
Started Oct 18 12:21:05 PM PDT 23
Finished Oct 18 12:21:06 PM PDT 23
Peak memory 206524 kb
Host smart-02d6cde3-30cc-49eb-889e-26b2ed21e449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85905273065553762858995455026051923351880464588563506548042388798399660889650 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 22.edn_intr_test.85905273065553762858995455026051923351880464588563506548042388798399660889650
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.56416978497697465774003034893371123990506608487819878188503339608813294654781
Short name T245
Test name
Test status
Simulation time 15333613 ps
CPU time 0.92 seconds
Started Oct 18 12:22:03 PM PDT 23
Finished Oct 18 12:22:05 PM PDT 23
Peak memory 206256 kb
Host smart-850f74ae-cb81-4bb7-82ad-01a688c65385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56416978497697465774003034893371123990506608487819878188503339608813294654781 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 23.edn_intr_test.56416978497697465774003034893371123990506608487819878188503339608813294654781
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.84318915416945830336177348388418961612135194970716755189639528966985975438517
Short name T212
Test name
Test status
Simulation time 15333613 ps
CPU time 0.87 seconds
Started Oct 18 12:26:07 PM PDT 23
Finished Oct 18 12:26:08 PM PDT 23
Peak memory 206000 kb
Host smart-4e17e31e-50f5-427e-b30c-09f1cb035135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84318915416945830336177348388418961612135194970716755189639528966985975438517 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 24.edn_intr_test.84318915416945830336177348388418961612135194970716755189639528966985975438517
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.95511657337042971195528795132791508003853975421872824008104423897905304669695
Short name T331
Test name
Test status
Simulation time 15333613 ps
CPU time 1.09 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:14 PM PDT 23
Peak memory 204788 kb
Host smart-f94675df-acce-42b6-8991-4507279c3b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95511657337042971195528795132791508003853975421872824008104423897905304669695 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 25.edn_intr_test.95511657337042971195528795132791508003853975421872824008104423897905304669695
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.10904053629521433716327474850891077228201418292084430698823960536163607216092
Short name T301
Test name
Test status
Simulation time 15333613 ps
CPU time 0.9 seconds
Started Oct 18 12:23:03 PM PDT 23
Finished Oct 18 12:23:04 PM PDT 23
Peak memory 206612 kb
Host smart-0b6f3fc7-c86d-4102-8404-e701c8490807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10904053629521433716327474850891077228201418292084430698823960536163607216092 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 26.edn_intr_test.10904053629521433716327474850891077228201418292084430698823960536163607216092
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.96010169112522607336104049803102924894178935391057198388544853419577715028775
Short name T85
Test name
Test status
Simulation time 15333613 ps
CPU time 0.98 seconds
Started Oct 18 12:20:31 PM PDT 23
Finished Oct 18 12:20:33 PM PDT 23
Peak memory 205872 kb
Host smart-9339b9d7-f262-4c34-b6bb-ebfd6583fd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96010169112522607336104049803102924894178935391057198388544853419577715028775 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.edn_intr_test.96010169112522607336104049803102924894178935391057198388544853419577715028775
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.92409197110826929041102270150337874271545224208049288417654312292240066185127
Short name T311
Test name
Test status
Simulation time 15333613 ps
CPU time 0.89 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:13 PM PDT 23
Peak memory 206216 kb
Host smart-08f7be5d-e62e-473c-9663-84852b43df69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92409197110826929041102270150337874271545224208049288417654312292240066185127 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 28.edn_intr_test.92409197110826929041102270150337874271545224208049288417654312292240066185127
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.5356053458009256159396902753190509743741653833901852748444850243220223418035
Short name T258
Test name
Test status
Simulation time 15333613 ps
CPU time 0.91 seconds
Started Oct 18 12:25:23 PM PDT 23
Finished Oct 18 12:25:24 PM PDT 23
Peak memory 206524 kb
Host smart-8cb3c86e-b344-4d21-8357-f90bf4bdb319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5356053458009256159396902753190509743741653833901852748444850243220223418035 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 29.edn_intr_test.5356053458009256159396902753190509743741653833901852748444850243220223418035
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.49736980393011454525164703138873422435374506009339345182526820704537299553930
Short name T86
Test name
Test status
Simulation time 31808344 ps
CPU time 1.41 seconds
Started Oct 18 12:22:05 PM PDT 23
Finished Oct 18 12:22:07 PM PDT 23
Peak memory 206720 kb
Host smart-d16fd2ed-0ace-4848-8761-834035243772
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49736980393011454525164703138873422435374506009339345182526820704537299553930 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.49736980393011454525164703138873422435374506009339345182526820704537299553930
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.14898371179875745235579647588753217665089116459968970759495860674031072312100
Short name T203
Test name
Test status
Simulation time 175969816 ps
CPU time 4.97 seconds
Started Oct 18 12:25:21 PM PDT 23
Finished Oct 18 12:25:27 PM PDT 23
Peak memory 206528 kb
Host smart-60fd1758-652a-4d1d-95f0-e9742c36aa02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14898371179875745235579647588753217665089116459968970759495860674031072312100 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.14898371179875745235579647588753217665089116459968970759495860674031072312100
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.59152623643308441059764040425330118222290046352043841714598643659173061610344
Short name T204
Test name
Test status
Simulation time 15899269 ps
CPU time 0.88 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:07 PM PDT 23
Peak memory 206440 kb
Host smart-b38966c9-e1e7-4012-8910-efc258a43963
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59152623643308441059764040425330118222290046352043841714598643659173061610344 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.59152623643308441059764040425330118222290046352043841714598643659173061610344
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.34300240356110945579740050925735635889058268431186308807533298009247999601819
Short name T237
Test name
Test status
Simulation time 27767944 ps
CPU time 1.26 seconds
Started Oct 18 12:27:32 PM PDT 23
Finished Oct 18 12:27:34 PM PDT 23
Peak memory 214724 kb
Host smart-ece150c3-7c3c-44ee-bc40-b8b5b5e31267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430024035611094557974005092573563588905826
8431186308807533298009247999601819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3430024035611094557974005092
5735635889058268431186308807533298009247999601819
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.57430763595149110662995234749366739865322866385294428759174782893452919323327
Short name T220
Test name
Test status
Simulation time 14091190 ps
CPU time 0.9 seconds
Started Oct 18 12:23:20 PM PDT 23
Finished Oct 18 12:23:21 PM PDT 23
Peak memory 206496 kb
Host smart-27a22465-eb2b-43fe-a778-daa0f20d641b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57430763595149110662995234749366739865322866385294428759174782893452919323327 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.57430763595149110662995234749366739865322866385294428759174782893452919323327
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.95139638358791365810569892569441223748116437339270510376108838766409509854453
Short name T264
Test name
Test status
Simulation time 15333613 ps
CPU time 0.88 seconds
Started Oct 18 12:27:23 PM PDT 23
Finished Oct 18 12:27:25 PM PDT 23
Peak memory 205468 kb
Host smart-75ecc436-7b9a-442b-93ed-6a1f5921818d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95139638358791365810569892569441223748116437339270510376108838766409509854453 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_intr_test.95139638358791365810569892569441223748116437339270510376108838766409509854453
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.113615082169902562825588565064764283091310207591048958924391463574671518620944
Short name T274
Test name
Test status
Simulation time 32384101 ps
CPU time 1.28 seconds
Started Oct 18 12:22:55 PM PDT 23
Finished Oct 18 12:22:57 PM PDT 23
Peak memory 206444 kb
Host smart-ca32dd6e-3692-4db2-8543-9a23ddcd0a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113615082169902562825588565064764283091310207591048958924391463574671518620944
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.113615082169902562825588565064764283091310207591048958924391463574671518620944
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.37296274513753452321993090936812050301683764917148362680401250905660002205534
Short name T243
Test name
Test status
Simulation time 100515346 ps
CPU time 3.5 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:33 PM PDT 23
Peak memory 214660 kb
Host smart-ebe2e468-f8bd-497e-a3f1-0053c7c52e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37296274513753452321993090936812050301683764917148362680401250905660002205534 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_tl_errors.37296274513753452321993090936812050301683764917148362680401250905660002205534
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.17950128789719156415279109592072115114147136682789436551092610785529754802734
Short name T225
Test name
Test status
Simulation time 87151723 ps
CPU time 2.27 seconds
Started Oct 18 12:26:50 PM PDT 23
Finished Oct 18 12:26:53 PM PDT 23
Peak memory 206360 kb
Host smart-01bcefd4-2635-4e3e-be8a-8b436a9848c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17950128789719156415279109592072115114147136682789436551092610785529754802734 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.17950128789719156415279109592072115114147136682789436551092610785529754802734
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.38023007399968091856981871902538421955363298674497103341565873173505153751030
Short name T238
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:22:39 PM PDT 23
Finished Oct 18 12:22:41 PM PDT 23
Peak memory 206408 kb
Host smart-24fe59c9-a344-4deb-82bb-c67f5307791c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38023007399968091856981871902538421955363298674497103341565873173505153751030 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 30.edn_intr_test.38023007399968091856981871902538421955363298674497103341565873173505153751030
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.37448765558409201857582163043746282106950385032512898456164791165822524801049
Short name T215
Test name
Test status
Simulation time 15333613 ps
CPU time 0.88 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:09 PM PDT 23
Peak memory 206040 kb
Host smart-c246fb4b-9928-47e5-a539-a1e6fa7c5ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37448765558409201857582163043746282106950385032512898456164791165822524801049 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 31.edn_intr_test.37448765558409201857582163043746282106950385032512898456164791165822524801049
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.61662845752561310837217985483350809650851483296316272509092644312931363449959
Short name T97
Test name
Test status
Simulation time 15333613 ps
CPU time 0.9 seconds
Started Oct 18 12:21:24 PM PDT 23
Finished Oct 18 12:21:25 PM PDT 23
Peak memory 206272 kb
Host smart-4255f456-ca57-4daf-bdba-bf0d912c0cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61662845752561310837217985483350809650851483296316272509092644312931363449959 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 32.edn_intr_test.61662845752561310837217985483350809650851483296316272509092644312931363449959
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.110760205890357008130803092340780723165860027677686221661826039882089769627661
Short name T290
Test name
Test status
Simulation time 15333613 ps
CPU time 0.84 seconds
Started Oct 18 12:26:55 PM PDT 23
Finished Oct 18 12:26:57 PM PDT 23
Peak memory 206100 kb
Host smart-8bd0d7e8-681b-4d54-92cc-c1aac58f4105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110760205890357008130803092340780723165860027677686221661826039882089769627661 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 33.edn_intr_test.110760205890357008130803092340780723165860027677686221661826039882089769627661
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.33210602022105454155159648458143009016533856914346926033077422222663870310691
Short name T82
Test name
Test status
Simulation time 15333613 ps
CPU time 0.88 seconds
Started Oct 18 12:25:15 PM PDT 23
Finished Oct 18 12:25:17 PM PDT 23
Peak memory 205260 kb
Host smart-d80f0a4d-3586-47f2-be02-9d48d94da2fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210602022105454155159648458143009016533856914346926033077422222663870310691 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 34.edn_intr_test.33210602022105454155159648458143009016533856914346926033077422222663870310691
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.60856105428685726727459704952112543673941211791808084938735975388411389086070
Short name T314
Test name
Test status
Simulation time 15333613 ps
CPU time 0.88 seconds
Started Oct 18 12:26:55 PM PDT 23
Finished Oct 18 12:26:56 PM PDT 23
Peak memory 206012 kb
Host smart-8771d327-4963-4533-8d41-549215170fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60856105428685726727459704952112543673941211791808084938735975388411389086070 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 35.edn_intr_test.60856105428685726727459704952112543673941211791808084938735975388411389086070
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.23281401545272644304816746877188317198474314596888959554131744651262106895561
Short name T321
Test name
Test status
Simulation time 15333613 ps
CPU time 0.89 seconds
Started Oct 18 12:21:43 PM PDT 23
Finished Oct 18 12:21:44 PM PDT 23
Peak memory 206232 kb
Host smart-19b380e5-2c6e-442f-b365-acf5d5fce8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23281401545272644304816746877188317198474314596888959554131744651262106895561 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 36.edn_intr_test.23281401545272644304816746877188317198474314596888959554131744651262106895561
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.34890108341890502428518682004140176199121098402454382079945830245117842258393
Short name T234
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:25:45 PM PDT 23
Finished Oct 18 12:25:47 PM PDT 23
Peak memory 206240 kb
Host smart-c55fe654-dbe0-41f6-98aa-af2cd5a5a126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34890108341890502428518682004140176199121098402454382079945830245117842258393 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 37.edn_intr_test.34890108341890502428518682004140176199121098402454382079945830245117842258393
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.12553222605638289333128178266072697396521395360163166397445421098730018607926
Short name T94
Test name
Test status
Simulation time 15333613 ps
CPU time 1.04 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:14 PM PDT 23
Peak memory 204720 kb
Host smart-07117c14-c833-40b9-be84-640b0d84869d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553222605638289333128178266072697396521395360163166397445421098730018607926 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 38.edn_intr_test.12553222605638289333128178266072697396521395360163166397445421098730018607926
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.9585145775041064996218092322011284581309513209848132273641579852198117469592
Short name T221
Test name
Test status
Simulation time 15333613 ps
CPU time 0.98 seconds
Started Oct 18 12:20:46 PM PDT 23
Finished Oct 18 12:20:47 PM PDT 23
Peak memory 204728 kb
Host smart-36f60b39-2410-4851-a408-591150b9ef65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9585145775041064996218092322011284581309513209848132273641579852198117469592 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 39.edn_intr_test.9585145775041064996218092322011284581309513209848132273641579852198117469592
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.68118171519711320639460247138524403567687447559542787452173720999227891843665
Short name T87
Test name
Test status
Simulation time 31808344 ps
CPU time 1.34 seconds
Started Oct 18 12:25:31 PM PDT 23
Finished Oct 18 12:25:33 PM PDT 23
Peak memory 206172 kb
Host smart-2ccfaf0f-45d8-43ac-ae71-eb2d3178da85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68118171519711320639460247138524403567687447559542787452173720999227891843665 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.68118171519711320639460247138524403567687447559542787452173720999227891843665
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.80024036422617662929678306918059771748238675023359230398673559848824492289164
Short name T244
Test name
Test status
Simulation time 175969816 ps
CPU time 4.7 seconds
Started Oct 18 12:25:34 PM PDT 23
Finished Oct 18 12:25:39 PM PDT 23
Peak memory 206468 kb
Host smart-1f1a22e6-7350-462d-9e9d-e4fe977e158b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80024036422617662929678306918059771748238675023359230398673559848824492289164 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.80024036422617662929678306918059771748238675023359230398673559848824492289164
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.94210925896078227919906455616176375033629806734193167681043320509498318362718
Short name T211
Test name
Test status
Simulation time 15899269 ps
CPU time 0.97 seconds
Started Oct 18 12:26:05 PM PDT 23
Finished Oct 18 12:26:07 PM PDT 23
Peak memory 205604 kb
Host smart-7e558a83-1cb9-4ee2-95b1-f12c0089b669
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94210925896078227919906455616176375033629806734193167681043320509498318362718 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.94210925896078227919906455616176375033629806734193167681043320509498318362718
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.55584495398310987212294038157995089807176089441057387718306280574874693057217
Short name T310
Test name
Test status
Simulation time 27767944 ps
CPU time 1.39 seconds
Started Oct 18 12:25:55 PM PDT 23
Finished Oct 18 12:25:57 PM PDT 23
Peak memory 213720 kb
Host smart-3293012d-623e-452e-9d69-f17919ef49fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5558449539831098721229403815799508980717608
9441057387718306280574874693057217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.5558449539831098721229403815
7995089807176089441057387718306280574874693057217
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.105473079468855625590115898612395691251549950375857897560918298880723689432327
Short name T218
Test name
Test status
Simulation time 14091190 ps
CPU time 0.91 seconds
Started Oct 18 12:24:13 PM PDT 23
Finished Oct 18 12:24:15 PM PDT 23
Peak memory 206516 kb
Host smart-ad5c9cd0-eb66-4e13-885d-7cb20185b19b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105473079468855625590115898612395691251549950375857897560918298880723689432327 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.105473079468855625590115898612395691251549950375857897560918298880723689432327
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.71553903322749157042656851222419207686049278694339155802184503236061776147486
Short name T232
Test name
Test status
Simulation time 15333613 ps
CPU time 0.87 seconds
Started Oct 18 12:26:07 PM PDT 23
Finished Oct 18 12:26:09 PM PDT 23
Peak memory 206124 kb
Host smart-f42da2cb-4584-4fda-8501-5a774df5d039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71553903322749157042656851222419207686049278694339155802184503236061776147486 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.edn_intr_test.71553903322749157042656851222419207686049278694339155802184503236061776147486
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.38334256218758547575044889182187498499481798850176512652855028705221529410354
Short name T91
Test name
Test status
Simulation time 32384101 ps
CPU time 1.33 seconds
Started Oct 18 12:20:35 PM PDT 23
Finished Oct 18 12:20:37 PM PDT 23
Peak memory 206464 kb
Host smart-39b99327-dd44-4800-bced-3a9fb4777698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334256218758547575044889182187498499481798850176512652855028705221529410354
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.38334256218758547575044889182187498499481798850176512652855028705221529410354
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.109866045208378642536369307646295002866056437456773761780116360541200762631543
Short name T235
Test name
Test status
Simulation time 100515346 ps
CPU time 3.54 seconds
Started Oct 18 12:25:51 PM PDT 23
Finished Oct 18 12:25:55 PM PDT 23
Peak memory 214412 kb
Host smart-c1bbd867-8a95-428e-8758-69a3a1fe8b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109866045208378642536369307646295002866056437456773761780116360541200762631543 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.edn_tl_errors.109866045208378642536369307646295002866056437456773761780116360541200762631543
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.62513379061272283657370670723536512120036025820940012481556437491809197167602
Short name T287
Test name
Test status
Simulation time 87151723 ps
CPU time 2.21 seconds
Started Oct 18 12:28:01 PM PDT 23
Finished Oct 18 12:28:04 PM PDT 23
Peak memory 206404 kb
Host smart-f6e26cb9-25d2-4cc5-9930-bc12bb2a7012
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62513379061272283657370670723536512120036025820940012481556437491809197167602 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.62513379061272283657370670723536512120036025820940012481556437491809197167602
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.70358796028825401874104198161005976900921661628812127757027039597528276218500
Short name T263
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:26:39 PM PDT 23
Finished Oct 18 12:26:41 PM PDT 23
Peak memory 206228 kb
Host smart-3dc4fa6b-0981-4dac-bd75-d96d3a55180e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70358796028825401874104198161005976900921661628812127757027039597528276218500 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 40.edn_intr_test.70358796028825401874104198161005976900921661628812127757027039597528276218500
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.6694724289418509604781270920925737814539510167193186887290554328560296601537
Short name T293
Test name
Test status
Simulation time 15333613 ps
CPU time 0.86 seconds
Started Oct 18 12:28:09 PM PDT 23
Finished Oct 18 12:28:11 PM PDT 23
Peak memory 206296 kb
Host smart-7b2eefbf-be30-4484-8b2e-61c3817e64a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6694724289418509604781270920925737814539510167193186887290554328560296601537 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 41.edn_intr_test.6694724289418509604781270920925737814539510167193186887290554328560296601537
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.248585931291148904800774338967497540834118526896236200112919121623152921617
Short name T252
Test name
Test status
Simulation time 15333613 ps
CPU time 0.84 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:31 PM PDT 23
Peak memory 205960 kb
Host smart-5555b9e4-30de-4554-8297-0c994b24df34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248585931291148904800774338967497540834118526896236200112919121623152921617 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 42.edn_intr_test.248585931291148904800774338967497540834118526896236200112919121623152921617
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.24930678325280705108676289600265196017065830533956775090047919288235566823401
Short name T216
Test name
Test status
Simulation time 15333613 ps
CPU time 0.84 seconds
Started Oct 18 12:27:49 PM PDT 23
Finished Oct 18 12:27:50 PM PDT 23
Peak memory 206272 kb
Host smart-1b799409-06cf-452b-b581-610ac8f59eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24930678325280705108676289600265196017065830533956775090047919288235566823401 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 43.edn_intr_test.24930678325280705108676289600265196017065830533956775090047919288235566823401
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.98985104784171406684309006644556093228860449190884093460900432932600953962082
Short name T207
Test name
Test status
Simulation time 15333613 ps
CPU time 0.89 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:17 PM PDT 23
Peak memory 206284 kb
Host smart-d8875e9c-d94c-4875-a822-551f07a9988d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98985104784171406684309006644556093228860449190884093460900432932600953962082 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 44.edn_intr_test.98985104784171406684309006644556093228860449190884093460900432932600953962082
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.29622292372583736401287912563979734264566446943092786575715098423638981650078
Short name T226
Test name
Test status
Simulation time 15333613 ps
CPU time 0.98 seconds
Started Oct 18 12:26:03 PM PDT 23
Finished Oct 18 12:26:05 PM PDT 23
Peak memory 205468 kb
Host smart-31e18598-147b-43b0-af6f-98cfcf679e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29622292372583736401287912563979734264566446943092786575715098423638981650078 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 45.edn_intr_test.29622292372583736401287912563979734264566446943092786575715098423638981650078
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.81736178718770639877688651693799037076919933487732596348177804634034194780534
Short name T332
Test name
Test status
Simulation time 15333613 ps
CPU time 0.91 seconds
Started Oct 18 12:26:14 PM PDT 23
Finished Oct 18 12:26:15 PM PDT 23
Peak memory 205508 kb
Host smart-4674bf11-2599-4c65-8390-3a25927547e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81736178718770639877688651693799037076919933487732596348177804634034194780534 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 46.edn_intr_test.81736178718770639877688651693799037076919933487732596348177804634034194780534
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.20257347386137494376379578334505028096697799954956948415431914297966419256356
Short name T313
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:26:14 PM PDT 23
Finished Oct 18 12:26:16 PM PDT 23
Peak memory 205892 kb
Host smart-7a8a1eb3-57de-4131-bf35-a84af3f28c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257347386137494376379578334505028096697799954956948415431914297966419256356 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 47.edn_intr_test.20257347386137494376379578334505028096697799954956948415431914297966419256356
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.47978309321187891989069083733808232833116432694463828102969542557278876334990
Short name T326
Test name
Test status
Simulation time 15333613 ps
CPU time 0.91 seconds
Started Oct 18 12:25:05 PM PDT 23
Finished Oct 18 12:25:06 PM PDT 23
Peak memory 206360 kb
Host smart-443d9530-3478-4672-9d5e-b3cde69c00a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47978309321187891989069083733808232833116432694463828102969542557278876334990 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 48.edn_intr_test.47978309321187891989069083733808232833116432694463828102969542557278876334990
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.86327736154324343378754372835512361296605575898357111639130389884845251372968
Short name T279
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:27:30 PM PDT 23
Finished Oct 18 12:27:31 PM PDT 23
Peak memory 206264 kb
Host smart-09601be0-b067-4083-88fb-bd0231965e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86327736154324343378754372835512361296605575898357111639130389884845251372968 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 49.edn_intr_test.86327736154324343378754372835512361296605575898357111639130389884845251372968
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.106214775041425755134931518748422343678251537169112251321484577644966727982406
Short name T306
Test name
Test status
Simulation time 27767944 ps
CPU time 1.33 seconds
Started Oct 18 12:20:35 PM PDT 23
Finished Oct 18 12:20:36 PM PDT 23
Peak memory 214796 kb
Host smart-512f1991-13b1-4689-91b9-8fa9c0405a96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062147750414257551349315187484223436782515
37169112251321484577644966727982406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.106214775041425755134931518
748422343678251537169112251321484577644966727982406
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.27612557307344232866987244133238557364862700760901722229860012192225774026182
Short name T286
Test name
Test status
Simulation time 14091190 ps
CPU time 0.89 seconds
Started Oct 18 12:21:07 PM PDT 23
Finished Oct 18 12:21:09 PM PDT 23
Peak memory 206452 kb
Host smart-c867ae1e-73c1-40a6-81ba-76dc9b0a9f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612557307344232866987244133238557364862700760901722229860012192225774026182 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.27612557307344232866987244133238557364862700760901722229860012192225774026182
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.102913683739811767069365778623100325771597405347760101963274043605917032133281
Short name T277
Test name
Test status
Simulation time 15333613 ps
CPU time 0.89 seconds
Started Oct 18 12:27:17 PM PDT 23
Finished Oct 18 12:27:18 PM PDT 23
Peak memory 205468 kb
Host smart-60441847-c007-46bd-8c93-ac0d50ae4766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102913683739811767069365778623100325771597405347760101963274043605917032133281 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.edn_intr_test.102913683739811767069365778623100325771597405347760101963274043605917032133281
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.64985044629686885542035534732927148129079900154126235207741552262887554900404
Short name T262
Test name
Test status
Simulation time 32384101 ps
CPU time 1.35 seconds
Started Oct 18 12:20:20 PM PDT 23
Finished Oct 18 12:20:22 PM PDT 23
Peak memory 206348 kb
Host smart-62bc25b4-32bd-45d8-8e00-f2cf103c52e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64985044629686885542035534732927148129079900154126235207741552262887554900404
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.64985044629686885542035534732927148129079900154126235207741552262887554900404
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.105369843631967891027324412239322752050454340068569750412349045979859143232990
Short name T239
Test name
Test status
Simulation time 100515346 ps
CPU time 3.69 seconds
Started Oct 18 12:21:37 PM PDT 23
Finished Oct 18 12:21:41 PM PDT 23
Peak memory 214284 kb
Host smart-372b06eb-2155-4c4a-9182-76685b1b2d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105369843631967891027324412239322752050454340068569750412349045979859143232990 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.edn_tl_errors.105369843631967891027324412239322752050454340068569750412349045979859143232990
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.33108378299830322296965606592244790810864725761090277294772487376267872396611
Short name T213
Test name
Test status
Simulation time 87151723 ps
CPU time 2.42 seconds
Started Oct 18 12:20:20 PM PDT 23
Finished Oct 18 12:20:22 PM PDT 23
Peak memory 206640 kb
Host smart-9b21f721-752d-4fd8-8762-f36baa09e5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33108378299830322296965606592244790810864725761090277294772487376267872396611 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.33108378299830322296965606592244790810864725761090277294772487376267872396611
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.46938760057905642716789910744359014052157660216200679885058305591136862134804
Short name T261
Test name
Test status
Simulation time 27767944 ps
CPU time 1.29 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:16 PM PDT 23
Peak memory 214756 kb
Host smart-21744d06-86bc-43e5-802d-0080f96f6f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4693876005790564271678991074435901405215766
0216200679885058305591136862134804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4693876005790564271678991074
4359014052157660216200679885058305591136862134804
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.101514007986274031377979066823184542167758941655468169188209798785564350984708
Short name T322
Test name
Test status
Simulation time 14091190 ps
CPU time 1.06 seconds
Started Oct 18 12:20:46 PM PDT 23
Finished Oct 18 12:20:47 PM PDT 23
Peak memory 205216 kb
Host smart-2cf64304-50b1-47e7-9879-c96270201f1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101514007986274031377979066823184542167758941655468169188209798785564350984708 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.101514007986274031377979066823184542167758941655468169188209798785564350984708
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.94870965291548410900259132326964774025095446869319163891416589171903983620095
Short name T330
Test name
Test status
Simulation time 15333613 ps
CPU time 0.9 seconds
Started Oct 18 12:22:14 PM PDT 23
Finished Oct 18 12:22:15 PM PDT 23
Peak memory 206612 kb
Host smart-4ae6b377-6bc8-43ae-8d22-3b45d2dec640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94870965291548410900259132326964774025095446869319163891416589171903983620095 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_intr_test.94870965291548410900259132326964774025095446869319163891416589171903983620095
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.114162902013232733368972829243310886799942477532644442980326316493214912999871
Short name T103
Test name
Test status
Simulation time 32384101 ps
CPU time 1.24 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:13 PM PDT 23
Peak memory 206440 kb
Host smart-621f2e93-9e75-4e7a-b2cb-bacc5cbf06a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114162902013232733368972829243310886799942477532644442980326316493214912999871
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.114162902013232733368972829243310886799942477532644442980326316493214912999871
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.70547406910611007214585324546587965452163155373323121449319903515659846529783
Short name T303
Test name
Test status
Simulation time 100515346 ps
CPU time 3.65 seconds
Started Oct 18 12:27:09 PM PDT 23
Finished Oct 18 12:27:13 PM PDT 23
Peak memory 214356 kb
Host smart-f0f6a7f3-46d7-4a46-9dfe-80a6d302e875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70547406910611007214585324546587965452163155373323121449319903515659846529783 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_tl_errors.70547406910611007214585324546587965452163155373323121449319903515659846529783
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.12919985302773774562281197651979964723324282735928308599607527084368844777385
Short name T307
Test name
Test status
Simulation time 87151723 ps
CPU time 2.32 seconds
Started Oct 18 12:20:33 PM PDT 23
Finished Oct 18 12:20:36 PM PDT 23
Peak memory 206464 kb
Host smart-dcd074b0-deb2-4795-9ba3-ca092c4a19b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919985302773774562281197651979964723324282735928308599607527084368844777385 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.12919985302773774562281197651979964723324282735928308599607527084368844777385
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.6365986792393866022630574906181022471709166855670740803492831402032289793104
Short name T309
Test name
Test status
Simulation time 27767944 ps
CPU time 1.28 seconds
Started Oct 18 12:26:23 PM PDT 23
Finished Oct 18 12:26:25 PM PDT 23
Peak memory 214488 kb
Host smart-8d13c89c-0d2c-4971-9f72-aed9422d445e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6365986792393866022630574906181022471709166
855670740803492831402032289793104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.63659867923938660226305749061
81022471709166855670740803492831402032289793104
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.69901189716927169711774177871789261054361409463872626627122457421690192744394
Short name T254
Test name
Test status
Simulation time 14091190 ps
CPU time 0.84 seconds
Started Oct 18 12:27:33 PM PDT 23
Finished Oct 18 12:27:34 PM PDT 23
Peak memory 206412 kb
Host smart-620ddb6c-7de3-4b23-a7d2-ed7bb499b3d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69901189716927169711774177871789261054361409463872626627122457421690192744394 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.69901189716927169711774177871789261054361409463872626627122457421690192744394
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.57992340157757466846314232321280520870358774731988462896498262509418477342974
Short name T229
Test name
Test status
Simulation time 15333613 ps
CPU time 0.87 seconds
Started Oct 18 12:25:30 PM PDT 23
Finished Oct 18 12:25:31 PM PDT 23
Peak memory 205456 kb
Host smart-08fb7df0-d0ad-44d1-b0c0-21338259a0a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57992340157757466846314232321280520870358774731988462896498262509418477342974 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_intr_test.57992340157757466846314232321280520870358774731988462896498262509418477342974
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.93810997866194743195179420751894590841594772127957451257334204414109977398174
Short name T89
Test name
Test status
Simulation time 32384101 ps
CPU time 1.34 seconds
Started Oct 18 12:23:31 PM PDT 23
Finished Oct 18 12:23:34 PM PDT 23
Peak memory 206444 kb
Host smart-62843f98-5c7b-4511-84c4-1f46c0cfb38d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93810997866194743195179420751894590841594772127957451257334204414109977398174
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.93810997866194743195179420751894590841594772127957451257334204414109977398174
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.61356534639229829358986230472531833848468582839943596680689990898737673427895
Short name T79
Test name
Test status
Simulation time 100515346 ps
CPU time 3.63 seconds
Started Oct 18 12:21:00 PM PDT 23
Finished Oct 18 12:21:04 PM PDT 23
Peak memory 214600 kb
Host smart-df06ab61-848c-4da6-9c1e-261133835c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61356534639229829358986230472531833848468582839943596680689990898737673427895 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_tl_errors.61356534639229829358986230472531833848468582839943596680689990898737673427895
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.29284476081472511917402957659443491122094290504601349777693784258298900423440
Short name T224
Test name
Test status
Simulation time 87151723 ps
CPU time 2.35 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:11 PM PDT 23
Peak memory 205288 kb
Host smart-ce8e022c-4100-4a08-b3b8-0e4318ffb553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284476081472511917402957659443491122094290504601349777693784258298900423440 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.29284476081472511917402957659443491122094290504601349777693784258298900423440
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.83881806982275247358961491170554689161602639657054498024949463246056995898003
Short name T275
Test name
Test status
Simulation time 27767944 ps
CPU time 1.33 seconds
Started Oct 18 12:22:11 PM PDT 23
Finished Oct 18 12:22:13 PM PDT 23
Peak memory 214772 kb
Host smart-936330db-9dd1-46c2-974e-d64636bb610f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8388180698227524735896149117055468916160263
9657054498024949463246056995898003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.8388180698227524735896149117
0554689161602639657054498024949463246056995898003
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.83550977895660809301319445366063912493782885444108028892328879952070869452320
Short name T228
Test name
Test status
Simulation time 14091190 ps
CPU time 0.91 seconds
Started Oct 18 12:21:19 PM PDT 23
Finished Oct 18 12:21:20 PM PDT 23
Peak memory 206644 kb
Host smart-11cce2a9-e497-4f26-a36e-f0bf13fe8389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83550977895660809301319445366063912493782885444108028892328879952070869452320 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.83550977895660809301319445366063912493782885444108028892328879952070869452320
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.47682286589383950413973829244646092718480012703377650145638527899865610610450
Short name T236
Test name
Test status
Simulation time 15333613 ps
CPU time 0.85 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:16 PM PDT 23
Peak memory 206036 kb
Host smart-0de5a35d-6795-4ae6-b6a7-3310ef91e17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47682286589383950413973829244646092718480012703377650145638527899865610610450 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.edn_intr_test.47682286589383950413973829244646092718480012703377650145638527899865610610450
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.561406137617964410720935455037398382882434708163043892541682900486428929370
Short name T278
Test name
Test status
Simulation time 32384101 ps
CPU time 1.39 seconds
Started Oct 18 12:27:15 PM PDT 23
Finished Oct 18 12:27:17 PM PDT 23
Peak memory 205592 kb
Host smart-97c78b29-5ebc-46b9-a2e7-eb31e50338a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561406137617964410720935455037398382882434708163043892541682900486428929370 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.561406137617964410720935455037398382882434708163043892541682900486428929370
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.113313586452720576153215685068231922938864193891392120656291570327211728418804
Short name T294
Test name
Test status
Simulation time 100515346 ps
CPU time 3.53 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:10 PM PDT 23
Peak memory 214356 kb
Host smart-9c3c7579-1d35-4f59-b7ba-23093df434d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113313586452720576153215685068231922938864193891392120656291570327211728418804 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.edn_tl_errors.113313586452720576153215685068231922938864193891392120656291570327211728418804
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.54202236095063773961399232021311130459232120990774348552765581106380580039561
Short name T248
Test name
Test status
Simulation time 87151723 ps
CPU time 2.34 seconds
Started Oct 18 12:28:18 PM PDT 23
Finished Oct 18 12:28:21 PM PDT 23
Peak memory 206416 kb
Host smart-a41ff1bf-6208-4f58-a922-5cc731d1ee07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54202236095063773961399232021311130459232120990774348552765581106380580039561 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.54202236095063773961399232021311130459232120990774348552765581106380580039561
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.89806984282009799358907408599081606213153329052874672141760071094157666947045
Short name T246
Test name
Test status
Simulation time 27767944 ps
CPU time 1.33 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:31 PM PDT 23
Peak memory 214676 kb
Host smart-451bd4f5-9585-47b2-a936-623a282275aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8980698428200979935890740859908160621315332
9052874672141760071094157666947045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.8980698428200979935890740859
9081606213153329052874672141760071094157666947045
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.98924253588642247862672094823896096792053905066029899167778449942866878660630
Short name T316
Test name
Test status
Simulation time 14091190 ps
CPU time 0.86 seconds
Started Oct 18 12:28:26 PM PDT 23
Finished Oct 18 12:28:28 PM PDT 23
Peak memory 206408 kb
Host smart-820de90f-7551-47e3-9367-cfcad6b7469d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98924253588642247862672094823896096792053905066029899167778449942866878660630 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.98924253588642247862672094823896096792053905066029899167778449942866878660630
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.98222199670466764227747613097493023804531242981565959078706448333528579058716
Short name T300
Test name
Test status
Simulation time 15333613 ps
CPU time 0.95 seconds
Started Oct 18 12:24:45 PM PDT 23
Finished Oct 18 12:24:46 PM PDT 23
Peak memory 206492 kb
Host smart-5cec97e8-122a-4856-87dd-644c48b1c64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98222199670466764227747613097493023804531242981565959078706448333528579058716 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.edn_intr_test.98222199670466764227747613097493023804531242981565959078706448333528579058716
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.107779559667464590196584281621809665913846956956255920837473849848840534493140
Short name T325
Test name
Test status
Simulation time 32384101 ps
CPU time 1.36 seconds
Started Oct 18 12:24:00 PM PDT 23
Finished Oct 18 12:24:02 PM PDT 23
Peak memory 206564 kb
Host smart-03934a5a-0ba0-42a6-a272-04e49ca378d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107779559667464590196584281621809665913846956956255920837473849848840534493140
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.107779559667464590196584281621809665913846956956255920837473849848840534493140
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.49501144077182387727022162428847844193750578303139022901422949931579497786360
Short name T302
Test name
Test status
Simulation time 100515346 ps
CPU time 3.52 seconds
Started Oct 18 12:28:05 PM PDT 23
Finished Oct 18 12:28:09 PM PDT 23
Peak memory 214508 kb
Host smart-c2589a2e-84a9-4887-b4ce-23681fd363ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49501144077182387727022162428847844193750578303139022901422949931579497786360 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.edn_tl_errors.49501144077182387727022162428847844193750578303139022901422949931579497786360
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.80612162129598705997148207066016674200172575530778382241444832006558761848285
Short name T295
Test name
Test status
Simulation time 87151723 ps
CPU time 2.34 seconds
Started Oct 18 12:26:14 PM PDT 23
Finished Oct 18 12:26:17 PM PDT 23
Peak memory 206120 kb
Host smart-63dc9dd3-86ee-4a4a-851f-89839919a692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80612162129598705997148207066016674200172575530778382241444832006558761848285 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.80612162129598705997148207066016674200172575530778382241444832006558761848285
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.97247775206348548151875371120876076311335656763841026875003189634264257828236
Short name T336
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205968 kb
Host smart-e5fd6500-8f34-4b46-b3d6-f57b01fd1823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97247775206348548151875371120876076311335656763841026875003189634264257828236 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_alert.97247775206348548151875371120876076311335656763841026875003189634264257828236
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.16504798353631498904995080378851426043566982869032583289807604799303327665311
Short name T667
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:29:49 PM PDT 23
Finished Oct 18 01:29:50 PM PDT 23
Peak memory 215260 kb
Host smart-107d14ea-afbc-45f9-b38c-82c5a4bcdec1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504798353631498904995080378851426043566982869032583289807604799303327665311 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.16504798353631498904995080378851426043566982869032583289807
604799303327665311
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.81502778410033174602191303188604833743480001554408092686678957509364625835933
Short name T641
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:29:51 PM PDT 23
Finished Oct 18 01:29:53 PM PDT 23
Peak memory 215248 kb
Host smart-e84682a6-8b95-4775-a561-ea0e7842ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81502778410033174602191303188604833743480001554408092686678957509364625835933 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
edn_err.81502778410033174602191303188604833743480001554408092686678957509364625835933
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.97474949800236237830581408815596266080640615799625932358455878235965680990087
Short name T134
Test name
Test status
Simulation time 22643412 ps
CPU time 0.94 seconds
Started Oct 18 01:29:47 PM PDT 23
Finished Oct 18 01:29:48 PM PDT 23
Peak memory 205816 kb
Host smart-d8016374-cc1d-4f99-ae43-cda8fb5d3c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97474949800236237830581408815596266080640615799625932358455878235965680990087 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.edn_genbits.97474949800236237830581408815596266080640615799625932358455878235965680990087
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.39084453305677977085991033800908215066024734082696801154280660338420552416693
Short name T580
Test name
Test status
Simulation time 22372583 ps
CPU time 0.98 seconds
Started Oct 18 01:30:10 PM PDT 23
Finished Oct 18 01:30:12 PM PDT 23
Peak memory 222992 kb
Host smart-65ee9b92-8d4c-4d34-8fee-7ab6f4e5fcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39084453305677977085991033800908215066024734082696801154280660338420552416693 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.edn_intr.39084453305677977085991033800908215066024734082696801154280660338420552416693
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.109416846219128920593389028107125926775334599433838234566511941281159198494423
Short name T109
Test name
Test status
Simulation time 19018470 ps
CPU time 0.81 seconds
Started Oct 18 01:29:34 PM PDT 23
Finished Oct 18 01:29:36 PM PDT 23
Peak memory 205620 kb
Host smart-f41d9f74-04fa-41b1-80b4-321d950e9ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109416846219128920593389028107125926775334599433838234566511941281159198494423 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.edn_regwen.109416846219128920593389028107125926775334599433838234566511941281159198494423
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.97420998124253391460603776595753062083933603613516245992010608658805679840309
Short name T27
Test name
Test status
Simulation time 359808016 ps
CPU time 6.04 seconds
Started Oct 18 01:30:10 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 235592 kb
Host smart-fcd5ee74-edb8-4b8f-8a85-b70549ba5fea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97420998124253391460603776595753062083933603613516245992010608658805679840309 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_sec_cm.97420998124253391460603776595753062083933603613516245992010608658805679840309
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.94590558875869527355524787181005387969887440124722759372527104137266737775799
Short name T165
Test name
Test status
Simulation time 21768426 ps
CPU time 0.82 seconds
Started Oct 18 01:29:22 PM PDT 23
Finished Oct 18 01:29:23 PM PDT 23
Peak memory 205556 kb
Host smart-082c03a3-c43f-4fb9-ba57-f946081b4064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94590558875869527355524787181005387969887440124722759372527104137266737775799 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_smoke.94590558875869527355524787181005387969887440124722759372527104137266737775799
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.94716001511499936064067723385582684838846634121046787854942563075493536202239
Short name T699
Test name
Test status
Simulation time 299451483 ps
CPU time 3.59 seconds
Started Oct 18 01:29:32 PM PDT 23
Finished Oct 18 01:29:36 PM PDT 23
Peak memory 206420 kb
Host smart-f5f93ab0-b2b1-4be8-b6ef-f9be9ce452fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94716001511499936064067723385582684838846634121046787854942563075493536202239 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.94716001511499936064067723385582684838846634121046787854942563075493536202239
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.56842653316537170966709243198952397643003944126423818539229462526469549813024
Short name T556
Test name
Test status
Simulation time 86880545330 ps
CPU time 1120.81 seconds
Started Oct 18 01:29:43 PM PDT 23
Finished Oct 18 01:48:24 PM PDT 23
Peak memory 218616 kb
Host smart-0c0642b2-77f6-44a2-b7a6-1d1a47fc4fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568426533165371709667092431
98952397643003944126423818539229462526469549813024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.568426533165
37170966709243198952397643003944126423818539229462526469549813024
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.85711107023189080975414021892226730006289896435925161454681174579532483237642
Short name T608
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:43 PM PDT 23
Peak memory 205968 kb
Host smart-e0c98d15-00f4-41e1-a49b-774b4480d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85711107023189080975414021892226730006289896435925161454681174579532483237642 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_alert.85711107023189080975414021892226730006289896435925161454681174579532483237642
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.15792689258326607277285191674374999733764311019150329542770312654533166486007
Short name T361
Test name
Test status
Simulation time 16111390 ps
CPU time 0.93 seconds
Started Oct 18 01:30:12 PM PDT 23
Finished Oct 18 01:30:13 PM PDT 23
Peak memory 206040 kb
Host smart-d8d7fab5-aa83-4521-87a6-9ec71b6acd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15792689258326607277285191674374999733764311019150329542770312654533166486007 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_alert_test.15792689258326607277285191674374999733764311019150329542770312654533166486007
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.5986131540610670548929935114317924522895717698588248016269794321297819769324
Short name T612
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 215008 kb
Host smart-98a5a179-519d-4d54-84d8-497c5f32532c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5986131540610670548929935114317924522895717698588248016269794321297819769324 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_disable.5986131540610670548929935114317924522895717698588248016269794321297819769324
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.30455719695400386342272598540741033750218383416070393973651898897787778523990
Short name T376
Test name
Test status
Simulation time 30622451 ps
CPU time 0.94 seconds
Started Oct 18 01:31:04 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 215280 kb
Host smart-e4b4d9c8-86de-40d3-971b-e09e0c3a7be2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30455719695400386342272598540741033750218383416070393973651898897787778523990 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.30455719695400386342272598540741033750218383416070393973651
898897787778523990
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.40614467876265195772684362719332134646008499525997188565027106287797398724356
Short name T116
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:30:09 PM PDT 23
Finished Oct 18 01:30:10 PM PDT 23
Peak memory 215224 kb
Host smart-59c323a9-a01d-4a0f-b103-7fa657d7bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40614467876265195772684362719332134646008499525997188565027106287797398724356 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
edn_err.40614467876265195772684362719332134646008499525997188565027106287797398724356
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2320890872531770109226609727634066360693735705826747724788435690150467108170
Short name T441
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 205752 kb
Host smart-e0e3bf1b-619b-4f3f-b2a3-4d3135a77c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320890872531770109226609727634066360693735705826747724788435690150467108170 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.edn_genbits.2320890872531770109226609727634066360693735705826747724788435690150467108170
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.79675436629341420116782512115149723411517387188325730150053135735619007135715
Short name T510
Test name
Test status
Simulation time 22372583 ps
CPU time 1.04 seconds
Started Oct 18 01:30:03 PM PDT 23
Finished Oct 18 01:30:05 PM PDT 23
Peak memory 222796 kb
Host smart-1867a6c3-e78c-4bb2-9f4b-c1e4a3367f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79675436629341420116782512115149723411517387188325730150053135735619007135715 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.edn_intr.79675436629341420116782512115149723411517387188325730150053135735619007135715
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.68487035280098617579394233633811026368299792519044117396555867898822978004172
Short name T497
Test name
Test status
Simulation time 19018470 ps
CPU time 0.84 seconds
Started Oct 18 01:29:50 PM PDT 23
Finished Oct 18 01:29:51 PM PDT 23
Peak memory 205640 kb
Host smart-3aa630b0-4eae-4309-bfa3-ba5207be00bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68487035280098617579394233633811026368299792519044117396555867898822978004172 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.edn_regwen.68487035280098617579394233633811026368299792519044117396555867898822978004172
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.35496648772939562191059904748993874802850728340427773385711871649901729495753
Short name T37
Test name
Test status
Simulation time 359808016 ps
CPU time 5.92 seconds
Started Oct 18 01:30:09 PM PDT 23
Finished Oct 18 01:30:15 PM PDT 23
Peak memory 235484 kb
Host smart-3250f2dd-a41e-4531-8464-b97917b8e170
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35496648772939562191059904748993874802850728340427773385711871649901729495753 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_sec_cm.35496648772939562191059904748993874802850728340427773385711871649901729495753
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.85270955046327962178234266978696673644904842582560952964068136824202031931683
Short name T420
Test name
Test status
Simulation time 21768426 ps
CPU time 0.82 seconds
Started Oct 18 01:29:27 PM PDT 23
Finished Oct 18 01:29:29 PM PDT 23
Peak memory 205636 kb
Host smart-bba437fd-760d-4c9b-92e8-f2976f661a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85270955046327962178234266978696673644904842582560952964068136824202031931683 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_smoke.85270955046327962178234266978696673644904842582560952964068136824202031931683
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.9855064426107022882643590178990749961579795747003727085035550211134294477218
Short name T685
Test name
Test status
Simulation time 299451483 ps
CPU time 3.69 seconds
Started Oct 18 01:29:38 PM PDT 23
Finished Oct 18 01:29:43 PM PDT 23
Peak memory 206536 kb
Host smart-67482fed-2e47-4559-8faa-cb26e1f2d482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9855064426107022882643590178990749961579795747003727085035550211134294477218 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.9855064426107022882643590178990749961579795747003727085035550211134294477218
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.68506558778353008984219445823874179965986822256386740550848512811834707297717
Short name T338
Test name
Test status
Simulation time 86880545330 ps
CPU time 1091.58 seconds
Started Oct 18 01:29:43 PM PDT 23
Finished Oct 18 01:47:55 PM PDT 23
Peak memory 218624 kb
Host smart-4614afa8-e7ee-4940-96bf-a47d63f1429f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685065587783530089842194458
23874179965986822256386740550848512811834707297717 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.685065587783
53008984219445823874179965986822256386740550848512811834707297717
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.69515951206285243924883339195221384212937234920899441761425611658237502131887
Short name T127
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:29:38 PM PDT 23
Finished Oct 18 01:29:39 PM PDT 23
Peak memory 206008 kb
Host smart-671222b2-bd74-41bc-9689-adf3b296ceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69515951206285243924883339195221384212937234920899441761425611658237502131887 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_alert.69515951206285243924883339195221384212937234920899441761425611658237502131887
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.89041259545821329007165730360680726796570570961667096506748025539236272778327
Short name T411
Test name
Test status
Simulation time 16111390 ps
CPU time 0.92 seconds
Started Oct 18 01:30:40 PM PDT 23
Finished Oct 18 01:30:42 PM PDT 23
Peak memory 205984 kb
Host smart-a7c51549-1d8d-4cb2-b1c2-e1d66b825c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89041259545821329007165730360680726796570570961667096506748025539236272778327 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_alert_test.89041259545821329007165730360680726796570570961667096506748025539236272778327
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.88550538224843575318700843734774396345778664263041322675274554659193690992781
Short name T444
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:05 PM PDT 23
Finished Oct 18 01:30:07 PM PDT 23
Peak memory 215012 kb
Host smart-6065d857-9e02-48ef-9bbb-f5694efc6bd3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88550538224843575318700843734774396345778664263041322675274554659193690992781 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.edn_disable.88550538224843575318700843734774396345778664263041322675274554659193690992781
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.105613279075168246795352086436637624403289675721205728650670162022525114854860
Short name T57
Test name
Test status
Simulation time 30622451 ps
CPU time 0.93 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 215260 kb
Host smart-3ad82f82-fff5-465c-9706-534b9f60715e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105613279075168246795352086436637624403289675721205728650670162022525114854860 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.105613279075168246795352086436637624403289675721205728650
670162022525114854860
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.92916240257540444364433432638110848280638149695768633584269352548010171975638
Short name T672
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 215292 kb
Host smart-4eeb083f-89f9-483d-9666-8dee91209e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92916240257540444364433432638110848280638149695768633584269352548010171975638 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.edn_err.92916240257540444364433432638110848280638149695768633584269352548010171975638
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.10523051825417257031322887908069413864157983122146974247949851341594099128654
Short name T428
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 205752 kb
Host smart-ee56a0d3-aee2-4909-93f1-7671ccc5ab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10523051825417257031322887908069413864157983122146974247949851341594099128654 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.edn_genbits.10523051825417257031322887908069413864157983122146974247949851341594099128654
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.47262576737268140952412264507067282088990345789920858446517857946021233022739
Short name T589
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:44 PM PDT 23
Peak memory 205656 kb
Host smart-7fae9858-5b83-4505-9a32-c11d148f1162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47262576737268140952412264507067282088990345789920858446517857946021233022739 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_smoke.47262576737268140952412264507067282088990345789920858446517857946021233022739
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.106172068493740630022187200662161855351322546814778227410202209832064351591701
Short name T490
Test name
Test status
Simulation time 299451483 ps
CPU time 3.82 seconds
Started Oct 18 01:31:00 PM PDT 23
Finished Oct 18 01:31:04 PM PDT 23
Peak memory 206500 kb
Host smart-6b393efe-b2e5-4101-bfed-0f0893c4982a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106172068493740630022187200662161855351322546814778227410202209832064351591701 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.106172068493740630022187200662161855351322546814778227410202209832064351591701
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.46041761652733828179743214319476805614038751800344608476953032228532975191084
Short name T659
Test name
Test status
Simulation time 86880545330 ps
CPU time 1104.8 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:48:09 PM PDT 23
Peak memory 218552 kb
Host smart-70a2888c-bf3e-43d7-95be-4a46205e88d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460417616527338281797432143
19476805614038751800344608476953032228532975191084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.46041761652
733828179743214319476805614038751800344608476953032228532975191084
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert_test.71300086361308019516252141461102451849456279023032362932748064360155180535140
Short name T651
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:30:51 PM PDT 23
Finished Oct 18 01:30:52 PM PDT 23
Peak memory 205984 kb
Host smart-cf296c69-9425-4596-a57e-11c938f38bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71300086361308019516252141461102451849456279023032362932748064360155180535140 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_alert_test.71300086361308019516252141461102451849456279023032362932748064360155180535140
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.84197333136811302615904945714271493524640033332287911755002857884690673749294
Short name T595
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 215140 kb
Host smart-581736dc-f533-433c-a0aa-5a628db72cda
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84197333136811302615904945714271493524640033332287911755002857884690673749294 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.edn_disable.84197333136811302615904945714271493524640033332287911755002857884690673749294
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.52123901475882547076850802447656923882500836197890032075610738266450909805888
Short name T545
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 215288 kb
Host smart-8e2c2680-5544-425e-a175-b13f8face170
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52123901475882547076850802447656923882500836197890032075610738266450909805888 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.5212390147588254707685080244765692388250083619789003207561
0738266450909805888
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.27234886899001945272517014179973077344933034629980956076380872709546775870937
Short name T121
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 215308 kb
Host smart-f1914345-c668-4cd1-b211-7a27531f7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27234886899001945272517014179973077344933034629980956076380872709546775870937 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.edn_err.27234886899001945272517014179973077344933034629980956076380872709546775870937
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.111939398085965476067726892426539638313540763056219096705068052083976778745439
Short name T605
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 222908 kb
Host smart-f9032769-220d-45ac-81e8-7b4f507a4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111939398085965476067726892426539638313540763056219096705068052083976778745439 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.edn_intr.111939398085965476067726892426539638313540763056219096705068052083976778745439
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.7820276082499181458267312851646840820994069307987741052440494712248279338033
Short name T157
Test name
Test status
Simulation time 21768426 ps
CPU time 0.83 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205760 kb
Host smart-07e0994b-2151-4b81-bf19-7fc52c97adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7820276082499181458267312851646840820994069307987741052440494712248279338033 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.edn_smoke.7820276082499181458267312851646840820994069307987741052440494712248279338033
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.98937865645312594777883522029670215958483542513308511151146550884356550485984
Short name T494
Test name
Test status
Simulation time 299451483 ps
CPU time 3.59 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 206428 kb
Host smart-98959f7c-e429-44b3-a82d-70caef6451c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98937865645312594777883522029670215958483542513308511151146550884356550485984 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.98937865645312594777883522029670215958483542513308511151146550884356550485984
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.99055289291020346901882021772192691780219449879658476926662539640374986550741
Short name T569
Test name
Test status
Simulation time 86880545330 ps
CPU time 1125.73 seconds
Started Oct 18 01:30:12 PM PDT 23
Finished Oct 18 01:48:59 PM PDT 23
Peak memory 218648 kb
Host smart-9d739ddf-e996-4562-960f-8de9ac3ba1a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990552892910203469018820217
72192691780219449879658476926662539640374986550741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.99055289291
020346901882021772192691780219449879658476926662539640374986550741
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.70278095064512810607122683181020030805107600797887770990841759196272734650921
Short name T652
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 206016 kb
Host smart-fc2967e3-0864-4593-9dd2-2c8e9857f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70278095064512810607122683181020030805107600797887770990841759196272734650921 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.edn_alert.70278095064512810607122683181020030805107600797887770990841759196272734650921
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2427915715762712187600988353812621018247858265802320850680159057190699434321
Short name T61
Test name
Test status
Simulation time 16111390 ps
CPU time 0.94 seconds
Started Oct 18 01:29:48 PM PDT 23
Finished Oct 18 01:29:50 PM PDT 23
Peak memory 206012 kb
Host smart-43fe56c4-bf9d-4a21-85a9-6f7c41638e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427915715762712187600988353812621018247858265802320850680159057190699434321 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_alert_test.2427915715762712187600988353812621018247858265802320850680159057190699434321
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.87814482538334991231692483933039484883830458250930114467704538444449492282725
Short name T482
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:29:55 PM PDT 23
Finished Oct 18 01:29:56 PM PDT 23
Peak memory 215156 kb
Host smart-4ea9eba2-a6ae-4bdc-b2de-6d9e52d793a3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87814482538334991231692483933039484883830458250930114467704538444449492282725 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.edn_disable.87814482538334991231692483933039484883830458250930114467704538444449492282725
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.60536669427533809939792166082433207589609245415079651210439977979366735349882
Short name T690
Test name
Test status
Simulation time 30622451 ps
CPU time 0.88 seconds
Started Oct 18 01:30:34 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 215204 kb
Host smart-3e8a01e1-4b18-42d2-8bb6-421160e06889
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60536669427533809939792166082433207589609245415079651210439977979366735349882 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.6053666942753380993979216608243320758960924541507965121043
9977979366735349882
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.44882724844924060193406059154621009800708752006049302362745375120926690762202
Short name T686
Test name
Test status
Simulation time 29871889 ps
CPU time 0.95 seconds
Started Oct 18 01:29:39 PM PDT 23
Finished Oct 18 01:29:40 PM PDT 23
Peak memory 215284 kb
Host smart-d5de1bd8-e5ee-4424-b729-7cbfc889ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44882724844924060193406059154621009800708752006049302362745375120926690762202 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.edn_err.44882724844924060193406059154621009800708752006049302362745375120926690762202
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.109275988926788413072584955075848831310070795856937480946167806277560865068437
Short name T122
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 205764 kb
Host smart-1564a54b-25fc-4e38-a09d-628c1a85b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109275988926788413072584955075848831310070795856937480946167806277560865068437 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.edn_genbits.109275988926788413072584955075848831310070795856937480946167806277560865068437
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.44589812412102285361003467835673143873186296133025585791851359556454357707639
Short name T34
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 222872 kb
Host smart-e643e565-4c8a-4e56-8fa7-0b616a14930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44589812412102285361003467835673143873186296133025585791851359556454357707639 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.edn_intr.44589812412102285361003467835673143873186296133025585791851359556454357707639
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.44949636713560377759022295132278370974212994611900564344328657933696803022539
Short name T601
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205648 kb
Host smart-dea1c056-b6b3-418b-846c-55859b642a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44949636713560377759022295132278370974212994611900564344328657933696803022539 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.edn_smoke.44949636713560377759022295132278370974212994611900564344328657933696803022539
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.109006555057008897361371217103766166504616710069464538338140222291105495508648
Short name T618
Test name
Test status
Simulation time 299451483 ps
CPU time 3.81 seconds
Started Oct 18 01:30:55 PM PDT 23
Finished Oct 18 01:30:59 PM PDT 23
Peak memory 206536 kb
Host smart-6c01a740-34bc-4f06-9e8e-7d77e4e1a8e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109006555057008897361371217103766166504616710069464538338140222291105495508648 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.109006555057008897361371217103766166504616710069464538338140222291105495508648
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.100835363399444136902157868489770810352771559017457724150424499315817727712141
Short name T566
Test name
Test status
Simulation time 86880545330 ps
CPU time 1119.87 seconds
Started Oct 18 01:30:49 PM PDT 23
Finished Oct 18 01:49:29 PM PDT 23
Peak memory 218608 kb
Host smart-7624f318-4893-49d6-ae7b-dae58d12da9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100835363399444136902157868
489770810352771559017457724150424499315817727712141 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1008353633
99444136902157868489770810352771559017457724150424499315817727712141
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.113286952721844236003569343471608386027572715474669257896391352525220851365799
Short name T485
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:29:48 PM PDT 23
Finished Oct 18 01:29:55 PM PDT 23
Peak memory 205996 kb
Host smart-5f9d0623-0be9-4bac-99ee-07cb52a509e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113286952721844236003569343471608386027572715474669257896391352525220851365799 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.edn_alert.113286952721844236003569343471608386027572715474669257896391352525220851365799
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.107967196850391191106054406821969356623771544542090844228107241435913031964720
Short name T704
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:29:57 PM PDT 23
Finished Oct 18 01:29:58 PM PDT 23
Peak memory 206016 kb
Host smart-35f72b78-604d-48e2-9baf-b4c90e20eacb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107967196850391191106054406821969356623771544542090844228107241435913031964720 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_alert_test.107967196850391191106054406821969356623771544542090844228107241435913031964720
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.85317302289009203156130269848389015101584106548344217134519647276352304846030
Short name T144
Test name
Test status
Simulation time 19976788 ps
CPU time 0.88 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:29:45 PM PDT 23
Peak memory 215016 kb
Host smart-11ace86b-eb35-4a7f-a71a-b7a26b6dab35
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85317302289009203156130269848389015101584106548344217134519647276352304846030 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.edn_disable.85317302289009203156130269848389015101584106548344217134519647276352304846030
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.14857265478679001024871401611858163356172629724675516515559193699146172395568
Short name T31
Test name
Test status
Simulation time 30622451 ps
CPU time 0.97 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:18 PM PDT 23
Peak memory 215228 kb
Host smart-1340cc29-323a-4bd5-870c-b5fe1a0a06e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857265478679001024871401611858163356172629724675516515559193699146172395568 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.1485726547867900102487140161185816335617262972467551651555
9193699146172395568
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.111231668151436213351307326812862169988660678283197465923335671048129724607570
Short name T676
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:29:51 PM PDT 23
Finished Oct 18 01:29:53 PM PDT 23
Peak memory 215284 kb
Host smart-486a20c0-2614-401e-b793-0349f78b10e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111231668151436213351307326812862169988660678283197465923335671048129724607570 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.edn_err.111231668151436213351307326812862169988660678283197465923335671048129724607570
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.94355565124930146556513052364937394090695256842301871111573109732085522108634
Short name T551
Test name
Test status
Simulation time 22643412 ps
CPU time 0.92 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 205756 kb
Host smart-08ee4226-f995-4df4-b56f-b516dbfa18ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94355565124930146556513052364937394090695256842301871111573109732085522108634 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.edn_genbits.94355565124930146556513052364937394090695256842301871111573109732085522108634
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.63031784678703492789297376957389995364192969039645258180354504852881520684678
Short name T486
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:29:46 PM PDT 23
Finished Oct 18 01:29:48 PM PDT 23
Peak memory 222944 kb
Host smart-c1c07707-aa33-4723-8789-2d87658be034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63031784678703492789297376957389995364192969039645258180354504852881520684678 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.edn_intr.63031784678703492789297376957389995364192969039645258180354504852881520684678
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_stress_all.43283362565685182557434545214594213519051741115597536466305696180484956533080
Short name T664
Test name
Test status
Simulation time 299451483 ps
CPU time 3.49 seconds
Started Oct 18 01:29:37 PM PDT 23
Finished Oct 18 01:29:40 PM PDT 23
Peak memory 206532 kb
Host smart-15cd4689-2e33-4eb7-99fe-88aeaf3f4018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43283362565685182557434545214594213519051741115597536466305696180484956533080 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.43283362565685182557434545214594213519051741115597536466305696180484956533080
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.50946765571331788197680424275116843170484571388420455982332992194864955638939
Short name T695
Test name
Test status
Simulation time 86880545330 ps
CPU time 1105.43 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:48:47 PM PDT 23
Peak memory 218652 kb
Host smart-6521597b-583d-4288-a037-2b57c659944e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509467655713317881976804242
75116843170484571388420455982332992194864955638939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.50946765571
331788197680424275116843170484571388420455982332992194864955638939
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert.70625393283880396645216032378479035908341811963053758744258767925696042701614
Short name T724
Test name
Test status
Simulation time 32330757 ps
CPU time 1 seconds
Started Oct 18 01:31:12 PM PDT 23
Finished Oct 18 01:31:14 PM PDT 23
Peak memory 205972 kb
Host smart-8a943806-a90c-401c-8d4f-16b61642fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70625393283880396645216032378479035908341811963053758744258767925696042701614 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_alert.70625393283880396645216032378479035908341811963053758744258767925696042701614
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.53752559231351695038080993359337639073288104018184187812832211618422638100431
Short name T461
Test name
Test status
Simulation time 16111390 ps
CPU time 0.92 seconds
Started Oct 18 01:30:55 PM PDT 23
Finished Oct 18 01:30:56 PM PDT 23
Peak memory 205960 kb
Host smart-5a6e5083-cf2f-43bc-83c9-9156cd8bf62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53752559231351695038080993359337639073288104018184187812832211618422638100431 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_alert_test.53752559231351695038080993359337639073288104018184187812832211618422638100431
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.72707253866332949769222310875086030334031163123259057465953295789590086951809
Short name T412
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 215128 kb
Host smart-2ff92fc8-5b83-41e0-ac4a-0ce670efaf3e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72707253866332949769222310875086030334031163123259057465953295789590086951809 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.edn_disable.72707253866332949769222310875086030334031163123259057465953295789590086951809
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.90051810474208117940459198238904182356031065362187007529552809678881721448521
Short name T58
Test name
Test status
Simulation time 30622451 ps
CPU time 0.9 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 214344 kb
Host smart-5cd5161d-79f1-42a7-b5e7-953d29916897
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90051810474208117940459198238904182356031065362187007529552809678881721448521 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.9005181047420811794045919823890418235603106536218700752955
2809678881721448521
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.78451027568440043502131977551484030861247132235835867856875466139708279770104
Short name T123
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:30:55 PM PDT 23
Finished Oct 18 01:30:56 PM PDT 23
Peak memory 215236 kb
Host smart-510cd68f-205f-414a-b287-780ab7ccf67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78451027568440043502131977551484030861247132235835867856875466139708279770104 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.edn_err.78451027568440043502131977551484030861247132235835867856875466139708279770104
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.23641417746331975072142922096942745844031214685277250403307791782463712686835
Short name T454
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 205760 kb
Host smart-0c9aeef2-5497-4454-a575-daf12c2ed6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23641417746331975072142922096942745844031214685277250403307791782463712686835 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.edn_genbits.23641417746331975072142922096942745844031214685277250403307791782463712686835
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.34112151447765387422821928305789569766809149346073186295440548977987266213323
Short name T674
Test name
Test status
Simulation time 22372583 ps
CPU time 1.04 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 222956 kb
Host smart-5a67b819-b90c-4cbf-94fd-1eb906e111ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34112151447765387422821928305789569766809149346073186295440548977987266213323 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.edn_intr.34112151447765387422821928305789569766809149346073186295440548977987266213323
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.28599710551683038996356578423072405402972181360384932528234825249616174361154
Short name T709
Test name
Test status
Simulation time 21768426 ps
CPU time 0.87 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 205688 kb
Host smart-bc2b4977-893a-4e3e-bfb9-2d602fc9393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28599710551683038996356578423072405402972181360384932528234825249616174361154 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_smoke.28599710551683038996356578423072405402972181360384932528234825249616174361154
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.68568339310505190254576239043264226249292776363906145261359721991560891984139
Short name T159
Test name
Test status
Simulation time 299451483 ps
CPU time 3.7 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 206500 kb
Host smart-f7028def-0dc3-40cd-b287-acbf55d9ad28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68568339310505190254576239043264226249292776363906145261359721991560891984139 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.68568339310505190254576239043264226249292776363906145261359721991560891984139
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.83945074456250724029845115644643140560970512275009656698200986589159405170977
Short name T161
Test name
Test status
Simulation time 86880545330 ps
CPU time 1042.41 seconds
Started Oct 18 01:30:13 PM PDT 23
Finished Oct 18 01:47:36 PM PDT 23
Peak memory 218652 kb
Host smart-82997cda-478a-4046-b680-1e7c96bf6410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839450744562507240298451156
44643140560970512275009656698200986589159405170977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.83945074456
250724029845115644643140560970512275009656698200986589159405170977
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_alert.108104515509431348646462204138273243387331801433082946007542468998311226199021
Short name T189
Test name
Test status
Simulation time 32330757 ps
CPU time 0.98 seconds
Started Oct 18 01:29:53 PM PDT 23
Finished Oct 18 01:29:55 PM PDT 23
Peak memory 205968 kb
Host smart-1faccfc5-633d-4042-8903-0c3b077f2e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108104515509431348646462204138273243387331801433082946007542468998311226199021 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.edn_alert.108104515509431348646462204138273243387331801433082946007542468998311226199021
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.72517957301305014012178910915941214802006359731583815488725266091346813871104
Short name T374
Test name
Test status
Simulation time 16111390 ps
CPU time 0.95 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:15 PM PDT 23
Peak memory 206004 kb
Host smart-2d04fb59-3f02-4150-8b2e-46c9836ddc80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72517957301305014012178910915941214802006359731583815488725266091346813871104 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_alert_test.72517957301305014012178910915941214802006359731583815488725266091346813871104
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.45615701691551956343603010326964970129959092776591975383006053139453956294869
Short name T427
Test name
Test status
Simulation time 19976788 ps
CPU time 0.87 seconds
Started Oct 18 01:30:11 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 215092 kb
Host smart-cc09f46b-1dba-4bcf-b81a-590a40e6125e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45615701691551956343603010326964970129959092776591975383006053139453956294869 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.edn_disable.45615701691551956343603010326964970129959092776591975383006053139453956294869
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.65543022843942358649328820404535524760076964243611787370533520030155457001710
Short name T532
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:29:48 PM PDT 23
Finished Oct 18 01:29:50 PM PDT 23
Peak memory 215304 kb
Host smart-58160ed6-b517-4bee-be47-c95e0c19afab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65543022843942358649328820404535524760076964243611787370533520030155457001710 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.6554302284394235864932882040453552476007696424361178737053
3520030155457001710
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.50451947247403120792299043835931864793839569677946454643350998237534891286050
Short name T364
Test name
Test status
Simulation time 29871889 ps
CPU time 0.95 seconds
Started Oct 18 01:29:40 PM PDT 23
Finished Oct 18 01:29:41 PM PDT 23
Peak memory 215300 kb
Host smart-ba12f8e2-88b2-43a1-8ee1-2ee6191521aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50451947247403120792299043835931864793839569677946454643350998237534891286050 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.edn_err.50451947247403120792299043835931864793839569677946454643350998237534891286050
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.43650045748455036092962634313036136722187531091396410677476223847681378855135
Short name T179
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:31:01 PM PDT 23
Peak memory 205768 kb
Host smart-4b6ab7e0-2299-4d3b-bedc-e1ce08b5b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43650045748455036092962634313036136722187531091396410677476223847681378855135 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.edn_genbits.43650045748455036092962634313036136722187531091396410677476223847681378855135
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.91631391411847092231430791271514501276693272143127761366163378215751645638016
Short name T613
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:29:45 PM PDT 23
Finished Oct 18 01:29:46 PM PDT 23
Peak memory 222932 kb
Host smart-487d5b05-6056-4275-9a1f-1de87d47d996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91631391411847092231430791271514501276693272143127761366163378215751645638016 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.edn_intr.91631391411847092231430791271514501276693272143127761366163378215751645638016
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.36351461754985394123396927062318943367640174902918762876814784948682742637352
Short name T466
Test name
Test status
Simulation time 21768426 ps
CPU time 0.88 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:31:00 PM PDT 23
Peak memory 205676 kb
Host smart-8d2494ce-4926-44fc-84cf-6c726013fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36351461754985394123396927062318943367640174902918762876814784948682742637352 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.edn_smoke.36351461754985394123396927062318943367640174902918762876814784948682742637352
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.96245470967612024734801544533971051701307712830326831285239394786924210340723
Short name T476
Test name
Test status
Simulation time 299451483 ps
CPU time 3.48 seconds
Started Oct 18 01:30:57 PM PDT 23
Finished Oct 18 01:31:01 PM PDT 23
Peak memory 206496 kb
Host smart-dd965134-017e-4797-8ba2-7a4756b32cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96245470967612024734801544533971051701307712830326831285239394786924210340723 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.96245470967612024734801544533971051701307712830326831285239394786924210340723
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.29021440645183904063702772770677824588074693392660984198626287915434154105642
Short name T181
Test name
Test status
Simulation time 86880545330 ps
CPU time 1087.65 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:47:57 PM PDT 23
Peak memory 218644 kb
Host smart-bf49c7e0-ebc3-4b56-a4ae-cb666220f6b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290214406451839040637027727
70677824588074693392660984198626287915434154105642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.29021440645
183904063702772770677824588074693392660984198626287915434154105642
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert.52953214812075897402227331558975907185409614813697353847419767161177979857444
Short name T50
Test name
Test status
Simulation time 32330757 ps
CPU time 0.99 seconds
Started Oct 18 01:29:51 PM PDT 23
Finished Oct 18 01:29:53 PM PDT 23
Peak memory 206016 kb
Host smart-d12eb081-7b48-4236-ae69-7a721b388916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52953214812075897402227331558975907185409614813697353847419767161177979857444 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.edn_alert.52953214812075897402227331558975907185409614813697353847419767161177979857444
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.87940749153305697548384860741935071435054861661651842213705826298703902498694
Short name T423
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 205968 kb
Host smart-647020b4-f0dd-4eff-9312-ff511161dc50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87940749153305697548384860741935071435054861661651842213705826298703902498694 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_alert_test.87940749153305697548384860741935071435054861661651842213705826298703902498694
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.76655435431092402882454998669741773989952467708719995806043411008558700916735
Short name T425
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 215092 kb
Host smart-c4334df0-d182-4a0f-a5a5-fb7608f76765
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76655435431092402882454998669741773989952467708719995806043411008558700916735 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.edn_disable.76655435431092402882454998669741773989952467708719995806043411008558700916735
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.22943098325027695076132196713103241748622087877043764397494464257388625467575
Short name T588
Test name
Test status
Simulation time 30622451 ps
CPU time 0.96 seconds
Started Oct 18 01:29:46 PM PDT 23
Finished Oct 18 01:29:47 PM PDT 23
Peak memory 215264 kb
Host smart-ab53dcb4-6b3e-4d82-ad9e-28539415b588
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22943098325027695076132196713103241748622087877043764397494464257388625467575 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.2294309832502769507613219671310324174862208787704376439749
4464257388625467575
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.86565616349101524870412080562491596190772145712333151857740393093400416985149
Short name T188
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:32 PM PDT 23
Peak memory 215196 kb
Host smart-75896e1f-38fa-4594-92e8-c7f86720bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86565616349101524870412080562491596190772145712333151857740393093400416985149 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.edn_err.86565616349101524870412080562491596190772145712333151857740393093400416985149
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.75688490950116036330004499434009759549078888406980513388415053462753186594591
Short name T705
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:30:12 PM PDT 23
Finished Oct 18 01:30:13 PM PDT 23
Peak memory 205768 kb
Host smart-eb81ecf0-5663-4b8c-81ce-3fa7049a7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75688490950116036330004499434009759549078888406980513388415053462753186594591 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.edn_genbits.75688490950116036330004499434009759549078888406980513388415053462753186594591
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.86824075596109349439429969017321450156253202010222798045344973017331320341794
Short name T21
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:30:47 PM PDT 23
Finished Oct 18 01:30:49 PM PDT 23
Peak memory 222804 kb
Host smart-10a5265d-819d-4406-9e1e-e8d0f8b181cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86824075596109349439429969017321450156253202010222798045344973017331320341794 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.edn_intr.86824075596109349439429969017321450156253202010222798045344973017331320341794
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.7839058054539786675738820718382689942886095189763345185460856545380026605619
Short name T370
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:32 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 205608 kb
Host smart-83925819-667c-4cfb-87f0-e90258e28085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7839058054539786675738820718382689942886095189763345185460856545380026605619 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.edn_smoke.7839058054539786675738820718382689942886095189763345185460856545380026605619
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.94566047897982838362468304563554008804044418896184386574523939799031492530766
Short name T73
Test name
Test status
Simulation time 299451483 ps
CPU time 3.73 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:40 PM PDT 23
Peak memory 206608 kb
Host smart-bbc27153-f219-43b5-bdc0-191535ad9956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94566047897982838362468304563554008804044418896184386574523939799031492530766 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.94566047897982838362468304563554008804044418896184386574523939799031492530766
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.84727305910581860698437485121627216717329111674551876789772946107789447957892
Short name T463
Test name
Test status
Simulation time 86880545330 ps
CPU time 1095.02 seconds
Started Oct 18 01:30:33 PM PDT 23
Finished Oct 18 01:48:48 PM PDT 23
Peak memory 218572 kb
Host smart-97587017-a7ca-4e4e-8840-3c6f2d62914a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847273059105818606984374851
21627216717329111674551876789772946107789447957892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.84727305910
581860698437485121627216717329111674551876789772946107789447957892
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert.35664450616874875453502777097675706863899678951202582324144207296147224443629
Short name T535
Test name
Test status
Simulation time 32330757 ps
CPU time 0.99 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:29:45 PM PDT 23
Peak memory 206008 kb
Host smart-80612f36-145a-40ad-9347-9a40ad25cb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35664450616874875453502777097675706863899678951202582324144207296147224443629 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.edn_alert.35664450616874875453502777097675706863899678951202582324144207296147224443629
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.100027777699549585598266731550516835207902526114469923016941430875716273914678
Short name T140
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:29:42 PM PDT 23
Finished Oct 18 01:29:44 PM PDT 23
Peak memory 205972 kb
Host smart-4a027e3f-6ce6-4d74-a528-c6aa2c5ab83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100027777699549585598266731550516835207902526114469923016941430875716273914678 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.edn_alert_test.100027777699549585598266731550516835207902526114469923016941430875716273914678
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.21378589033263136537051473303517448539499629020470987408571283400200179955374
Short name T591
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 215044 kb
Host smart-de35d75b-9988-4e58-a484-08dc17af899f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21378589033263136537051473303517448539499629020470987408571283400200179955374 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.edn_disable.21378589033263136537051473303517448539499629020470987408571283400200179955374
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.96541937925973359886600396674826505005508545921074555957565697636415553602031
Short name T60
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:15 PM PDT 23
Peak memory 215284 kb
Host smart-9fcf4adc-49d7-43a0-b4a4-15bd86c49197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96541937925973359886600396674826505005508545921074555957565697636415553602031 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.9654193792597335988660039667482650500550854592107455595756
5697636415553602031
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.97382120367000372033953500286930358250522257100907962079393918263381672550404
Short name T723
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 215260 kb
Host smart-4cecfa2e-f964-4ddb-924d-f8293e3bc486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97382120367000372033953500286930358250522257100907962079393918263381672550404 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.edn_err.97382120367000372033953500286930358250522257100907962079393918263381672550404
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.83072783747080146057773117631026586170537477756067706871895053648972258479543
Short name T392
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:30:12 PM PDT 23
Finished Oct 18 01:30:14 PM PDT 23
Peak memory 205760 kb
Host smart-a7acda07-5b52-4d97-8703-d3b532cbb3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83072783747080146057773117631026586170537477756067706871895053648972258479543 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.edn_genbits.83072783747080146057773117631026586170537477756067706871895053648972258479543
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.80729442185255198933719974169403596343748554368603400143748893393015842741864
Short name T380
Test name
Test status
Simulation time 22372583 ps
CPU time 0.98 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 222920 kb
Host smart-41c0acd1-dc68-49ab-b6e3-7ab9b28b900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80729442185255198933719974169403596343748554368603400143748893393015842741864 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.edn_intr.80729442185255198933719974169403596343748554368603400143748893393015842741864
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.18339446060480022090628223460952959942932842377233381864076073235980125453712
Short name T649
Test name
Test status
Simulation time 21768426 ps
CPU time 0.82 seconds
Started Oct 18 01:30:08 PM PDT 23
Finished Oct 18 01:30:09 PM PDT 23
Peak memory 205668 kb
Host smart-1b4230e2-3879-4669-a0dc-40ae37938e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18339446060480022090628223460952959942932842377233381864076073235980125453712 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.edn_smoke.18339446060480022090628223460952959942932842377233381864076073235980125453712
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.68322189591221802183550161092855577284151965790942342917408178765647769902393
Short name T455
Test name
Test status
Simulation time 299451483 ps
CPU time 3.61 seconds
Started Oct 18 01:30:57 PM PDT 23
Finished Oct 18 01:31:01 PM PDT 23
Peak memory 206492 kb
Host smart-ddd7e06f-af96-42c8-9dae-7088da143ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68322189591221802183550161092855577284151965790942342917408178765647769902393 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.68322189591221802183550161092855577284151965790942342917408178765647769902393
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_alert.30689345726783389431770551922260099640187508146023058853471190789936858263802
Short name T585
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:30:10 PM PDT 23
Finished Oct 18 01:30:11 PM PDT 23
Peak memory 205952 kb
Host smart-d9d55586-5846-41bb-a47a-d70330a94142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30689345726783389431770551922260099640187508146023058853471190789936858263802 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_alert.30689345726783389431770551922260099640187508146023058853471190789936858263802
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.85334549018816713808490873767580307656807798991795557773506512107614541520645
Short name T347
Test name
Test status
Simulation time 16111390 ps
CPU time 0.95 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 205988 kb
Host smart-9ea130f7-cd3f-49de-9d9d-c254ff7d2dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85334549018816713808490873767580307656807798991795557773506512107614541520645 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_alert_test.85334549018816713808490873767580307656807798991795557773506512107614541520645
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.64388777828022364843796400521812645136246619680061572113360061509012894062161
Short name T453
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 215052 kb
Host smart-e10b7a37-ffc7-49ac-b42a-ced2caf0a1ad
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64388777828022364843796400521812645136246619680061572113360061509012894062161 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.edn_disable.64388777828022364843796400521812645136246619680061572113360061509012894062161
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.87500127203682938245252952656290375252194772880413178076943914894261968325287
Short name T616
Test name
Test status
Simulation time 30622451 ps
CPU time 0.9 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 215260 kb
Host smart-64c95ec2-f650-4cbf-bf2d-d2ca4543f62c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87500127203682938245252952656290375252194772880413178076943914894261968325287 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.8750012720368293824525295265629037525219477288041317807694
3914894261968325287
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.33441278975906970014323508949702030782514170062839948190069725683939605957664
Short name T449
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:43 PM PDT 23
Peak memory 215264 kb
Host smart-87e13fd2-ea39-491a-9241-de701e56a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33441278975906970014323508949702030782514170062839948190069725683939605957664 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.edn_err.33441278975906970014323508949702030782514170062839948190069725683939605957664
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.9656208192799211654203788624490993950203836878795479112610366854127373600850
Short name T129
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:29:46 PM PDT 23
Finished Oct 18 01:29:47 PM PDT 23
Peak memory 205768 kb
Host smart-d3169d9b-5ac3-4e6d-a867-9ea3e598c8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9656208192799211654203788624490993950203836878795479112610366854127373600850 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.edn_genbits.9656208192799211654203788624490993950203836878795479112610366854127373600850
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.16663289281734974668051738011883637839694641239861478362596482299397122252232
Short name T409
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 222924 kb
Host smart-6ec89af2-39b4-4969-868c-dd08cfa0d158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16663289281734974668051738011883637839694641239861478362596482299397122252232 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.edn_intr.16663289281734974668051738011883637839694641239861478362596482299397122252232
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.98933376618044020620308720125683948562616594814246190527833739555521288663269
Short name T620
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:07 PM PDT 23
Finished Oct 18 01:30:08 PM PDT 23
Peak memory 205704 kb
Host smart-9665335f-592c-4619-9a3f-4b87eeac0a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98933376618044020620308720125683948562616594814246190527833739555521288663269 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_smoke.98933376618044020620308720125683948562616594814246190527833739555521288663269
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.85242520958398100099460797412954208904276384379430933971930246574115762999015
Short name T511
Test name
Test status
Simulation time 299451483 ps
CPU time 3.6 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 206480 kb
Host smart-83619eae-5b3c-428b-8733-015fc117f493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85242520958398100099460797412954208904276384379430933971930246574115762999015 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.85242520958398100099460797412954208904276384379430933971930246574115762999015
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.115702824650980726371570761736397536991648733984968160438154044236730866575249
Short name T190
Test name
Test status
Simulation time 86880545330 ps
CPU time 1151.04 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:49:49 PM PDT 23
Peak memory 218628 kb
Host smart-b10fee27-20d9-41e6-befe-5eeabac59dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115702824650980726371570761
736397536991648733984968160438154044236730866575249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1157028246
50980726371570761736397536991648733984968160438154044236730866575249
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.80313539429168842145080965969752697276911683163790457359527117383153951648409
Short name T565
Test name
Test status
Simulation time 32330757 ps
CPU time 0.97 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 205980 kb
Host smart-e925d610-eb69-42f4-8c40-1c75d9d75570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80313539429168842145080965969752697276911683163790457359527117383153951648409 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_alert.80313539429168842145080965969752697276911683163790457359527117383153951648409
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.11528297251753727388348483330325198575385849818943094244841438416207544344264
Short name T124
Test name
Test status
Simulation time 16111390 ps
CPU time 0.97 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:31:00 PM PDT 23
Peak memory 205940 kb
Host smart-882a47a0-f6e6-42a8-be6e-1295f37226b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528297251753727388348483330325198575385849818943094244841438416207544344264 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_alert_test.11528297251753727388348483330325198575385849818943094244841438416207544344264
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.29027893040986936256566111806954639029187434285760816907558185668763812452982
Short name T457
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:26 PM PDT 23
Peak memory 215140 kb
Host smart-f7a0dcaf-ffdf-45dc-b146-14b327eac327
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29027893040986936256566111806954639029187434285760816907558185668763812452982 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.edn_disable.29027893040986936256566111806954639029187434285760816907558185668763812452982
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.8780422890639526039688142752214656504490501331995961050591672472872626677894
Short name T360
Test name
Test status
Simulation time 30622451 ps
CPU time 0.98 seconds
Started Oct 18 01:30:40 PM PDT 23
Finished Oct 18 01:30:41 PM PDT 23
Peak memory 215268 kb
Host smart-ad395d7f-ad24-4349-bbc8-411514885a98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8780422890639526039688142752214656504490501331995961050591672472872626677894 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.87804228906395260396881427522146565044905013319959610505916
72472872626677894
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.32559231610909933494270766495497806250029021986092606623175111415318345715916
Short name T688
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:45 PM PDT 23
Peak memory 215292 kb
Host smart-b9de20ff-f9bf-4e5f-971b-213ed409afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32559231610909933494270766495497806250029021986092606623175111415318345715916 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.edn_err.32559231610909933494270766495497806250029021986092606623175111415318345715916
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.60503467290115256747352153755960167050267892683538080719238252640619094696706
Short name T163
Test name
Test status
Simulation time 22643412 ps
CPU time 0.99 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 205692 kb
Host smart-af3e16bf-a887-4618-a80b-f1ab35624188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60503467290115256747352153755960167050267892683538080719238252640619094696706 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.edn_genbits.60503467290115256747352153755960167050267892683538080719238252640619094696706
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.57586986855177222512320537871747693429585585823640432619536277980082976719203
Short name T150
Test name
Test status
Simulation time 22372583 ps
CPU time 1.03 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 222940 kb
Host smart-5046ddeb-2ce7-45d9-8dc4-3a6e14a3c0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57586986855177222512320537871747693429585585823640432619536277980082976719203 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.edn_intr.57586986855177222512320537871747693429585585823640432619536277980082976719203
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.15015406727609817547147692765373685630803496839884041938323394455796375284400
Short name T478
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 205612 kb
Host smart-a9dcdf34-f843-4f6f-83a1-ab2adcd65f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15015406727609817547147692765373685630803496839884041938323394455796375284400 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_smoke.15015406727609817547147692765373685630803496839884041938323394455796375284400
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.54205494106377361564500110862769870556620382755718331457614252168526566069076
Short name T543
Test name
Test status
Simulation time 299451483 ps
CPU time 3.61 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 206504 kb
Host smart-4fa8accd-4107-4fdc-8afb-0ec937171fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54205494106377361564500110862769870556620382755718331457614252168526566069076 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.54205494106377361564500110862769870556620382755718331457614252168526566069076
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.6899148819342415718309200695439575054015695535661572676036203869061818452215
Short name T377
Test name
Test status
Simulation time 86880545330 ps
CPU time 1097.94 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:48:54 PM PDT 23
Peak memory 218648 kb
Host smart-fdd9b7dc-2d10-49c6-bd7a-6a8bc61d3b33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689914881934241571830920069
5439575054015695535661572676036203869061818452215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.689914881934
2415718309200695439575054015695535661572676036203869061818452215
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert.22035036586576531608342959044202693214235632824923679203903226707138916239749
Short name T435
Test name
Test status
Simulation time 32330757 ps
CPU time 0.97 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:44 PM PDT 23
Peak memory 205936 kb
Host smart-d0a2be47-732d-4fac-b5e3-df743eeef779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22035036586576531608342959044202693214235632824923679203903226707138916239749 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_alert.22035036586576531608342959044202693214235632824923679203903226707138916239749
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.47028991802046689279795095045541375030610214597194086250009559281097626833707
Short name T576
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:30:45 PM PDT 23
Finished Oct 18 01:30:46 PM PDT 23
Peak memory 205980 kb
Host smart-2cf916ab-ffad-4409-ab91-7d4bc2712d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47028991802046689279795095045541375030610214597194086250009559281097626833707 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_alert_test.47028991802046689279795095045541375030610214597194086250009559281097626833707
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.99459884411985635530420141252978905817453964442918235393052696081152791994468
Short name T62
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 215088 kb
Host smart-58d2c2a6-4faf-48db-ae8c-9a014db0d0d9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99459884411985635530420141252978905817453964442918235393052696081152791994468 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_disable.99459884411985635530420141252978905817453964442918235393052696081152791994468
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.63797563277220497843380919695195536144682636314821190871522792552829190471230
Short name T582
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:22 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 215228 kb
Host smart-b1ec3932-d331-48b5-aa0d-d4f478e4fa34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63797563277220497843380919695195536144682636314821190871522792552829190471230 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.63797563277220497843380919695195536144682636314821190871522
792552829190471230
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.91805264405169855710447432490048621027130793707376090167608044120449069060024
Short name T437
Test name
Test status
Simulation time 29871889 ps
CPU time 0.98 seconds
Started Oct 18 01:30:34 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 215420 kb
Host smart-1ed40d64-6b66-4bff-b2b2-e33af1cd5b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91805264405169855710447432490048621027130793707376090167608044120449069060024 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
edn_err.91805264405169855710447432490048621027130793707376090167608044120449069060024
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.101485824350143822909778729032316328034214618323158332936978037222259562503486
Short name T125
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205800 kb
Host smart-61832a03-1b1e-4bf7-8e30-6afe78aabc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101485824350143822909778729032316328034214618323158332936978037222259562503486 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.edn_genbits.101485824350143822909778729032316328034214618323158332936978037222259562503486
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.14775721372700256890599981031477382530232935698151616878845235082027043209996
Short name T721
Test name
Test status
Simulation time 22372583 ps
CPU time 1.03 seconds
Started Oct 18 01:30:45 PM PDT 23
Finished Oct 18 01:30:46 PM PDT 23
Peak memory 222900 kb
Host smart-c49fce39-2f5c-490f-8c13-bec222961486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14775721372700256890599981031477382530232935698151616878845235082027043209996 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.edn_intr.14775721372700256890599981031477382530232935698151616878845235082027043209996
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.68503895569337736433034709226176434521811147438207156957879155710712303852671
Short name T513
Test name
Test status
Simulation time 19018470 ps
CPU time 0.87 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 205612 kb
Host smart-eb940541-d325-4aa5-ae81-f9c63354c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68503895569337736433034709226176434521811147438207156957879155710712303852671 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.edn_regwen.68503895569337736433034709226176434521811147438207156957879155710712303852671
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.89398349696875864440029512813738696682425951616115298469099269222288723209437
Short name T74
Test name
Test status
Simulation time 21768426 ps
CPU time 0.9 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:36 PM PDT 23
Peak memory 205796 kb
Host smart-96e8350b-e92d-46bb-b98e-f1fa736be957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89398349696875864440029512813738696682425951616115298469099269222288723209437 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_smoke.89398349696875864440029512813738696682425951616115298469099269222288723209437
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.79225177892429585778687248541005838231870314770221049878041556184939664655960
Short name T44
Test name
Test status
Simulation time 299451483 ps
CPU time 3.68 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 206420 kb
Host smart-f018c5da-e493-499f-a2f8-54992c39ddbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79225177892429585778687248541005838231870314770221049878041556184939664655960 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.79225177892429585778687248541005838231870314770221049878041556184939664655960
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.54370256515068768730813260762142017119204048145941502546787955027885999881814
Short name T391
Test name
Test status
Simulation time 86880545330 ps
CPU time 1101 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:48:47 PM PDT 23
Peak memory 218576 kb
Host smart-9f25259a-f5e9-4c41-b719-996a39fd9f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543702565150687687308132607
62142017119204048145941502546787955027885999881814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.543702565150
68768730813260762142017119204048145941502546787955027885999881814
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.114225028915930904074087372631273107655792313087804210255847919026625876339385
Short name T345
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 205932 kb
Host smart-b6c87c04-8410-45c9-af21-841aaf650451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114225028915930904074087372631273107655792313087804210255847919026625876339385 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.edn_alert.114225028915930904074087372631273107655792313087804210255847919026625876339385
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.28072930659077280057888081617544196155596797330600591273138377422955873237495
Short name T114
Test name
Test status
Simulation time 16111390 ps
CPU time 0.92 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:36 PM PDT 23
Peak memory 205880 kb
Host smart-50ab178a-353b-4141-9da9-4cc1a1727ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072930659077280057888081617544196155596797330600591273138377422955873237495 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_alert_test.28072930659077280057888081617544196155596797330600591273138377422955873237495
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.15634897630261895660217163477309727662415077236838893101671095235490809370238
Short name T639
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 215080 kb
Host smart-d2999407-2868-4d3c-a547-0b647b48bc0a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15634897630261895660217163477309727662415077236838893101671095235490809370238 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.edn_disable.15634897630261895660217163477309727662415077236838893101671095235490809370238
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.114306962172859603889141567474947745134187181636817168459188652630178351586458
Short name T661
Test name
Test status
Simulation time 30622451 ps
CPU time 0.9 seconds
Started Oct 18 01:30:23 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 215216 kb
Host smart-03da3440-fbbc-4c71-9d64-4b89385642be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114306962172859603889141567474947745134187181636817168459188652630178351586458 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.114306962172859603889141567474947745134187181636817168459
188652630178351586458
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.99648642832337519085163351452233507710242299641007484146382765989910725341923
Short name T42
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:29:53 PM PDT 23
Finished Oct 18 01:29:54 PM PDT 23
Peak memory 205740 kb
Host smart-3dd82bb8-760f-4f20-9734-42b4d5e21915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99648642832337519085163351452233507710242299641007484146382765989910725341923 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.edn_genbits.99648642832337519085163351452233507710242299641007484146382765989910725341923
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.85327302910376901885946115801631605428401839300100554727095159888660290666943
Short name T367
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:31:00 PM PDT 23
Peak memory 222940 kb
Host smart-968d1e1c-80d3-4714-9991-bbce6e10b7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85327302910376901885946115801631605428401839300100554727095159888660290666943 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.edn_intr.85327302910376901885946115801631605428401839300100554727095159888660290666943
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.76476949389749143510681698686695530680630500141112762533541757539109335563081
Short name T633
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 205600 kb
Host smart-b5d86a39-b752-4cd8-b896-9297761fb43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76476949389749143510681698686695530680630500141112762533541757539109335563081 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.edn_smoke.76476949389749143510681698686695530680630500141112762533541757539109335563081
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.108683056676404750289469255942890237515075013006747545310459704139403571355910
Short name T662
Test name
Test status
Simulation time 299451483 ps
CPU time 3.6 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:41 PM PDT 23
Peak memory 206536 kb
Host smart-8537cd04-198c-465c-8545-2b1a94cb91fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108683056676404750289469255942890237515075013006747545310459704139403571355910 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.108683056676404750289469255942890237515075013006747545310459704139403571355910
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.92972716970285251491927139501034825948232786311574903212631579184324232200755
Short name T3
Test name
Test status
Simulation time 86880545330 ps
CPU time 1114.17 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:49:10 PM PDT 23
Peak memory 218628 kb
Host smart-3b7b7544-e128-4929-a8c2-a1f60b3cc824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929727169702852514919271395
01034825948232786311574903212631579184324232200755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.92972716970
285251491927139501034825948232786311574903212631579184324232200755
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert.72003027090025648358126103974062065999378576518483927212389092067581133679927
Short name T149
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:57 PM PDT 23
Peak memory 205892 kb
Host smart-5712c723-b8ca-4389-9bfe-69b1f59e8c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72003027090025648358126103974062065999378576518483927212389092067581133679927 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_alert.72003027090025648358126103974062065999378576518483927212389092067581133679927
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.74014399141885351301844040367246770014501149573933638964407771549629448124704
Short name T598
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:31:32 PM PDT 23
Finished Oct 18 01:31:33 PM PDT 23
Peak memory 205920 kb
Host smart-3a93ed1c-f9f4-4b72-b939-061f4df162bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74014399141885351301844040367246770014501149573933638964407771549629448124704 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_alert_test.74014399141885351301844040367246770014501149573933638964407771549629448124704
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.48536508779959292777315865951163371032309923962854063825264053394340119082659
Short name T66
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 215052 kb
Host smart-a3aa7605-9448-4859-b83b-55bad0524d82
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48536508779959292777315865951163371032309923962854063825264053394340119082659 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.edn_disable.48536508779959292777315865951163371032309923962854063825264053394340119082659
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.21772058720270611265355721370584384450058770430888443411271268535252987406384
Short name T720
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 215196 kb
Host smart-34b0e23d-ca55-46d0-88ad-e9fb0f49f9f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21772058720270611265355721370584384450058770430888443411271268535252987406384 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.2177205872027061126535572137058438445005877043088844341127
1268535252987406384
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.109037360029485967918587711418565210324763620125662117568257423659369960242165
Short name T371
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:05 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 215260 kb
Host smart-1574de25-154a-4255-9d14-f42d488f2811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109037360029485967918587711418565210324763620125662117568257423659369960242165 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.edn_err.109037360029485967918587711418565210324763620125662117568257423659369960242165
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.61236585241999206307752551697375701115656983234141836911603083655411389823073
Short name T151
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:57 PM PDT 23
Peak memory 205632 kb
Host smart-95eb8161-3abf-43da-bdc6-7dd6b9cb9610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61236585241999206307752551697375701115656983234141836911603083655411389823073 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.edn_genbits.61236585241999206307752551697375701115656983234141836911603083655411389823073
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.92159448870991075184565882082847326136639618701768570343949961809194498702946
Short name T458
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:57 PM PDT 23
Peak memory 222896 kb
Host smart-deaae25f-a534-47fc-9fbc-702288f69301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92159448870991075184565882082847326136639618701768570343949961809194498702946 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.edn_intr.92159448870991075184565882082847326136639618701768570343949961809194498702946
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.42247516344944729549000353364269378255534050106431087788290447875465306631727
Short name T48
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:31:26 PM PDT 23
Finished Oct 18 01:31:27 PM PDT 23
Peak memory 205700 kb
Host smart-ada29e8d-5669-4997-a86b-716134748f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42247516344944729549000353364269378255534050106431087788290447875465306631727 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_smoke.42247516344944729549000353364269378255534050106431087788290447875465306631727
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.86331483858673254169891654372537243731995971580683753474903057202622718639305
Short name T396
Test name
Test status
Simulation time 299451483 ps
CPU time 3.72 seconds
Started Oct 18 01:30:57 PM PDT 23
Finished Oct 18 01:31:01 PM PDT 23
Peak memory 206484 kb
Host smart-1ced5989-4c58-4062-89f0-acf262c6aee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86331483858673254169891654372537243731995971580683753474903057202622718639305 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.86331483858673254169891654372537243731995971580683753474903057202622718639305
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.33488847318168479659078843842734025282905848281979817842633293269159760764123
Short name T462
Test name
Test status
Simulation time 86880545330 ps
CPU time 1084.47 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:49:06 PM PDT 23
Peak memory 218592 kb
Host smart-d20862b8-b352-45b8-a8b9-6c544b320c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334888473181684796590788438
42734025282905848281979817842633293269159760764123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.33488847318
168479659078843842734025282905848281979817842633293269159760764123
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.61122259431305754335181504748588054836167307009605862827363538157491069625722
Short name T573
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:30:10 PM PDT 23
Finished Oct 18 01:30:11 PM PDT 23
Peak memory 206032 kb
Host smart-9b04ecb0-465a-4396-ab35-29aadafaf717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61122259431305754335181504748588054836167307009605862827363538157491069625722 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_alert.61122259431305754335181504748588054836167307009605862827363538157491069625722
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.72462507476257232308552536122012844430493667956668974494816081072715566583383
Short name T422
Test name
Test status
Simulation time 16111390 ps
CPU time 0.93 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:32 PM PDT 23
Peak memory 205932 kb
Host smart-2b1770af-cd74-49be-81c8-e6a0d645c7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72462507476257232308552536122012844430493667956668974494816081072715566583383 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_alert_test.72462507476257232308552536122012844430493667956668974494816081072715566583383
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.64215523706055398101703417026353668465811462251497591312396581853879450470263
Short name T703
Test name
Test status
Simulation time 19976788 ps
CPU time 0.81 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:18 PM PDT 23
Peak memory 215016 kb
Host smart-7e8bc6c3-c824-4a00-a9db-870aac61625a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64215523706055398101703417026353668465811462251497591312396581853879450470263 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.edn_disable.64215523706055398101703417026353668465811462251497591312396581853879450470263
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.8691761376520813985364019505981821731176460044325009447187728180531620410271
Short name T687
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 215208 kb
Host smart-07ca3d14-9968-4a32-ac57-62f9286e1f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8691761376520813985364019505981821731176460044325009447187728180531620410271 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
edn_err.8691761376520813985364019505981821731176460044325009447187728180531620410271
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.89590038655421118361033623891781980920563529039220399351325059840717236987022
Short name T375
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:30:45 PM PDT 23
Finished Oct 18 01:30:47 PM PDT 23
Peak memory 205732 kb
Host smart-9d982cab-649f-4c0a-b8b8-d78097a67028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89590038655421118361033623891781980920563529039220399351325059840717236987022 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.edn_genbits.89590038655421118361033623891781980920563529039220399351325059840717236987022
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.110368070316296583828783098276617256891031970608369621006931785365166819397855
Short name T16
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:31:01 PM PDT 23
Peak memory 222904 kb
Host smart-8368d389-2997-40d2-ae62-2847cc15b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110368070316296583828783098276617256891031970608369621006931785365166819397855 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.edn_intr.110368070316296583828783098276617256891031970608369621006931785365166819397855
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.31266012859263716054161804026386904121083581369086019819863904848934095671023
Short name T171
Test name
Test status
Simulation time 21768426 ps
CPU time 1 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:31:15 PM PDT 23
Peak memory 205696 kb
Host smart-cb07c850-ba52-4c92-a083-06f3fb2298d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31266012859263716054161804026386904121083581369086019819863904848934095671023 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_smoke.31266012859263716054161804026386904121083581369086019819863904848934095671023
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.47613365458402173339892418755941215395565673704698632528107540305939516507101
Short name T586
Test name
Test status
Simulation time 299451483 ps
CPU time 3.61 seconds
Started Oct 18 01:31:00 PM PDT 23
Finished Oct 18 01:31:04 PM PDT 23
Peak memory 206504 kb
Host smart-a1206066-c704-484d-8593-d1010ab7ee79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47613365458402173339892418755941215395565673704698632528107540305939516507101 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.47613365458402173339892418755941215395565673704698632528107540305939516507101
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.95597353982417333041318388795430024689701469902779681449706469380155287786228
Short name T7
Test name
Test status
Simulation time 86880545330 ps
CPU time 1134.24 seconds
Started Oct 18 01:30:10 PM PDT 23
Finished Oct 18 01:49:05 PM PDT 23
Peak memory 218660 kb
Host smart-3adc8338-3f79-49c2-9881-96901232cd11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955973539824173330413183887
95430024689701469902779681449706469380155287786228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.95597353982
417333041318388795430024689701469902779681449706469380155287786228
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.19110609184572036445331305151299555760647865328683736702973707987572433890403
Short name T176
Test name
Test status
Simulation time 32330757 ps
CPU time 0.99 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 205924 kb
Host smart-cc70f33d-56ba-46df-8b60-fef431581169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19110609184572036445331305151299555760647865328683736702973707987572433890403 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_alert.19110609184572036445331305151299555760647865328683736702973707987572433890403
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.102071298958395204255660630017316823846353158944987589986244691517222503041993
Short name T506
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:30:54 PM PDT 23
Finished Oct 18 01:30:55 PM PDT 23
Peak memory 205992 kb
Host smart-35581ffc-68db-4434-bd82-bc8d9bf5a684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102071298958395204255660630017316823846353158944987589986244691517222503041993 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.edn_alert_test.102071298958395204255660630017316823846353158944987589986244691517222503041993
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.8224268841701886857238203732844827669241200033696713656182888628944745953951
Short name T348
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:23 PM PDT 23
Finished Oct 18 01:30:25 PM PDT 23
Peak memory 215116 kb
Host smart-12a11dc6-71f2-4dfa-b9ba-e792f1929ace
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8224268841701886857238203732844827669241200033696713656182888628944745953951 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_disable.8224268841701886857238203732844827669241200033696713656182888628944745953951
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.54210013337620339672473945139365835469699563115106465241098223746728301439162
Short name T55
Test name
Test status
Simulation time 30622451 ps
CPU time 0.93 seconds
Started Oct 18 01:30:23 PM PDT 23
Finished Oct 18 01:30:25 PM PDT 23
Peak memory 215332 kb
Host smart-0b923ec8-c52c-4922-b640-04cafbdbe3e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54210013337620339672473945139365835469699563115106465241098223746728301439162 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.5421001333762033967247394513936583546969956311510646524109
8223746728301439162
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.47363242267812432658928707302189584602400083691593183073113776007054037208246
Short name T446
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:30:22 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 215264 kb
Host smart-faec7970-0b85-4d94-864d-b71375c4aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47363242267812432658928707302189584602400083691593183073113776007054037208246 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.edn_err.47363242267812432658928707302189584602400083691593183073113776007054037208246
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.53926678564941025127597754683269927759445408607739613126270481665692549254191
Short name T131
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:30:13 PM PDT 23
Finished Oct 18 01:30:14 PM PDT 23
Peak memory 205820 kb
Host smart-3706a43d-0bc0-45c3-a396-775dfd1f09e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53926678564941025127597754683269927759445408607739613126270481665692549254191 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.edn_genbits.53926678564941025127597754683269927759445408607739613126270481665692549254191
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.36932796745722170367610976847298646598338835587433580830784346610785030437114
Short name T11
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 222968 kb
Host smart-f6679a82-785b-4a3f-b807-9c8d61a218d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36932796745722170367610976847298646598338835587433580830784346610785030437114 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.edn_intr.36932796745722170367610976847298646598338835587433580830784346610785030437114
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.62006597722547097029530488197311327598209793067669985148609768498510321498613
Short name T501
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205692 kb
Host smart-2806002d-2350-40e4-a06d-a233630df023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62006597722547097029530488197311327598209793067669985148609768498510321498613 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_smoke.62006597722547097029530488197311327598209793067669985148609768498510321498613
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.41595402109999199495504828264906009529262077908540979259052726399483901696882
Short name T682
Test name
Test status
Simulation time 299451483 ps
CPU time 3.73 seconds
Started Oct 18 01:30:07 PM PDT 23
Finished Oct 18 01:30:11 PM PDT 23
Peak memory 206480 kb
Host smart-53e2c828-2bd4-4370-8504-624befb08570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41595402109999199495504828264906009529262077908540979259052726399483901696882 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.41595402109999199495504828264906009529262077908540979259052726399483901696882
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.51965236053914437546833753891245499499279401702993939664609665665746159588186
Short name T6
Test name
Test status
Simulation time 86880545330 ps
CPU time 1113.25 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:48:53 PM PDT 23
Peak memory 218628 kb
Host smart-44123f6b-3a35-40f1-81c8-69c9e0097393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519652360539144375468337538
91245499499279401702993939664609665665746159588186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.51965236053
914437546833753891245499499279401702993939664609665665746159588186
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.71343255442618592061339435556526826411290625647306860136103697596495386806586
Short name T621
Test name
Test status
Simulation time 32330757 ps
CPU time 0.98 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 205972 kb
Host smart-daac30f5-719a-4b49-aff8-3d55e28abdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71343255442618592061339435556526826411290625647306860136103697596495386806586 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.edn_alert.71343255442618592061339435556526826411290625647306860136103697596495386806586
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.68149737435563605094231662412581628029741868468567370994574956367076120344100
Short name T17
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 205912 kb
Host smart-60782a4b-a490-4664-ada9-835ce250459a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68149737435563605094231662412581628029741868468567370994574956367076120344100 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_alert_test.68149737435563605094231662412581628029741868468567370994574956367076120344100
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.112203488697672034441847564933401787960609706586377737465176371555612709729848
Short name T70
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:24 PM PDT 23
Finished Oct 18 01:30:26 PM PDT 23
Peak memory 214972 kb
Host smart-4532acc3-ff1b-4cdd-8eed-b2b5da177a14
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112203488697672034441847564933401787960609706586377737465176371555612709729848 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 24.edn_disable.112203488697672034441847564933401787960609706586377737465176371555612709729848
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.11292039768452269561457828868295283063852401574313574226465130228866059572001
Short name T617
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:38 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 215400 kb
Host smart-e6892511-370c-4e47-a75a-46d9a86bf71f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292039768452269561457828868295283063852401574313574226465130228866059572001 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.1129203976845226956145782886829528306385240157431357422646
5130228866059572001
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.97387049787935296712715026033863877161802454010863527175559205523562209120441
Short name T549
Test name
Test status
Simulation time 29871889 ps
CPU time 0.93 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 215316 kb
Host smart-c1b105fe-5370-4983-9a2e-1d0c1c4d943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97387049787935296712715026033863877161802454010863527175559205523562209120441 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.edn_err.97387049787935296712715026033863877161802454010863527175559205523562209120441
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.34561389009011727043330064272483762610919704839045729620769656076489676582927
Short name T553
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:32 PM PDT 23
Peak memory 205768 kb
Host smart-f3e11c95-1a4e-4fd1-97b0-bbdcdd5c077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34561389009011727043330064272483762610919704839045729620769656076489676582927 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.edn_genbits.34561389009011727043330064272483762610919704839045729620769656076489676582927
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.67590674604530973407023046735973067854568509353144310568778906281389802185152
Short name T607
Test name
Test status
Simulation time 22372583 ps
CPU time 1.09 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 222900 kb
Host smart-d930ef97-4166-4715-ad1f-968937eb0b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67590674604530973407023046735973067854568509353144310568778906281389802185152 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.edn_intr.67590674604530973407023046735973067854568509353144310568778906281389802185152
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.8274364340085986923993102974460920233601598202925132450423632601450938983971
Short name T554
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:47 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 205660 kb
Host smart-e9c14411-bb27-439c-a768-29132a52b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8274364340085986923993102974460920233601598202925132450423632601450938983971 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.edn_smoke.8274364340085986923993102974460920233601598202925132450423632601450938983971
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.107252783220208721410213590458650740710003871514659551168816389395579866893094
Short name T581
Test name
Test status
Simulation time 299451483 ps
CPU time 3.62 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 206500 kb
Host smart-98fa3439-aaff-4f33-8d15-d7bbfaeade71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107252783220208721410213590458650740710003871514659551168816389395579866893094 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.107252783220208721410213590458650740710003871514659551168816389395579866893094
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.67969994283966610891473419303119039063180414653339649745689336181016746440272
Short name T464
Test name
Test status
Simulation time 86880545330 ps
CPU time 1115.22 seconds
Started Oct 18 01:30:13 PM PDT 23
Finished Oct 18 01:48:49 PM PDT 23
Peak memory 218692 kb
Host smart-2f8a1dbb-9c6e-474d-8ca2-2794bfd6a2f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679699942839666108914734193
03119039063180414653339649745689336181016746440272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.67969994283
966610891473419303119039063180414653339649745689336181016746440272
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.84302986494457489647030055293282913033760265747457617862452557185135210772096
Short name T707
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:30:22 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 206012 kb
Host smart-800d8251-8c47-4260-aeee-06567ca1bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84302986494457489647030055293282913033760265747457617862452557185135210772096 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_alert.84302986494457489647030055293282913033760265747457617862452557185135210772096
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.8561583774477684679513779486210289244810382837568304013009603866531841553768
Short name T726
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:36 PM PDT 23
Peak memory 205944 kb
Host smart-af0119e1-e8fc-4027-97a1-fcf28c85909e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8561583774477684679513779486210289244810382837568304013009603866531841553768 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_alert_test.8561583774477684679513779486210289244810382837568304013009603866531841553768
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2264480112303573134078513143608527948279430370954233650351573423267803548602
Short name T523
Test name
Test status
Simulation time 19976788 ps
CPU time 0.81 seconds
Started Oct 18 01:30:43 PM PDT 23
Finished Oct 18 01:30:44 PM PDT 23
Peak memory 214972 kb
Host smart-a12aefe6-2b7e-4803-a185-849e2f1e069b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264480112303573134078513143608527948279430370954233650351573423267803548602 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_disable.2264480112303573134078513143608527948279430370954233650351573423267803548602
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.28649229564460265786306207790042207506769671418465667870971922620709861025897
Short name T563
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:34 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 215228 kb
Host smart-f6d056ec-4ae4-408c-93b4-81309fcc2aa7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28649229564460265786306207790042207506769671418465667870971922620709861025897 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2864922956446026578630620779004220750676967141846566787097
1922620709861025897
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.4639892303559967901057226461624993237354900646034222741819757097147395559546
Short name T440
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:36 PM PDT 23
Peak memory 215296 kb
Host smart-5b39b443-0288-487b-88ca-12d6277c1d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4639892303559967901057226461624993237354900646034222741819757097147395559546 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
edn_err.4639892303559967901057226461624993237354900646034222741819757097147395559546
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.41253339957909627077346793562188387435841001626953331273347603923374598920604
Short name T154
Test name
Test status
Simulation time 22643412 ps
CPU time 0.94 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 205648 kb
Host smart-4a8f25ed-f223-4413-8c91-304c31ddcb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41253339957909627077346793562188387435841001626953331273347603923374598920604 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.edn_genbits.41253339957909627077346793562188387435841001626953331273347603923374598920604
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.78917691335403549941251699886491516889296342332529073160412808499678714358851
Short name T503
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:30:40 PM PDT 23
Finished Oct 18 01:30:41 PM PDT 23
Peak memory 222904 kb
Host smart-32d367df-9780-4911-983c-696d035a5832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78917691335403549941251699886491516889296342332529073160412808499678714358851 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.edn_intr.78917691335403549941251699886491516889296342332529073160412808499678714358851
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.45456763490579025246335755872777686141269715008183618055605856156975581360868
Short name T393
Test name
Test status
Simulation time 21768426 ps
CPU time 0.88 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 205692 kb
Host smart-86b1a7d9-34f7-427f-9596-60c9c9b0eb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45456763490579025246335755872777686141269715008183618055605856156975581360868 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_smoke.45456763490579025246335755872777686141269715008183618055605856156975581360868
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.93581419834340299933992128747221631304986353890515707198310080339639871091296
Short name T479
Test name
Test status
Simulation time 299451483 ps
CPU time 3.53 seconds
Started Oct 18 01:30:47 PM PDT 23
Finished Oct 18 01:30:51 PM PDT 23
Peak memory 206548 kb
Host smart-a77c0abc-2bcd-4077-89b5-ee44d4de6892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93581419834340299933992128747221631304986353890515707198310080339639871091296 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.93581419834340299933992128747221631304986353890515707198310080339639871091296
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.25949673362868668579607233946198556527604808573539985486194032832810410862518
Short name T526
Test name
Test status
Simulation time 86880545330 ps
CPU time 1099.51 seconds
Started Oct 18 01:30:38 PM PDT 23
Finished Oct 18 01:48:58 PM PDT 23
Peak memory 218676 kb
Host smart-f6ef45f2-044c-4162-b87a-dd03fb4e6966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259496733628686685796072339
46198556527604808573539985486194032832810410862518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.25949673362
868668579607233946198556527604808573539985486194032832810410862518
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.98027659615834991119124349576015759669147337410311298649367900993944570782142
Short name T186
Test name
Test status
Simulation time 32330757 ps
CPU time 0.97 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205976 kb
Host smart-164702ac-daaf-4286-b691-322f10918aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98027659615834991119124349576015759669147337410311298649367900993944570782142 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.edn_alert.98027659615834991119124349576015759669147337410311298649367900993944570782142
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.57717506149650174313982386569375218059238948981472495211585981452305570921162
Short name T372
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:18 PM PDT 23
Peak memory 205988 kb
Host smart-72d7f2e6-f8a2-4f41-8cff-7ce083c64640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57717506149650174313982386569375218059238948981472495211585981452305570921162 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_alert_test.57717506149650174313982386569375218059238948981472495211585981452305570921162
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.55087096310899772124484128640850560046139735743948192665742431012808061520535
Short name T522
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 215124 kb
Host smart-fb69f638-7fd0-44b4-850b-befea17be764
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55087096310899772124484128640850560046139735743948192665742431012808061520535 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.edn_disable.55087096310899772124484128640850560046139735743948192665742431012808061520535
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.36225601922977675321946847414780417399773343374580865124090915272407928022600
Short name T521
Test name
Test status
Simulation time 30622451 ps
CPU time 0.93 seconds
Started Oct 18 01:30:38 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 215220 kb
Host smart-f962a3a0-5cd9-4d42-9859-6420b7df58fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36225601922977675321946847414780417399773343374580865124090915272407928022600 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.3622560192297767532194684741478041739977334337458086512409
0915272407928022600
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2668646079302612112503256386629335204134922384958295429999686904311101229648
Short name T496
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 215184 kb
Host smart-a4baac69-22b2-4ae3-8d94-84cede09fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668646079302612112503256386629335204134922384958295429999686904311101229648 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
edn_err.2668646079302612112503256386629335204134922384958295429999686904311101229648
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.101029236639447178289405532803324112584643836819907711232619138698814994192580
Short name T520
Test name
Test status
Simulation time 22643412 ps
CPU time 0.93 seconds
Started Oct 18 01:30:50 PM PDT 23
Finished Oct 18 01:30:51 PM PDT 23
Peak memory 205672 kb
Host smart-bb9b9de5-de1b-48d9-b622-199a55ebf7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101029236639447178289405532803324112584643836819907711232619138698814994192580 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.edn_genbits.101029236639447178289405532803324112584643836819907711232619138698814994192580
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.114695594226752378273988381164786244141919541226510355323295260120619404504476
Short name T32
Test name
Test status
Simulation time 22372583 ps
CPU time 1.04 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 222940 kb
Host smart-1ade724e-c3eb-4366-80d4-a405fef3fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114695594226752378273988381164786244141919541226510355323295260120619404504476 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.edn_intr.114695594226752378273988381164786244141919541226510355323295260120619404504476
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.35173360672331590247526959762896950141532997509176810991226418919475310982847
Short name T384
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:31:00 PM PDT 23
Finished Oct 18 01:31:01 PM PDT 23
Peak memory 205572 kb
Host smart-2e5c7af3-5a6d-4004-a121-4cfd064fb405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35173360672331590247526959762896950141532997509176810991226418919475310982847 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.edn_smoke.35173360672331590247526959762896950141532997509176810991226418919475310982847
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.26740420873048648501891060575709118016333716608427706734583100872773763925041
Short name T564
Test name
Test status
Simulation time 299451483 ps
CPU time 3.67 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 206568 kb
Host smart-6fdb5934-cc9e-48a0-9d4e-f4ebdbeb65ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26740420873048648501891060575709118016333716608427706734583100872773763925041 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.26740420873048648501891060575709118016333716608427706734583100872773763925041
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.90746188018786361617475159488679810784562646728583227118304223012564030540008
Short name T528
Test name
Test status
Simulation time 86880545330 ps
CPU time 1098.25 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:48:48 PM PDT 23
Peak memory 218640 kb
Host smart-0d956dce-19ef-4142-bfa0-ee5eb09eabaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907461880187863616174751594
88679810784562646728583227118304223012564030540008 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.90746188018
786361617475159488679810784562646728583227118304223012564030540008
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.73850042991430665422102098557592371384318739159104191825162718027507974309602
Short name T611
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:34 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 205904 kb
Host smart-d63246d8-6f39-467f-ab1c-8bf24f9083c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73850042991430665422102098557592371384318739159104191825162718027507974309602 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_alert.73850042991430665422102098557592371384318739159104191825162718027507974309602
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.112473080159941336321096423209762523901121555173948838425808808981322305555347
Short name T712
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:36 PM PDT 23
Peak memory 205988 kb
Host smart-aa34c2b7-fa21-41c6-af3e-b700b1c39a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112473080159941336321096423209762523901121555173948838425808808981322305555347 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.edn_alert_test.112473080159941336321096423209762523901121555173948838425808808981322305555347
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.75475136893223759156631651083694040950544833303033479511823101437795337959761
Short name T698
Test name
Test status
Simulation time 19976788 ps
CPU time 0.85 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 215168 kb
Host smart-1e2276dc-0be0-4245-b1d0-f78981fa5bc9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75475136893223759156631651083694040950544833303033479511823101437795337959761 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.edn_disable.75475136893223759156631651083694040950544833303033479511823101437795337959761
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.87369977145305048843946596185764359594003419750604116194576965849236950280371
Short name T418
Test name
Test status
Simulation time 30622451 ps
CPU time 0.95 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 215196 kb
Host smart-ded3f7d3-af1b-4368-9216-7901216968be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87369977145305048843946596185764359594003419750604116194576965849236950280371 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.8736997714530504884394659618576435959400341975060411619457
6965849236950280371
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.88806516479333147707608520506164130750185612900007578950478736828045178508179
Short name T669
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 215292 kb
Host smart-4450176e-89b0-4ba7-b342-4614a8a4f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88806516479333147707608520506164130750185612900007578950478736828045178508179 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.edn_err.88806516479333147707608520506164130750185612900007578950478736828045178508179
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.105951934418978737443214285292621525433359835671413405905607662636644537813268
Short name T352
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:43 PM PDT 23
Peak memory 205764 kb
Host smart-1837749e-f0db-4d43-a7b3-38a3f39192a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105951934418978737443214285292621525433359835671413405905607662636644537813268 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.edn_genbits.105951934418978737443214285292621525433359835671413405905607662636644537813268
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.44849618753047844454483250152281939184377234644929825511730697972814430782631
Short name T438
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 222940 kb
Host smart-bf16def7-438b-4953-8d3d-42feaa9c9669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44849618753047844454483250152281939184377234644929825511730697972814430782631 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.edn_intr.44849618753047844454483250152281939184377234644929825511730697972814430782631
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.14905020757013450400787711974291766925991722038366056286770226729011891125456
Short name T399
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:30:47 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 205688 kb
Host smart-5c93145c-04f9-4845-9e1f-91cb16f73f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14905020757013450400787711974291766925991722038366056286770226729011891125456 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_smoke.14905020757013450400787711974291766925991722038366056286770226729011891125456
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.20009332769365179691473940718848308661285433966205499871721961370189987900713
Short name T182
Test name
Test status
Simulation time 299451483 ps
CPU time 3.54 seconds
Started Oct 18 01:30:40 PM PDT 23
Finished Oct 18 01:30:44 PM PDT 23
Peak memory 206516 kb
Host smart-a5597911-36d1-407b-b2f8-a599b32f22da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20009332769365179691473940718848308661285433966205499871721961370189987900713 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.20009332769365179691473940718848308661285433966205499871721961370189987900713
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.32235340032650444567048320581088464583131222364565792641734204678255133218733
Short name T162
Test name
Test status
Simulation time 86880545330 ps
CPU time 1134.76 seconds
Started Oct 18 01:30:12 PM PDT 23
Finished Oct 18 01:49:07 PM PDT 23
Peak memory 218604 kb
Host smart-56e3d153-35fd-43da-a336-cc9f7f92166f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322353400326504445670483205
81088464583131222364565792641734204678255133218733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.32235340032
650444567048320581088464583131222364565792641734204678255133218733
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.114045179764907208275110824966603420519160478539371061470468690232299780796293
Short name T436
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 205908 kb
Host smart-eaa45628-a8fb-4176-9d86-e0c247a31e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114045179764907208275110824966603420519160478539371061470468690232299780796293 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.edn_alert.114045179764907208275110824966603420519160478539371061470468690232299780796293
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.27167371246183033865086897992577711464713290766269657613408749896127506104153
Short name T655
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 205904 kb
Host smart-4247a2d9-254f-4d00-ad48-8f72d0ac214a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167371246183033865086897992577711464713290766269657613408749896127506104153 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_alert_test.27167371246183033865086897992577711464713290766269657613408749896127506104153
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.11245627208870635778009364684945157034800225691852792375029795492246082511998
Short name T177
Test name
Test status
Simulation time 19976788 ps
CPU time 0.87 seconds
Started Oct 18 01:30:53 PM PDT 23
Finished Oct 18 01:30:54 PM PDT 23
Peak memory 215040 kb
Host smart-a3994f92-631e-4f4a-9884-873613e96a93
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11245627208870635778009364684945157034800225691852792375029795492246082511998 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.edn_disable.11245627208870635778009364684945157034800225691852792375029795492246082511998
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.65813703451519581888897809687315852233818155895353857771785714212129962792786
Short name T552
Test name
Test status
Simulation time 30622451 ps
CPU time 0.99 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 215300 kb
Host smart-c1458c7c-cf26-4637-b08a-134caf0eb8f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65813703451519581888897809687315852233818155895353857771785714212129962792786 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.6581370345151958188889780968731585223381815589535385777178
5714212129962792786
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.52396871672157013620321831121888948320686679476669668472713474937662957934563
Short name T614
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 215200 kb
Host smart-9d63b590-5df3-43c8-92e2-8918ac502155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52396871672157013620321831121888948320686679476669668472713474937662957934563 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.edn_err.52396871672157013620321831121888948320686679476669668472713474937662957934563
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.9714063021666150329516627184465315396320085929629797648159584000164698805810
Short name T341
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 205724 kb
Host smart-caa8fbb1-6c71-439d-a054-60cf7a758b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9714063021666150329516627184465315396320085929629797648159584000164698805810 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.edn_genbits.9714063021666150329516627184465315396320085929629797648159584000164698805810
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.82362671449206968806565663638694386102388495243507355755822702919881168287691
Short name T561
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 222940 kb
Host smart-34d48305-5d78-4e04-97cf-8318142fc98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82362671449206968806565663638694386102388495243507355755822702919881168287691 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.edn_intr.82362671449206968806565663638694386102388495243507355755822702919881168287691
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.15096507489133902023545744954593287239602831680943171630445096698046954189273
Short name T609
Test name
Test status
Simulation time 21768426 ps
CPU time 0.83 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 205624 kb
Host smart-de5b739b-ace6-48f9-9513-6c5feb793392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15096507489133902023545744954593287239602831680943171630445096698046954189273 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.edn_smoke.15096507489133902023545744954593287239602831680943171630445096698046954189273
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.23580170640720518253275059414036554539620288048876713574730382785637243415291
Short name T414
Test name
Test status
Simulation time 299451483 ps
CPU time 3.6 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:26 PM PDT 23
Peak memory 206240 kb
Host smart-f266fc21-d7ed-4858-b0af-226d27463541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23580170640720518253275059414036554539620288048876713574730382785637243415291 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.23580170640720518253275059414036554539620288048876713574730382785637243415291
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.108185643857268118171053677492599013357473134398616217083934635674124329840046
Short name T4
Test name
Test status
Simulation time 86880545330 ps
CPU time 1137.32 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:49:33 PM PDT 23
Peak memory 218620 kb
Host smart-c67c1cf9-611c-4e07-bb08-53711c050aee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108185643857268118171053677
492599013357473134398616217083934635674124329840046 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1081856438
57268118171053677492599013357473134398616217083934635674124329840046
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.72932446032529081623451464835809509949228613309747944579332673500981385155921
Short name T653
Test name
Test status
Simulation time 32330757 ps
CPU time 1.08 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:15 PM PDT 23
Peak memory 205944 kb
Host smart-5d78cce5-2e7f-4842-b5ba-c3690d4a9e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72932446032529081623451464835809509949228613309747944579332673500981385155921 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_alert.72932446032529081623451464835809509949228613309747944579332673500981385155921
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.22133384866371418005799661791488309171445028365798948789978984801615699833731
Short name T28
Test name
Test status
Simulation time 16111390 ps
CPU time 0.97 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 206024 kb
Host smart-89813c3a-fafb-44c0-a9cb-5e4957a77d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133384866371418005799661791488309171445028365798948789978984801615699833731 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_alert_test.22133384866371418005799661791488309171445028365798948789978984801615699833731
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.48524246187475861383182151429894754617527323580932612060850651681995622765961
Short name T191
Test name
Test status
Simulation time 19976788 ps
CPU time 0.82 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:26 PM PDT 23
Peak memory 215140 kb
Host smart-2e02f353-3b0f-4966-8fb7-46330027c8cf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48524246187475861383182151429894754617527323580932612060850651681995622765961 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.edn_disable.48524246187475861383182151429894754617527323580932612060850651681995622765961
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.91955557071602819626290069862007025629361320388946955232277303758169377480991
Short name T516
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:32 PM PDT 23
Finished Oct 18 01:30:43 PM PDT 23
Peak memory 215252 kb
Host smart-4a213a4f-b74e-45fc-87a3-53c950f99a5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91955557071602819626290069862007025629361320388946955232277303758169377480991 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.9195555707160281962629006986200702562936132038894695523227
7303758169377480991
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.81029559401067583479341777590355705895877625496161508583080744689010941692165
Short name T701
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:33 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 215216 kb
Host smart-84f12edd-c6e3-42b1-900b-2f98e0b9df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81029559401067583479341777590355705895877625496161508583080744689010941692165 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.edn_err.81029559401067583479341777590355705895877625496161508583080744689010941692165
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.63058040353290230795690904633309978031435372443786736985241502202426568978770
Short name T694
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 205776 kb
Host smart-31d873be-47e3-4056-9cd9-9f465c397c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63058040353290230795690904633309978031435372443786736985241502202426568978770 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.edn_genbits.63058040353290230795690904633309978031435372443786736985241502202426568978770
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.95916937749530198616203809549923571478644984589376889380594234648784555659198
Short name T692
Test name
Test status
Simulation time 22372583 ps
CPU time 0.96 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 222924 kb
Host smart-8aeb4d54-6c21-425f-9cd5-5bac3b840ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95916937749530198616203809549923571478644984589376889380594234648784555659198 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.edn_intr.95916937749530198616203809549923571478644984589376889380594234648784555659198
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.48581129835673264140862086283087890431125479677980239804081949260083304969974
Short name T410
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 205624 kb
Host smart-de190a0a-fea8-4d1c-a572-d94b54ee849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48581129835673264140862086283087890431125479677980239804081949260083304969974 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_smoke.48581129835673264140862086283087890431125479677980239804081949260083304969974
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.77611395359291043861041688729958342377900554287658908836702624195719421966702
Short name T416
Test name
Test status
Simulation time 299451483 ps
CPU time 3.64 seconds
Started Oct 18 01:30:45 PM PDT 23
Finished Oct 18 01:30:49 PM PDT 23
Peak memory 206492 kb
Host smart-cb688b17-7f28-44ee-92c2-9799fd3d11ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77611395359291043861041688729958342377900554287658908836702624195719421966702 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.77611395359291043861041688729958342377900554287658908836702624195719421966702
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.44105448185604566741011409457151905695956896766785673944568199395832446626902
Short name T623
Test name
Test status
Simulation time 86880545330 ps
CPU time 1117.97 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:49:09 PM PDT 23
Peak memory 218564 kb
Host smart-9279f2d2-2c0c-4c45-b5dd-36c82a7c6c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441054481856045667410114094
57151905695956896766785673944568199395832446626902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.44105448185
604566741011409457151905695956896766785673944568199395832446626902
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.16796344641812047928297481178385576420159436785480619622723474292674015571914
Short name T710
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:30:59 PM PDT 23
Peak memory 205940 kb
Host smart-41a57cf5-5efa-4f60-9356-718eac46665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16796344641812047928297481178385576420159436785480619622723474292674015571914 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.edn_alert.16796344641812047928297481178385576420159436785480619622723474292674015571914
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.96242532585969411508865831991548357464465971278270616352953804179960461744615
Short name T666
Test name
Test status
Simulation time 16111390 ps
CPU time 0.92 seconds
Started Oct 18 01:29:42 PM PDT 23
Finished Oct 18 01:29:43 PM PDT 23
Peak memory 206048 kb
Host smart-6c6cea8e-18a0-4179-86d0-ee0e217d7d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96242532585969411508865831991548357464465971278270616352953804179960461744615 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_alert_test.96242532585969411508865831991548357464465971278270616352953804179960461744615
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.19277867096218185093300470220976111543533599517316810276416636424484649849189
Short name T68
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:08 PM PDT 23
Finished Oct 18 01:30:10 PM PDT 23
Peak memory 215084 kb
Host smart-41e5da01-687e-4334-ad17-eb6d14af63c8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277867096218185093300470220976111543533599517316810276416636424484649849189 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_disable.19277867096218185093300470220976111543533599517316810276416636424484649849189
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.48267331942046223870263103184949743739344473490559916591384880396630924322755
Short name T525
Test name
Test status
Simulation time 30622451 ps
CPU time 1 seconds
Started Oct 18 01:29:48 PM PDT 23
Finished Oct 18 01:29:50 PM PDT 23
Peak memory 215284 kb
Host smart-993687df-ad0a-4c8e-9c3b-5e1c12034750
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48267331942046223870263103184949743739344473490559916591384880396630924322755 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.48267331942046223870263103184949743739344473490559916591384
880396630924322755
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.68006219398038130993014288817631861578389130692024143685733239285437283961728
Short name T557
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:29:38 PM PDT 23
Finished Oct 18 01:29:39 PM PDT 23
Peak memory 215300 kb
Host smart-1e6d5dcc-e32a-4c75-95ba-334f86d033d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68006219398038130993014288817631861578389130692024143685733239285437283961728 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
edn_err.68006219398038130993014288817631861578389130692024143685733239285437283961728
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.14631746663290202410746691626943947700951952065161178305336270243687988539706
Short name T493
Test name
Test status
Simulation time 22643412 ps
CPU time 0.93 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:31:00 PM PDT 23
Peak memory 205748 kb
Host smart-4f136543-cdcc-4b62-ae56-409cb2262c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14631746663290202410746691626943947700951952065161178305336270243687988539706 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.edn_genbits.14631746663290202410746691626943947700951952065161178305336270243687988539706
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.31518203551839454284244389443897133277284225723018287271187925858763376125707
Short name T351
Test name
Test status
Simulation time 22372583 ps
CPU time 0.98 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 222892 kb
Host smart-2dc213df-6500-4a8b-b129-fcb6ee8bb98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31518203551839454284244389443897133277284225723018287271187925858763376125707 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.edn_intr.31518203551839454284244389443897133277284225723018287271187925858763376125707
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.88400105165280299624046320046324931342814329800254467906017924527243997999186
Short name T417
Test name
Test status
Simulation time 19018470 ps
CPU time 0.86 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 205664 kb
Host smart-01f35f20-329d-4111-82e7-585758914bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88400105165280299624046320046324931342814329800254467906017924527243997999186 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.edn_regwen.88400105165280299624046320046324931342814329800254467906017924527243997999186
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.40682291132528626417784567404862527794144239797438503236834703997401468705793
Short name T26
Test name
Test status
Simulation time 359808016 ps
CPU time 5.79 seconds
Started Oct 18 01:29:53 PM PDT 23
Finished Oct 18 01:29:59 PM PDT 23
Peak memory 235480 kb
Host smart-b4d81515-0af4-4a5e-9ad0-a1edaf3b869e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40682291132528626417784567404862527794144239797438503236834703997401468705793 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_sec_cm.40682291132528626417784567404862527794144239797438503236834703997401468705793
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.114818965262196504701114045765008187282988517801577599088306320567610425997124
Short name T388
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:31:12 PM PDT 23
Peak memory 205660 kb
Host smart-9ddb6c7e-2d19-46b5-8501-183eaafd81a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114818965262196504701114045765008187282988517801577599088306320567610425997124 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.edn_smoke.114818965262196504701114045765008187282988517801577599088306320567610425997124
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.37627045842403664102695941411091266849979462973680705300633316352908117485948
Short name T39
Test name
Test status
Simulation time 299451483 ps
CPU time 3.69 seconds
Started Oct 18 01:31:27 PM PDT 23
Finished Oct 18 01:31:31 PM PDT 23
Peak memory 206512 kb
Host smart-0ac12b5b-c0c1-4b2d-ba0a-8465c4c7a0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37627045842403664102695941411091266849979462973680705300633316352908117485948 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.37627045842403664102695941411091266849979462973680705300633316352908117485948
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.82351915615619169796403331391033940094529297790854865239178384563140226907265
Short name T475
Test name
Test status
Simulation time 86880545330 ps
CPU time 1065.25 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:48:23 PM PDT 23
Peak memory 218596 kb
Host smart-9b3c32d7-e7b4-4bd4-8ee0-6b48f61ae5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823519156156191697964033313
91033940094529297790854865239178384563140226907265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.823519156156
19169796403331391033940094529297790854865239178384563140226907265
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.102770154425414862573842575370126563233315354611792472434181987214164169040311
Short name T702
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 205972 kb
Host smart-f85093b0-e918-4ded-86c0-432e9baca0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102770154425414862573842575370126563233315354611792472434181987214164169040311 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.edn_alert.102770154425414862573842575370126563233315354611792472434181987214164169040311
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.78815533925363793880480720428547942110402098543530977427268073357217819412674
Short name T671
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 205932 kb
Host smart-0042970b-dd5d-47a8-957a-23bde2231c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78815533925363793880480720428547942110402098543530977427268073357217819412674 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_alert_test.78815533925363793880480720428547942110402098543530977427268073357217819412674
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.73483829751747535711662535871170885213661316486419691250849020427801155733665
Short name T514
Test name
Test status
Simulation time 19976788 ps
CPU time 0.85 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 215164 kb
Host smart-200431e3-65de-49cb-906d-f9f85ef07f29
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73483829751747535711662535871170885213661316486419691250849020427801155733665 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.edn_disable.73483829751747535711662535871170885213661316486419691250849020427801155733665
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.58576723730560285927741452757917449749864010402514812851616104370149219899873
Short name T643
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 214472 kb
Host smart-2e90d686-484a-4a5d-a7f6-74bc085bddae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58576723730560285927741452757917449749864010402514812851616104370149219899873 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.5857672373056028592774145275791744974986401040251481285161
6104370149219899873
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.88018215314865364807710178362067549736100517288139850893507324196934573473234
Short name T133
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:30:31 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 215296 kb
Host smart-8824c6f9-7fb5-4a75-8a07-c7ef8e3c4775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88018215314865364807710178362067549736100517288139850893507324196934573473234 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.edn_err.88018215314865364807710178362067549736100517288139850893507324196934573473234
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.107975693281402353467313115024244929971408378240918775517379259580344087411681
Short name T450
Test name
Test status
Simulation time 22643412 ps
CPU time 0.93 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:18 PM PDT 23
Peak memory 205760 kb
Host smart-7fdc2578-0eb9-4132-80f6-620250b9cc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107975693281402353467313115024244929971408378240918775517379259580344087411681 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.edn_genbits.107975693281402353467313115024244929971408378240918775517379259580344087411681
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.75350928076088766684246044764238140573700389907471444968863031011144377049375
Short name T403
Test name
Test status
Simulation time 22372583 ps
CPU time 0.98 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 222888 kb
Host smart-8b5a3f5d-f450-4e16-92e2-dd854e811f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75350928076088766684246044764238140573700389907471444968863031011144377049375 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.edn_intr.75350928076088766684246044764238140573700389907471444968863031011144377049375
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.55184863918108393196709954609156583082266007770374327913003284561942177732876
Short name T577
Test name
Test status
Simulation time 21768426 ps
CPU time 0.87 seconds
Started Oct 18 01:30:13 PM PDT 23
Finished Oct 18 01:30:14 PM PDT 23
Peak memory 205688 kb
Host smart-d81bd5dc-02b7-4f4e-be61-6eedcab3bee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55184863918108393196709954609156583082266007770374327913003284561942177732876 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.edn_smoke.55184863918108393196709954609156583082266007770374327913003284561942177732876
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.87394271031627702413315205678306441663877208976789912102214448196876904790590
Short name T632
Test name
Test status
Simulation time 299451483 ps
CPU time 3.78 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:34 PM PDT 23
Peak memory 206532 kb
Host smart-2bdd5496-8155-43d0-b07c-bf2318f2e028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87394271031627702413315205678306441663877208976789912102214448196876904790590 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.87394271031627702413315205678306441663877208976789912102214448196876904790590
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.7882268333315329676845810209723851247462589543778239855789799245465066084626
Short name T515
Test name
Test status
Simulation time 86880545330 ps
CPU time 1070.18 seconds
Started Oct 18 01:30:23 PM PDT 23
Finished Oct 18 01:48:14 PM PDT 23
Peak memory 218648 kb
Host smart-07e823d0-6bca-4d9d-bce8-2639ce2b4943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788226833331532967684581020
9723851247462589543778239855789799245465066084626 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.788226833331
5329676845810209723851247462589543778239855789799245465066084626
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.84470868608568111686696738292875899665761585296338015246975887668483821978472
Short name T575
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:30:23 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 205888 kb
Host smart-31347e90-ec30-4a45-859a-bf368ae2efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84470868608568111686696738292875899665761585296338015246975887668483821978472 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_alert.84470868608568111686696738292875899665761585296338015246975887668483821978472
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.34676963789065939088522694688946718469425220152072800079979641184158131409612
Short name T725
Test name
Test status
Simulation time 16111390 ps
CPU time 0.93 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 205868 kb
Host smart-a9f84de9-4109-433b-aeb5-a5d01646fd68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34676963789065939088522694688946718469425220152072800079979641184158131409612 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_alert_test.34676963789065939088522694688946718469425220152072800079979641184158131409612
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.32278916371944952435368487203928454665518287570880821118246960349470061773552
Short name T67
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 215096 kb
Host smart-6973cb1a-c521-4014-b7a5-94bed488fa1c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32278916371944952435368487203928454665518287570880821118246960349470061773552 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.edn_disable.32278916371944952435368487203928454665518287570880821118246960349470061773552
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3066471712337432258954460469592519803640050340782716133631739214337119323550
Short name T30
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 214400 kb
Host smart-e91be730-f390-478a-b979-58639b3d1c9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066471712337432258954460469592519803640050340782716133631739214337119323550 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.30664717123374322589544604695925198036400503407827161336317
39214337119323550
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.19825019338382788876290130616418572515875740791177440326394693313189523597844
Short name T107
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 215420 kb
Host smart-685d4a5c-e5b0-4a64-b39f-2c314f23998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19825019338382788876290130616418572515875740791177440326394693313189523597844 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.edn_err.19825019338382788876290130616418572515875740791177440326394693313189523597844
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.74195130068379615972563283403252505900589363415234177141475025221538931351950
Short name T531
Test name
Test status
Simulation time 22643412 ps
CPU time 0.91 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205684 kb
Host smart-519e95ca-c797-4507-a215-ccc1faffe475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74195130068379615972563283403252505900589363415234177141475025221538931351950 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.edn_genbits.74195130068379615972563283403252505900589363415234177141475025221538931351950
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.12656412423417402314609140684384111356528845887966727180059293272271500855054
Short name T33
Test name
Test status
Simulation time 22372583 ps
CPU time 1.03 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:16 PM PDT 23
Peak memory 222848 kb
Host smart-b00abe23-734a-4a6a-9611-02a8c0fccdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12656412423417402314609140684384111356528845887966727180059293272271500855054 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.edn_intr.12656412423417402314609140684384111356528845887966727180059293272271500855054
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.84312028556855788684908756435673274346585341675619834462263870234659117031922
Short name T548
Test name
Test status
Simulation time 21768426 ps
CPU time 0.88 seconds
Started Oct 18 01:30:34 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 205600 kb
Host smart-7d26a364-41eb-44d3-85d7-5965f40f9506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84312028556855788684908756435673274346585341675619834462263870234659117031922 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_smoke.84312028556855788684908756435673274346585341675619834462263870234659117031922
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.36680657686647584243220078581801392060067874495975448803067267471326965296385
Short name T610
Test name
Test status
Simulation time 299451483 ps
CPU time 3.75 seconds
Started Oct 18 01:30:33 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 206516 kb
Host smart-2b2fed79-a078-4584-abd0-5dec58629060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36680657686647584243220078581801392060067874495975448803067267471326965296385 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.36680657686647584243220078581801392060067874495975448803067267471326965296385
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.43607958556231893337636054309684258760833363322309877656724210008482672518165
Short name T167
Test name
Test status
Simulation time 86880545330 ps
CPU time 1083.16 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:48:32 PM PDT 23
Peak memory 218676 kb
Host smart-f9e4d78e-bcd2-431a-a581-767e7911add7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436079585562318933376360543
09684258760833363322309877656724210008482672518165 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.43607958556
231893337636054309684258760833363322309877656724210008482672518165
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.100557516343133172023149041231711005346359388028705002907564803659199950276850
Short name T456
Test name
Test status
Simulation time 32330757 ps
CPU time 0.91 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205872 kb
Host smart-f38af515-0980-49ad-a25e-0d0ec74d3887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100557516343133172023149041231711005346359388028705002907564803659199950276850 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.edn_alert.100557516343133172023149041231711005346359388028705002907564803659199950276850
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.74919960596860325906471217313640544411750547412001713910347051998901208055759
Short name T64
Test name
Test status
Simulation time 16111390 ps
CPU time 0.94 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205976 kb
Host smart-c2caf5b0-8cf7-451e-a1a9-fbb7a4a08f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74919960596860325906471217313640544411750547412001713910347051998901208055759 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_alert_test.74919960596860325906471217313640544411750547412001713910347051998901208055759
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.47085333526124260867448712294380476935243898136853922194005271876177535638588
Short name T547
Test name
Test status
Simulation time 19976788 ps
CPU time 0.89 seconds
Started Oct 18 01:30:22 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 215132 kb
Host smart-7c97fbce-028c-45c9-9fe7-0d32aed6f89e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47085333526124260867448712294380476935243898136853922194005271876177535638588 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.edn_disable.47085333526124260867448712294380476935243898136853922194005271876177535638588
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.31038115306182764104246986707052520997341519079860938278388034597353255880447
Short name T468
Test name
Test status
Simulation time 30622451 ps
CPU time 0.95 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 215264 kb
Host smart-bc95f7a0-f703-4ec3-873f-32c1eef072b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31038115306182764104246986707052520997341519079860938278388034597353255880447 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.3103811530618276410424698670705252099734151907986093827838
8034597353255880447
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.76513960538821703728013322873903627231973562161010495081623022540603441845970
Short name T126
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 215212 kb
Host smart-205b1287-0aef-436f-977b-727c1cdbc081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76513960538821703728013322873903627231973562161010495081623022540603441845970 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.edn_err.76513960538821703728013322873903627231973562161010495081623022540603441845970
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.58251077692369741526703399499060059695672237599340565881987754050635724138976
Short name T445
Test name
Test status
Simulation time 22643412 ps
CPU time 0.94 seconds
Started Oct 18 01:30:11 PM PDT 23
Finished Oct 18 01:30:12 PM PDT 23
Peak memory 205740 kb
Host smart-87828002-5393-4f4b-b348-07ee7a61e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58251077692369741526703399499060059695672237599340565881987754050635724138976 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.edn_genbits.58251077692369741526703399499060059695672237599340565881987754050635724138976
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.63250090641687531931174035791560928262455392243252897692955186531859041276934
Short name T630
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:30:50 PM PDT 23
Finished Oct 18 01:30:51 PM PDT 23
Peak memory 222908 kb
Host smart-b0de0d40-6c8b-4e95-9fe8-a3a5cd8f2b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63250090641687531931174035791560928262455392243252897692955186531859041276934 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.edn_intr.63250090641687531931174035791560928262455392243252897692955186531859041276934
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.107029732306351027235413779043388388945365233361746833350435723126047320721750
Short name T187
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 204952 kb
Host smart-810429c1-3725-4798-822a-eb61042aa672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107029732306351027235413779043388388945365233361746833350435723126047320721750 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.edn_smoke.107029732306351027235413779043388388945365233361746833350435723126047320721750
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.19765450553144205145221001400784421524299052675232983030305978690360191599919
Short name T373
Test name
Test status
Simulation time 299451483 ps
CPU time 3.69 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 206548 kb
Host smart-e58fb8ec-10c8-46d1-904c-380ed39c773f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19765450553144205145221001400784421524299052675232983030305978690360191599919 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.19765450553144205145221001400784421524299052675232983030305978690360191599919
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.8154670459789622329500056425342029079231861645513818329942520327423791193873
Short name T530
Test name
Test status
Simulation time 86880545330 ps
CPU time 1123.68 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:49:06 PM PDT 23
Peak memory 218648 kb
Host smart-7aa79189-814b-454c-b317-9f3122c178f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815467045978962232950005642
5342029079231861645513818329942520327423791193873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.815467045978
9622329500056425342029079231861645513818329942520327423791193873
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.99830218344263729296147108980961735803747357507301927161727183435515068348296
Short name T718
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:30:11 PM PDT 23
Finished Oct 18 01:30:12 PM PDT 23
Peak memory 205948 kb
Host smart-2e5ca675-0a42-43e5-a5cc-8dd3fd020604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99830218344263729296147108980961735803747357507301927161727183435515068348296 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_alert.99830218344263729296147108980961735803747357507301927161727183435515068348296
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.22913173699854122948505903335049965810557139232692383010821088580794136379949
Short name T645
Test name
Test status
Simulation time 16111390 ps
CPU time 0.94 seconds
Started Oct 18 01:30:48 PM PDT 23
Finished Oct 18 01:30:50 PM PDT 23
Peak memory 206020 kb
Host smart-927b2592-40e3-4a08-9244-4a04c0df6c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913173699854122948505903335049965810557139232692383010821088580794136379949 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_alert_test.22913173699854122948505903335049965810557139232692383010821088580794136379949
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.55301477452530886895712620792909442094478764669602375397276315243317425318285
Short name T369
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:30:38 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 215040 kb
Host smart-671b5e2b-0fd1-4c12-988a-b632fe4cbe55
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55301477452530886895712620792909442094478764669602375397276315243317425318285 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.edn_disable.55301477452530886895712620792909442094478764669602375397276315243317425318285
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.26712623965118141768043675167042643097028107134649873966349466779819529651415
Short name T638
Test name
Test status
Simulation time 30622451 ps
CPU time 0.94 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 215204 kb
Host smart-95a31e38-42de-4506-a2dd-47477db1a079
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26712623965118141768043675167042643097028107134649873966349466779819529651415 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.2671262396511814176804367516704264309702810713464987396634
9466779819529651415
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.103553265414795821956129012662444175529580872859027179331927243554036487525950
Short name T378
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 215300 kb
Host smart-9f2cc093-470b-434a-b11b-08231c03bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103553265414795821956129012662444175529580872859027179331927243554036487525950 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.edn_err.103553265414795821956129012662444175529580872859027179331927243554036487525950
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.42690755716012026660738104109644536417347121435868217121133775255786388461571
Short name T147
Test name
Test status
Simulation time 22643412 ps
CPU time 0.94 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 205784 kb
Host smart-1e9f2705-77d0-4e27-b439-267e1ab1cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42690755716012026660738104109644536417347121435868217121133775255786388461571 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.edn_genbits.42690755716012026660738104109644536417347121435868217121133775255786388461571
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.31173044294207966005405549032873410048744934003813764584847261080353282902725
Short name T626
Test name
Test status
Simulation time 22372583 ps
CPU time 0.96 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 222860 kb
Host smart-4673e280-f7e2-4bdc-abc1-7ae405c0a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31173044294207966005405549032873410048744934003813764584847261080353282902725 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.edn_intr.31173044294207966005405549032873410048744934003813764584847261080353282902725
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.11539584354069806885498201864589992826907557160063467663397069576318200798560
Short name T20
Test name
Test status
Simulation time 21768426 ps
CPU time 0.89 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:20 PM PDT 23
Peak memory 205728 kb
Host smart-79de146c-03a8-4e66-b03d-2db72fe2f1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11539584354069806885498201864589992826907557160063467663397069576318200798560 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_smoke.11539584354069806885498201864589992826907557160063467663397069576318200798560
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.22028457175212342192021023153391929460926837036937137355395594126678108239706
Short name T567
Test name
Test status
Simulation time 299451483 ps
CPU time 3.48 seconds
Started Oct 18 01:30:50 PM PDT 23
Finished Oct 18 01:30:54 PM PDT 23
Peak memory 206516 kb
Host smart-3c8a2255-d8ac-45cf-b893-b0eb7b7f1fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028457175212342192021023153391929460926837036937137355395594126678108239706 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.22028457175212342192021023153391929460926837036937137355395594126678108239706
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.102235981389738943775252520794432196770242173054707424928472390987210045546402
Short name T335
Test name
Test status
Simulation time 86880545330 ps
CPU time 1060.45 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:48:00 PM PDT 23
Peak memory 218644 kb
Host smart-27405b53-cd51-4d23-bf61-d15a3b3173bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102235981389738943775252520
794432196770242173054707424928472390987210045546402 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1022359813
89738943775252520794432196770242173054707424928472390987210045546402
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.68047809176589948510840035489317449119229953793500531367323284835372899466680
Short name T24
Test name
Test status
Simulation time 32330757 ps
CPU time 0.99 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205888 kb
Host smart-06e3628a-2992-4dbc-923a-e2945f3064bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68047809176589948510840035489317449119229953793500531367323284835372899466680 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_alert.68047809176589948510840035489317449119229953793500531367323284835372899466680
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.106567849398617783500420068353974278267476200612820832544885991566816190588282
Short name T451
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 205980 kb
Host smart-8a5c4c9d-7a60-4642-b636-0504983bfbe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106567849398617783500420068353974278267476200612820832544885991566816190588282 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_alert_test.106567849398617783500420068353974278267476200612820832544885991566816190588282
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.17864066743863624753427819225124933686735651599744057118648493660224843877818
Short name T158
Test name
Test status
Simulation time 19976788 ps
CPU time 0.87 seconds
Started Oct 18 01:30:11 PM PDT 23
Finished Oct 18 01:30:12 PM PDT 23
Peak memory 215140 kb
Host smart-94d67810-bdd5-4a08-8cb3-649918df4fed
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17864066743863624753427819225124933686735651599744057118648493660224843877818 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.edn_disable.17864066743863624753427819225124933686735651599744057118648493660224843877818
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.14160086069838037071342208882126462755825439248713266480759478644475267017716
Short name T722
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:31 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 215220 kb
Host smart-003562be-450b-4086-9945-2b35a005c416
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14160086069838037071342208882126462755825439248713266480759478644475267017716 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.1416008606983803707134220888212646275582543924871326648075
9478644475267017716
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4819315702039261687979926048514385369387696052461921692760190142993044609011
Short name T533
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:30:27 PM PDT 23
Finished Oct 18 01:30:28 PM PDT 23
Peak memory 215188 kb
Host smart-7381803e-5875-4c52-87ef-6df296c2b3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4819315702039261687979926048514385369387696052461921692760190142993044609011 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
edn_err.4819315702039261687979926048514385369387696052461921692760190142993044609011
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.27116665058065444830276807568894947603396447994577852098766242940805180647081
Short name T120
Test name
Test status
Simulation time 22643412 ps
CPU time 0.94 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 205660 kb
Host smart-9d6900e2-92c0-4e66-955f-943966ca7a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27116665058065444830276807568894947603396447994577852098766242940805180647081 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.edn_genbits.27116665058065444830276807568894947603396447994577852098766242940805180647081
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.12289785729850847854476505088837106362319288711686162458199366553915125506423
Short name T579
Test name
Test status
Simulation time 22372583 ps
CPU time 0.98 seconds
Started Oct 18 01:30:23 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 222900 kb
Host smart-7ae1e0fd-655e-4c70-8c0f-c586504b8bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12289785729850847854476505088837106362319288711686162458199366553915125506423 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.edn_intr.12289785729850847854476505088837106362319288711686162458199366553915125506423
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.61538882006756597395998391000652439211088820080056275558849714770429695074529
Short name T713
Test name
Test status
Simulation time 21768426 ps
CPU time 0.89 seconds
Started Oct 18 01:30:53 PM PDT 23
Finished Oct 18 01:30:54 PM PDT 23
Peak memory 205664 kb
Host smart-215d5aa9-fcf0-4ea9-a31d-ed19d813e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61538882006756597395998391000652439211088820080056275558849714770429695074529 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_smoke.61538882006756597395998391000652439211088820080056275558849714770429695074529
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.32821910649543452013624826109343097767589073336314322906449816197523514267474
Short name T72
Test name
Test status
Simulation time 299451483 ps
CPU time 3.59 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 206448 kb
Host smart-f46ebfff-733a-4eb8-87a8-bccd23b70cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32821910649543452013624826109343097767589073336314322906449816197523514267474 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.32821910649543452013624826109343097767589073336314322906449816197523514267474
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.79378526376044172071891280280096925827641282842695515634712782955329414499087
Short name T452
Test name
Test status
Simulation time 86880545330 ps
CPU time 1109.5 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:49:06 PM PDT 23
Peak memory 218760 kb
Host smart-5e483d99-43bc-4a67-a616-e55e54369587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793785263760441720718912802
80096925827641282842695515634712782955329414499087 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.79378526376
044172071891280280096925827641282842695515634712782955329414499087
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.18052583602371475735766470614625621621932831727032073618977841344058703529894
Short name T542
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:43 PM PDT 23
Peak memory 206008 kb
Host smart-d9b20095-5737-4386-931d-71ce6cbd8e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18052583602371475735766470614625621621932831727032073618977841344058703529894 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_alert.18052583602371475735766470614625621621932831727032073618977841344058703529894
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.82791634907509903615993367432773132204539181534225819509904439743314226103954
Short name T152
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 205952 kb
Host smart-a0704693-e380-4737-8296-017e63797d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82791634907509903615993367432773132204539181534225819509904439743314226103954 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_alert_test.82791634907509903615993367432773132204539181534225819509904439743314226103954
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.90177173512998952723738639624320893121611198295024890753739683167591448806528
Short name T45
Test name
Test status
Simulation time 19976788 ps
CPU time 0.85 seconds
Started Oct 18 01:30:33 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 215140 kb
Host smart-80d75208-ae71-4c49-a97b-5e6b054f90a4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90177173512998952723738639624320893121611198295024890753739683167591448806528 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.edn_disable.90177173512998952723738639624320893121611198295024890753739683167591448806528
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.80989252602546084413329359034284252157408755611605096628192479626162263722844
Short name T353
Test name
Test status
Simulation time 30622451 ps
CPU time 0.99 seconds
Started Oct 18 01:30:55 PM PDT 23
Finished Oct 18 01:30:56 PM PDT 23
Peak memory 215216 kb
Host smart-961d62a1-31ee-4a67-b5e1-e08946f4d42c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80989252602546084413329359034284252157408755611605096628192479626162263722844 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.8098925260254608441332935903428425215740875561160509662819
2479626162263722844
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.86390088834934687813467910753879072421140739194217932811831698547269260320016
Short name T500
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:50 PM PDT 23
Finished Oct 18 01:30:51 PM PDT 23
Peak memory 215316 kb
Host smart-bf8ba1e3-1e61-4b4a-932c-c1bb48aae255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86390088834934687813467910753879072421140739194217932811831698547269260320016 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.edn_err.86390088834934687813467910753879072421140739194217932811831698547269260320016
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.54097749595406063294299440674631994226177463710216484914255195760973863435065
Short name T128
Test name
Test status
Simulation time 22643412 ps
CPU time 0.94 seconds
Started Oct 18 01:30:43 PM PDT 23
Finished Oct 18 01:30:44 PM PDT 23
Peak memory 205744 kb
Host smart-2c7318d8-fc9a-4d3a-9a20-980cab9d1f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54097749595406063294299440674631994226177463710216484914255195760973863435065 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.edn_genbits.54097749595406063294299440674631994226177463710216484914255195760973863435065
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.45748508385284725000316357793933360878455055101978935803672632464152454183448
Short name T433
Test name
Test status
Simulation time 22372583 ps
CPU time 0.98 seconds
Started Oct 18 01:30:41 PM PDT 23
Finished Oct 18 01:30:42 PM PDT 23
Peak memory 222868 kb
Host smart-4f3bcd9d-34fe-47c7-8ea5-7b179c31f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45748508385284725000316357793933360878455055101978935803672632464152454183448 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.edn_intr.45748508385284725000316357793933360878455055101978935803672632464152454183448
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.68284555676149241170080036657804549049829541927218848175314768981328267398855
Short name T365
Test name
Test status
Simulation time 21768426 ps
CPU time 0.89 seconds
Started Oct 18 01:30:20 PM PDT 23
Finished Oct 18 01:30:22 PM PDT 23
Peak memory 205648 kb
Host smart-ddb2e0fb-3c15-48da-9f21-60e5e9707fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68284555676149241170080036657804549049829541927218848175314768981328267398855 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_smoke.68284555676149241170080036657804549049829541927218848175314768981328267398855
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.50676800606146102391344787264706670104860779296595791518707828254101617874642
Short name T357
Test name
Test status
Simulation time 299451483 ps
CPU time 3.56 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:25 PM PDT 23
Peak memory 206532 kb
Host smart-9cfbe201-850e-47b6-b81a-b618f845ff19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50676800606146102391344787264706670104860779296595791518707828254101617874642 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.50676800606146102391344787264706670104860779296595791518707828254101617874642
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.16184026114571091279168427621617546396202658225088605356162550504210438861150
Short name T597
Test name
Test status
Simulation time 86880545330 ps
CPU time 1106.01 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:49:31 PM PDT 23
Peak memory 218580 kb
Host smart-ad14bddd-736d-45d6-8f3e-a36f54228d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161840261145710912791684276
21617546396202658225088605356162550504210438861150 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.16184026114
571091279168427621617546396202658225088605356162550504210438861150
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.52529879220513662730766268634728317159895755380324933757231507922914661480138
Short name T492
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:30:32 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 205844 kb
Host smart-b5029821-b1e8-4414-83cf-086570ca06e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52529879220513662730766268634728317159895755380324933757231507922914661480138 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_alert.52529879220513662730766268634728317159895755380324933757231507922914661480138
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.51844893688810009973164250554535471888559943841395466134821324238186345867265
Short name T663
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 206032 kb
Host smart-19a444c4-9467-4bf2-9e65-02b1eafe884b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51844893688810009973164250554535471888559943841395466134821324238186345867265 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_alert_test.51844893688810009973164250554535471888559943841395466134821324238186345867265
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.62178428495028138165660631582749059896662055077028701448330384534382329672043
Short name T63
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:31:03 PM PDT 23
Peak memory 215108 kb
Host smart-1d3dd063-5994-44ca-b86f-41ae68aa74d6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62178428495028138165660631582749059896662055077028701448330384534382329672043 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.edn_disable.62178428495028138165660631582749059896662055077028701448330384534382329672043
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.80181097221287295300898489110621568173131789996764446748094387147273554608724
Short name T697
Test name
Test status
Simulation time 30622451 ps
CPU time 1.05 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 215300 kb
Host smart-c1bcbbd9-9b6c-4d39-bb64-7532762f29b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80181097221287295300898489110621568173131789996764446748094387147273554608724 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.8018109722128729530089848911062156817313178999676444674809
4387147273554608724
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.107127381706130178093235241791099382370836544880137730166236152184548601304030
Short name T137
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:31:04 PM PDT 23
Peak memory 215228 kb
Host smart-6d05e6df-7ee3-4852-ac87-ec9a1e04b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107127381706130178093235241791099382370836544880137730166236152184548601304030 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.edn_err.107127381706130178093235241791099382370836544880137730166236152184548601304030
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.26449016072276866644473692815368813376749503297725420236392586009106405919285
Short name T419
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:58 PM PDT 23
Peak memory 205736 kb
Host smart-6220d030-5aac-410d-a45d-c9a6abb8f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26449016072276866644473692815368813376749503297725420236392586009106405919285 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.edn_genbits.26449016072276866644473692815368813376749503297725420236392586009106405919285
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.78165339187610748008051778308754150532903493425395854333296861531799446058084
Short name T489
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 222916 kb
Host smart-fb65fe53-07e2-49d6-8f16-6885bcf38372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78165339187610748008051778308754150532903493425395854333296861531799446058084 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.edn_intr.78165339187610748008051778308754150532903493425395854333296861531799446058084
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.46137913054484526537695995609778857705958586774126704523209253416067286938566
Short name T527
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:30:43 PM PDT 23
Finished Oct 18 01:30:44 PM PDT 23
Peak memory 205620 kb
Host smart-0a96ca99-c421-442d-9ca0-4e85d69fe611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46137913054484526537695995609778857705958586774126704523209253416067286938566 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_smoke.46137913054484526537695995609778857705958586774126704523209253416067286938566
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.44232282052886977080912922266607836038480416665014087264215796524428679160657
Short name T139
Test name
Test status
Simulation time 299451483 ps
CPU time 3.59 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 206484 kb
Host smart-1ebd1264-0eae-440a-bac6-7d8e57fbafda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44232282052886977080912922266607836038480416665014087264215796524428679160657 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.44232282052886977080912922266607836038480416665014087264215796524428679160657
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.8385299294296438572570615949956945129393401576904870568506841101226965362016
Short name T431
Test name
Test status
Simulation time 86880545330 ps
CPU time 1084.12 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:49:03 PM PDT 23
Peak memory 218504 kb
Host smart-217f2460-9977-4e37-b420-c5438420fd39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838529929429643857257061594
9956945129393401576904870568506841101226965362016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.838529929429
6438572570615949956945129393401576904870568506841101226965362016
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.91614650510074671140190775858102293294388639719627098715766639166606080836916
Short name T405
Test name
Test status
Simulation time 32330757 ps
CPU time 0.98 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 205956 kb
Host smart-e4bff5d1-8e4b-4be4-b34b-1b247a63c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91614650510074671140190775858102293294388639719627098715766639166606080836916 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.edn_alert.91614650510074671140190775858102293294388639719627098715766639166606080836916
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.23099737262721205991223243520254053504617814808112802269413615376920732221458
Short name T41
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:30:31 PM PDT 23
Finished Oct 18 01:30:33 PM PDT 23
Peak memory 205912 kb
Host smart-3cc80e7c-2845-4b08-9c60-03ff322782f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099737262721205991223243520254053504617814808112802269413615376920732221458 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_alert_test.23099737262721205991223243520254053504617814808112802269413615376920732221458
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.71273362716387355477353656519601250967080756664698261922098746326939340839880
Short name T599
Test name
Test status
Simulation time 19976788 ps
CPU time 0.81 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 215060 kb
Host smart-6d343070-d28e-4fc7-af80-1ee4e2eb24f7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71273362716387355477353656519601250967080756664698261922098746326939340839880 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.edn_disable.71273362716387355477353656519601250967080756664698261922098746326939340839880
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.107685832655549172007367495187106941847660403454609663616691513118315210197767
Short name T708
Test name
Test status
Simulation time 30622451 ps
CPU time 0.88 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 215240 kb
Host smart-c76d3087-8bac-4812-beec-e7c9903bb3ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107685832655549172007367495187106941847660403454609663616691513118315210197767 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.107685832655549172007367495187106941847660403454609663616
691513118315210197767
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.49416547098479904609980316015483256865243634473273768102124651048058545469735
Short name T13
Test name
Test status
Simulation time 29871889 ps
CPU time 0.97 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:26 PM PDT 23
Peak memory 215292 kb
Host smart-bbc2c11f-60f4-447a-aebc-42fc2aeccdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49416547098479904609980316015483256865243634473273768102124651048058545469735 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.edn_err.49416547098479904609980316015483256865243634473273768102124651048058545469735
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.43399280448885003992954560124897409210469457092386746798393456565835712668768
Short name T397
Test name
Test status
Simulation time 22643412 ps
CPU time 1 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 205816 kb
Host smart-df6ce6b1-4a97-4ba0-a86f-5b9a363ca2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43399280448885003992954560124897409210469457092386746798393456565835712668768 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.edn_genbits.43399280448885003992954560124897409210469457092386746798393456565835712668768
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.64995013391421583789727267723564369283383275372051223100433156209683392191530
Short name T714
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:31:04 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 222804 kb
Host smart-9dc0f788-b688-4a0a-858c-19393558d420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64995013391421583789727267723564369283383275372051223100433156209683392191530 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.edn_intr.64995013391421583789727267723564369283383275372051223100433156209683392191530
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.61490735117050654178697621374943025872515335186763083951590808933944504569063
Short name T47
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:30:49 PM PDT 23
Finished Oct 18 01:30:50 PM PDT 23
Peak memory 205676 kb
Host smart-f16f2c06-8af5-4979-b31d-1bea9d258764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61490735117050654178697621374943025872515335186763083951590808933944504569063 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.edn_smoke.61490735117050654178697621374943025872515335186763083951590808933944504569063
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.112368891633495442022363664027191723332281589655016169911252736924610748950792
Short name T654
Test name
Test status
Simulation time 299451483 ps
CPU time 3.59 seconds
Started Oct 18 01:31:31 PM PDT 23
Finished Oct 18 01:31:35 PM PDT 23
Peak memory 206436 kb
Host smart-92210002-b6a1-4de6-a70a-cb5cde9ef3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112368891633495442022363664027191723332281589655016169911252736924610748950792 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.112368891633495442022363664027191723332281589655016169911252736924610748950792
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3113651149110807304344292084356911813939807056919913829004954649488408748758
Short name T143
Test name
Test status
Simulation time 86880545330 ps
CPU time 1108.91 seconds
Started Oct 18 01:31:08 PM PDT 23
Finished Oct 18 01:49:38 PM PDT 23
Peak memory 218560 kb
Host smart-3b7d706e-7b3e-4753-94a3-a0216ffa94b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311365114911080730434429208
4356911813939807056919913829004954649488408748758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.311365114911
0807304344292084356911813939807056919913829004954649488408748758
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.45196084512235063071769480072980050126038730772598403617610018974295761037440
Short name T130
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:57 PM PDT 23
Finished Oct 18 01:30:58 PM PDT 23
Peak memory 205976 kb
Host smart-a19c7b1a-f5d2-4c55-9795-f1e9bd39bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45196084512235063071769480072980050126038730772598403617610018974295761037440 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_alert.45196084512235063071769480072980050126038730772598403617610018974295761037440
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.94341922966113349347041491602272542292250628314610354996030267792444322807325
Short name T642
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:31:00 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 205976 kb
Host smart-19e6a8fd-8d3d-4d06-967b-e857bd13d51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94341922966113349347041491602272542292250628314610354996030267792444322807325 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_alert_test.94341922966113349347041491602272542292250628314610354996030267792444322807325
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.75188067569874785587072405484393277279918385842147618198885605136897721005557
Short name T175
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 215160 kb
Host smart-b08c74c8-46c8-455c-98b3-e73b27808a34
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75188067569874785587072405484393277279918385842147618198885605136897721005557 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.edn_disable.75188067569874785587072405484393277279918385842147618198885605136897721005557
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3397126262041619428521371454132380557639462304020026834697910263949457369135
Short name T529
Test name
Test status
Simulation time 30622451 ps
CPU time 0.91 seconds
Started Oct 18 01:30:55 PM PDT 23
Finished Oct 18 01:30:56 PM PDT 23
Peak memory 215232 kb
Host smart-cec3aad8-3e1c-42b0-9491-04f1f1e54249
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397126262041619428521371454132380557639462304020026834697910263949457369135 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.33971262620416194285213714541323805576394623040200268346979
10263949457369135
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.109962849598366737179642137325596848893707234655521868304443738518923755516765
Short name T169
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 215296 kb
Host smart-4d1b1086-ba87-49a4-ab08-0c6e64560426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109962849598366737179642137325596848893707234655521868304443738518923755516765 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.edn_err.109962849598366737179642137325596848893707234655521868304443738518923755516765
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.115614702003574279853686944128893173158438577174801415359813138611869918747946
Short name T583
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:30:21 PM PDT 23
Finished Oct 18 01:30:23 PM PDT 23
Peak memory 205528 kb
Host smart-7e84aab9-5b0f-4235-ad24-55568e0052e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115614702003574279853686944128893173158438577174801415359813138611869918747946 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.edn_genbits.115614702003574279853686944128893173158438577174801415359813138611869918747946
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.865218254695954518687939317274767628313141991512680287280781381575732185536
Short name T35
Test name
Test status
Simulation time 22372583 ps
CPU time 1.04 seconds
Started Oct 18 01:30:17 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 222904 kb
Host smart-94032ce3-8c06-4273-a0bb-dbcd53ac9b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865218254695954518687939317274767628313141991512680287280781381575732185536 -assert nopostproc +UVM_TESTNAME=edn_intr_te
st +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.edn_intr.865218254695954518687939317274767628313141991512680287280781381575732185536
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.65466431590337960388322618629083660794072175663575263941366240293387900957251
Short name T387
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 205648 kb
Host smart-ecde9242-3a92-4e9c-8ba0-65a5d1d31aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65466431590337960388322618629083660794072175663575263941366240293387900957251 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_smoke.65466431590337960388322618629083660794072175663575263941366240293387900957251
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.98338641485078222342709415802462339212459394049348726756467967986749879866774
Short name T700
Test name
Test status
Simulation time 299451483 ps
CPU time 3.72 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 206472 kb
Host smart-600b4027-fb16-4b32-9c18-7d3d21d35640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98338641485078222342709415802462339212459394049348726756467967986749879866774 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.98338641485078222342709415802462339212459394049348726756467967986749879866774
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.70675861140472779308563806381804789451012588760426043532148404124013435905845
Short name T606
Test name
Test status
Simulation time 86880545330 ps
CPU time 1091.72 seconds
Started Oct 18 01:30:24 PM PDT 23
Finished Oct 18 01:48:37 PM PDT 23
Peak memory 218608 kb
Host smart-98e76075-c10e-4d6c-b5a3-af7317d9fa19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706758611404727793085638063
81804789451012588760426043532148404124013435905845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.70675861140
472779308563806381804789451012588760426043532148404124013435905845
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.30006360008763086655597892004769420518764469055263247961654682257794190787153
Short name T354
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:30:18 PM PDT 23
Finished Oct 18 01:30:19 PM PDT 23
Peak memory 205964 kb
Host smart-8df1286a-8209-4514-8465-965c14b130db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30006360008763086655597892004769420518764469055263247961654682257794190787153 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.edn_alert.30006360008763086655597892004769420518764469055263247961654682257794190787153
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.31131637971016000865025270136813573800605646781388703196802649948240300564932
Short name T728
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:41 PM PDT 23
Finished Oct 18 01:30:42 PM PDT 23
Peak memory 205996 kb
Host smart-0ba527e5-1dbd-49e5-a382-1d6c2fcf3e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31131637971016000865025270136813573800605646781388703196802649948240300564932 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_alert_test.31131637971016000865025270136813573800605646781388703196802649948240300564932
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.109470347396332260719350337405921594188859920741775766941651428731939607763458
Short name T665
Test name
Test status
Simulation time 19976788 ps
CPU time 0.85 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:31:00 PM PDT 23
Peak memory 215116 kb
Host smart-90948215-b6d9-4f39-9ced-4d927a8a4129
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109470347396332260719350337405921594188859920741775766941651428731939607763458 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.edn_disable.109470347396332260719350337405921594188859920741775766941651428731939607763458
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.109153044230527856638435522963416415120080114430332965503836453667391217269023
Short name T538
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 215160 kb
Host smart-24491573-514a-4bb2-810a-4ca63a5282fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109153044230527856638435522963416415120080114430332965503836453667391217269023 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.109153044230527856638435522963416415120080114430332965503
836453667391217269023
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.83131487214034154792677857337244344118275741059853790810759935001069379734847
Short name T402
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 215244 kb
Host smart-b9321f9b-7736-4fa1-b2f1-1f9335f6fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83131487214034154792677857337244344118275741059853790810759935001069379734847 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.edn_err.83131487214034154792677857337244344118275741059853790810759935001069379734847
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.96343351274312325035880201658834280259689668488313016540420472399594912577719
Short name T537
Test name
Test status
Simulation time 22643412 ps
CPU time 0.93 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 205732 kb
Host smart-506ddfed-6b00-46e3-b951-ee2b62d88550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96343351274312325035880201658834280259689668488313016540420472399594912577719 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.edn_genbits.96343351274312325035880201658834280259689668488313016540420472399594912577719
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.77411296101437067768532485516495827819624764971827089675981409247527671507963
Short name T487
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:31 PM PDT 23
Peak memory 222860 kb
Host smart-aecc6386-f980-479a-86d4-3f99bff7cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77411296101437067768532485516495827819624764971827089675981409247527671507963 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.edn_intr.77411296101437067768532485516495827819624764971827089675981409247527671507963
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.16397778525279388417186570389229788923561509871176888812053563770237134558679
Short name T680
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 205648 kb
Host smart-878ce971-0c53-4fb0-9489-1832e5781be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16397778525279388417186570389229788923561509871176888812053563770237134558679 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.edn_smoke.16397778525279388417186570389229788923561509871176888812053563770237134558679
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.114574940412529734926043770971692328497891287800346226102126677507524043327641
Short name T138
Test name
Test status
Simulation time 299451483 ps
CPU time 3.62 seconds
Started Oct 18 01:30:35 PM PDT 23
Finished Oct 18 01:30:39 PM PDT 23
Peak memory 206520 kb
Host smart-73a48823-7638-41ed-9d70-192255560b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114574940412529734926043770971692328497891287800346226102126677507524043327641 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.114574940412529734926043770971692328497891287800346226102126677507524043327641
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.57479407361476706145964908252569683038899159480331963987364533064789964470783
Short name T382
Test name
Test status
Simulation time 86880545330 ps
CPU time 1133.76 seconds
Started Oct 18 01:30:51 PM PDT 23
Finished Oct 18 01:49:46 PM PDT 23
Peak memory 218628 kb
Host smart-dcaee41f-ad23-46bf-a6ce-5dddddaaa71e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574794073614767061459649082
52569683038899159480331963987364533064789964470783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.57479407361
476706145964908252569683038899159480331963987364533064789964470783
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.50541414030394270357259161152900395254075619849802794363667533541794708611484
Short name T508
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 205936 kb
Host smart-ca8f026d-ca52-4d73-a8af-c653fe443982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50541414030394270357259161152900395254075619849802794363667533541794708611484 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.edn_alert.50541414030394270357259161152900395254075619849802794363667533541794708611484
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.82896667270020164525086781552360195492496896046663414642086547818361989208910
Short name T474
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 205940 kb
Host smart-0cff8f97-bb6b-442f-a741-d33a8ae5d46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82896667270020164525086781552360195492496896046663414642086547818361989208910 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_alert_test.82896667270020164525086781552360195492496896046663414642086547818361989208910
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.72121152461023115051628628092978611571659868086605306439275171145603359437532
Short name T434
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:29:45 PM PDT 23
Finished Oct 18 01:29:46 PM PDT 23
Peak memory 215128 kb
Host smart-a7244739-3d5e-432a-b7ce-54dd3dc4d90b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72121152461023115051628628092978611571659868086605306439275171145603359437532 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_disable.72121152461023115051628628092978611571659868086605306439275171145603359437532
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.22368589477902122344748293825921097115668379632144683115204111971018102138252
Short name T572
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:29:51 PM PDT 23
Peak memory 215268 kb
Host smart-0965b237-01f4-4054-88d0-8d282ac909a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22368589477902122344748293825921097115668379632144683115204111971018102138252 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.22368589477902122344748293825921097115668379632144683115204
111971018102138252
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.78384688268032144375800193098508736139546898808681859971560312356398233211276
Short name T408
Test name
Test status
Simulation time 29871889 ps
CPU time 0.86 seconds
Started Oct 18 01:30:01 PM PDT 23
Finished Oct 18 01:30:02 PM PDT 23
Peak memory 215132 kb
Host smart-bb8de4d3-ec2e-41d6-a0a1-c018bb69d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78384688268032144375800193098508736139546898808681859971560312356398233211276 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
edn_err.78384688268032144375800193098508736139546898808681859971560312356398233211276
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.95410652365375214590347270493539449806156619838450906577827855820066524400079
Short name T648
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:29:34 PM PDT 23
Finished Oct 18 01:29:41 PM PDT 23
Peak memory 205788 kb
Host smart-3b518560-9504-4936-b4c0-8d0eb1bd17ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95410652365375214590347270493539449806156619838450906577827855820066524400079 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.edn_genbits.95410652365375214590347270493539449806156619838450906577827855820066524400079
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.110976158173834774518177566148719066567921490713806762919683281705370878812454
Short name T164
Test name
Test status
Simulation time 22372583 ps
CPU time 1 seconds
Started Oct 18 01:30:45 PM PDT 23
Finished Oct 18 01:30:47 PM PDT 23
Peak memory 222928 kb
Host smart-7c6c7a97-3d18-4e52-ad90-e0443cb0b3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110976158173834774518177566148719066567921490713806762919683281705370878812454 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.edn_intr.110976158173834774518177566148719066567921490713806762919683281705370878812454
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.76713470340704302608987533548307785541888293015097016496820622640447889057066
Short name T689
Test name
Test status
Simulation time 19018470 ps
CPU time 0.85 seconds
Started Oct 18 01:29:42 PM PDT 23
Finished Oct 18 01:29:44 PM PDT 23
Peak memory 205552 kb
Host smart-32716949-5997-4edf-8b1a-37d53ffcb631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76713470340704302608987533548307785541888293015097016496820622640447889057066 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.edn_regwen.76713470340704302608987533548307785541888293015097016496820622640447889057066
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.78703351626391858916925442505818593283024643026843491116652828086077084413890
Short name T38
Test name
Test status
Simulation time 359808016 ps
CPU time 6.12 seconds
Started Oct 18 01:30:29 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 235484 kb
Host smart-28a15923-4def-4095-933d-82c138db20c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78703351626391858916925442505818593283024643026843491116652828086077084413890 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_sec_cm.78703351626391858916925442505818593283024643026843491116652828086077084413890
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.50638125566328909137141859910755674384656779058715537097129206034194387333728
Short name T550
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:29:36 PM PDT 23
Finished Oct 18 01:29:37 PM PDT 23
Peak memory 205648 kb
Host smart-9bb98462-d658-4698-83fd-f7a141c5e0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50638125566328909137141859910755674384656779058715537097129206034194387333728 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.edn_smoke.50638125566328909137141859910755674384656779058715537097129206034194387333728
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.89606403682265194582296248896760782121996227036533251546262886560188433640316
Short name T407
Test name
Test status
Simulation time 299451483 ps
CPU time 3.62 seconds
Started Oct 18 01:29:30 PM PDT 23
Finished Oct 18 01:29:34 PM PDT 23
Peak memory 206536 kb
Host smart-f4433fb8-c745-4436-ab62-953c3cfec193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89606403682265194582296248896760782121996227036533251546262886560188433640316 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.89606403682265194582296248896760782121996227036533251546262886560188433640316
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.110437543705152558204586508397179445378822472611871104584350066409507590354805
Short name T421
Test name
Test status
Simulation time 86880545330 ps
CPU time 1066.42 seconds
Started Oct 18 01:29:43 PM PDT 23
Finished Oct 18 01:47:30 PM PDT 23
Peak memory 218692 kb
Host smart-807c34c4-093d-4986-a955-1ba3b9e90ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110437543705152558204586508
397179445378822472611871104584350066409507590354805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.11043754370
5152558204586508397179445378822472611871104584350066409507590354805
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.42142380945177247498095838778327918445441853832169016141071732140071905353644
Short name T646
Test name
Test status
Simulation time 32330757 ps
CPU time 0.99 seconds
Started Oct 18 01:31:04 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 206008 kb
Host smart-50b49435-dadd-4b48-bbdb-520f07c69977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42142380945177247498095838778327918445441853832169016141071732140071905353644 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_alert.42142380945177247498095838778327918445441853832169016141071732140071905353644
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2929807975627162649947490822635527478253155585580193196324352312890275717350
Short name T495
Test name
Test status
Simulation time 16111390 ps
CPU time 0.94 seconds
Started Oct 18 01:31:05 PM PDT 23
Finished Oct 18 01:31:07 PM PDT 23
Peak memory 205932 kb
Host smart-432954ae-a2b1-493c-96df-e173a31f631a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929807975627162649947490822635527478253155585580193196324352312890275717350 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_alert_test.2929807975627162649947490822635527478253155585580193196324352312890275717350
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.38447237170146424542466788938563167537752433703219153229089396138027127612434
Short name T499
Test name
Test status
Simulation time 19976788 ps
CPU time 0.81 seconds
Started Oct 18 01:31:04 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 215096 kb
Host smart-ceb103a9-bb65-42c0-b8b9-74a07282d3d0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38447237170146424542466788938563167537752433703219153229089396138027127612434 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.edn_disable.38447237170146424542466788938563167537752433703219153229089396138027127612434
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.23712154858361738796988883141760631132794589778332075891991627241235968419397
Short name T448
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:49 PM PDT 23
Peak memory 215128 kb
Host smart-8f562013-d015-4a63-bc1c-d2074eaefc55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712154858361738796988883141760631132794589778332075891991627241235968419397 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.2371215485836173879698888314176063113279458977833207589199
1627241235968419397
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.73674624220805122200670550067068078312004987877836262478516089347988802954255
Short name T344
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 215152 kb
Host smart-6720e9ea-29fc-49d3-b423-e0e888b42a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73674624220805122200670550067068078312004987877836262478516089347988802954255 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.edn_err.73674624220805122200670550067068078312004987877836262478516089347988802954255
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.14316500202199142808553979325288834264928547692400908886285293116188466394151
Short name T587
Test name
Test status
Simulation time 22643412 ps
CPU time 0.91 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 205756 kb
Host smart-57c9c154-d58b-4393-8a26-b396466294fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14316500202199142808553979325288834264928547692400908886285293116188466394151 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.edn_genbits.14316500202199142808553979325288834264928547692400908886285293116188466394151
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.68967281522062081729899022130290287599841398652016472241065756648658859510250
Short name T196
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:57 PM PDT 23
Peak memory 222892 kb
Host smart-5a9f6193-d6cd-46ab-be66-b768ef784108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68967281522062081729899022130290287599841398652016472241065756648658859510250 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.edn_intr.68967281522062081729899022130290287599841398652016472241065756648658859510250
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.80908033650377240187417621947034318112777486717373909908409818464360403187289
Short name T141
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 205692 kb
Host smart-95259713-3789-46bb-af98-e28d281eb0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80908033650377240187417621947034318112777486717373909908409818464360403187289 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_smoke.80908033650377240187417621947034318112777486717373909908409818464360403187289
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.77305312259297581400707428850551596677867846374761933189900082157507500824386
Short name T76
Test name
Test status
Simulation time 299451483 ps
CPU time 3.53 seconds
Started Oct 18 01:31:20 PM PDT 23
Finished Oct 18 01:31:24 PM PDT 23
Peak memory 206524 kb
Host smart-49f2ec2a-f5fc-4629-917e-8834560bea57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77305312259297581400707428850551596677867846374761933189900082157507500824386 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.77305312259297581400707428850551596677867846374761933189900082157507500824386
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.97141274423595645043034246527782976302534564191989699822138877355141075328884
Short name T10
Test name
Test status
Simulation time 86880545330 ps
CPU time 1120.38 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:49:40 PM PDT 23
Peak memory 218660 kb
Host smart-ee24639d-6104-4f50-967c-f6b4cf37afe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971412744235956450430342465
27782976302534564191989699822138877355141075328884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.97141274423
595645043034246527782976302534564191989699822138877355141075328884
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.93152229623635567245264743706727127154585159059025954499421649307286037852786
Short name T670
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 205912 kb
Host smart-f72d2161-aa77-42ad-a9ad-c69b85746a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93152229623635567245264743706727127154585159059025954499421649307286037852786 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_alert.93152229623635567245264743706727127154585159059025954499421649307286037852786
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.35251442085033253937391355524156093099997331401941417115526985828524982176466
Short name T483
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 205988 kb
Host smart-d896aa07-8702-4da5-bfd3-ec757ece3bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35251442085033253937391355524156093099997331401941417115526985828524982176466 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_alert_test.35251442085033253937391355524156093099997331401941417115526985828524982176466
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.58590942083365995904517627692186934887706035637742002370445484978513490623931
Short name T467
Test name
Test status
Simulation time 19976788 ps
CPU time 0.84 seconds
Started Oct 18 01:30:54 PM PDT 23
Finished Oct 18 01:30:55 PM PDT 23
Peak memory 215116 kb
Host smart-6a572958-f0e3-4e38-af35-5e9ae5a3282d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58590942083365995904517627692186934887706035637742002370445484978513490623931 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.edn_disable.58590942083365995904517627692186934887706035637742002370445484978513490623931
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.65962823528896093080910549291133332260155549895351479740250988565782945325182
Short name T679
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:31:39 PM PDT 23
Finished Oct 18 01:31:41 PM PDT 23
Peak memory 215280 kb
Host smart-1a4456a8-aca9-45b2-afc0-e1657a75c673
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65962823528896093080910549291133332260155549895351479740250988565782945325182 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.6596282352889609308091054929113333226015554989535147974025
0988565782945325182
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.106585814766001767403657109792191245737852770864149833599563552072998451010697
Short name T717
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:17 PM PDT 23
Finished Oct 18 01:31:19 PM PDT 23
Peak memory 215300 kb
Host smart-fa8adba0-bd90-4cd8-83fa-a4a38c27b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106585814766001767403657109792191245737852770864149833599563552072998451010697 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.edn_err.106585814766001767403657109792191245737852770864149833599563552072998451010697
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.66858248483003541686165231035802928951609946163920263615026287723806562892851
Short name T404
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:31:14 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 205772 kb
Host smart-656a1ad3-266d-4eb0-adcd-64579a3f12b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66858248483003541686165231035802928951609946163920263615026287723806562892851 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.edn_genbits.66858248483003541686165231035802928951609946163920263615026287723806562892851
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3071022723696578292535513635545888831862670516782957732140566145424542029345
Short name T198
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 222916 kb
Host smart-0caa0a19-d839-45e9-9390-7e9d9cbd0629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071022723696578292535513635545888831862670516782957732140566145424542029345 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.edn_intr.3071022723696578292535513635545888831862670516782957732140566145424542029345
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.86429824927765990870523551825638905198071999566310252998527631584558111499389
Short name T395
Test name
Test status
Simulation time 21768426 ps
CPU time 0.83 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 205632 kb
Host smart-021046e3-2a09-44ba-afb8-5c1573034093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86429824927765990870523551825638905198071999566310252998527631584558111499389 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_smoke.86429824927765990870523551825638905198071999566310252998527631584558111499389
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.71083632191278250471485261048036832946907011618614195504225905181908087306154
Short name T430
Test name
Test status
Simulation time 299451483 ps
CPU time 3.54 seconds
Started Oct 18 01:30:59 PM PDT 23
Finished Oct 18 01:31:03 PM PDT 23
Peak memory 206420 kb
Host smart-47f58bb3-8179-4edd-859a-37a174561e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71083632191278250471485261048036832946907011618614195504225905181908087306154 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.71083632191278250471485261048036832946907011618614195504225905181908087306154
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.106052265085524989132179512196757924740897282233692959438378976743863258986813
Short name T363
Test name
Test status
Simulation time 86880545330 ps
CPU time 1102.64 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:49:25 PM PDT 23
Peak memory 218616 kb
Host smart-bd5f91bf-d3f8-45dd-ae36-7d4d3abb844a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106052265085524989132179512
196757924740897282233692959438378976743863258986813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1060522650
85524989132179512196757924740897282233692959438378976743863258986813
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.52960600795108685655481669196232922418783027835297860670638233256862754381930
Short name T578
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:31:19 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 205968 kb
Host smart-fefef1f6-ee10-4028-9f89-8824900238c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52960600795108685655481669196232922418783027835297860670638233256862754381930 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_alert.52960600795108685655481669196232922418783027835297860670638233256862754381930
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.67436165997683253435785306398432376147579215947753698259683970914402418738071
Short name T174
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 205908 kb
Host smart-ade3bbe4-3b8f-4c93-a5d5-387937785890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67436165997683253435785306398432376147579215947753698259683970914402418738071 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_alert_test.67436165997683253435785306398432376147579215947753698259683970914402418738071
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.83926100005918683702851305608681595359632822575102825806587195591736019229336
Short name T12
Test name
Test status
Simulation time 19976788 ps
CPU time 0.89 seconds
Started Oct 18 01:31:14 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 215136 kb
Host smart-030e8789-527b-4109-ac42-ebe80940d21b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83926100005918683702851305608681595359632822575102825806587195591736019229336 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.edn_disable.83926100005918683702851305608681595359632822575102825806587195591736019229336
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.23543515487593693664972151707605470071394863109894765318307966429954011401372
Short name T504
Test name
Test status
Simulation time 30622451 ps
CPU time 0.89 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:04 PM PDT 23
Peak memory 215112 kb
Host smart-b9591434-2658-4779-8518-44ef5ce2136b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23543515487593693664972151707605470071394863109894765318307966429954011401372 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2354351548759369366497215170760547007139486310989476531830
7966429954011401372
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.95740198700213363527103418582218693323501024038137224604550378512228160468355
Short name T625
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:14 PM PDT 23
Finished Oct 18 01:31:15 PM PDT 23
Peak memory 215288 kb
Host smart-0db5b18f-19d7-4bb1-8cc7-c5c56b8d1b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95740198700213363527103418582218693323501024038137224604550378512228160468355 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.edn_err.95740198700213363527103418582218693323501024038137224604550378512228160468355
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.70522964752630495486976060987980640823385694805164974259004107352980560737013
Short name T349
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:31:14 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 205636 kb
Host smart-97324892-7cdc-4b67-af7a-5795f9f9ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70522964752630495486976060987980640823385694805164974259004107352980560737013 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.edn_genbits.70522964752630495486976060987980640823385694805164974259004107352980560737013
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.59535919802328676565848785898372734137591909447162060794146131827523279607939
Short name T471
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:31:12 PM PDT 23
Peak memory 222920 kb
Host smart-6009c024-a7a6-4643-a91b-71e1bcabe108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59535919802328676565848785898372734137591909447162060794146131827523279607939 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.edn_intr.59535919802328676565848785898372734137591909447162060794146131827523279607939
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.29682587323116293552645512161705328454045871726237128214820755072927442468860
Short name T337
Test name
Test status
Simulation time 21768426 ps
CPU time 0.89 seconds
Started Oct 18 01:30:40 PM PDT 23
Finished Oct 18 01:30:42 PM PDT 23
Peak memory 204660 kb
Host smart-637955c7-40f6-4cfe-8ca8-375808cc1aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29682587323116293552645512161705328454045871726237128214820755072927442468860 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_smoke.29682587323116293552645512161705328454045871726237128214820755072927442468860
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.78402111606672322585163054857913947476163515700401437359267154557333467524918
Short name T439
Test name
Test status
Simulation time 299451483 ps
CPU time 3.54 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 206524 kb
Host smart-6c2498e7-60e4-4ef7-9cc0-731e8418fa92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78402111606672322585163054857913947476163515700401437359267154557333467524918 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.78402111606672322585163054857913947476163515700401437359267154557333467524918
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.39390354822323947879999683817893591801957813034621283297742578824317537728899
Short name T355
Test name
Test status
Simulation time 86880545330 ps
CPU time 1130.03 seconds
Started Oct 18 01:31:34 PM PDT 23
Finished Oct 18 01:50:25 PM PDT 23
Peak memory 218644 kb
Host smart-d211756f-6de7-4424-85e6-d70f7073694f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393903548223239478799996838
17893591801957813034621283297742578824317537728899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.39390354822
323947879999683817893591801957813034621283297742578824317537728899
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.90116091249900599250407444282608691056414474998028861814792394432204885576086
Short name T505
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 206012 kb
Host smart-294fd659-e345-4263-b880-2b8d4cd12fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90116091249900599250407444282608691056414474998028861814792394432204885576086 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_alert.90116091249900599250407444282608691056414474998028861814792394432204885576086
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.37894240514196871792899619291495347038420034857585642019666316239414643433246
Short name T519
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:31:08 PM PDT 23
Finished Oct 18 01:31:10 PM PDT 23
Peak memory 205996 kb
Host smart-a895a9cb-21d8-454b-8ee8-5cec76cb6ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37894240514196871792899619291495347038420034857585642019666316239414643433246 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_alert_test.37894240514196871792899619291495347038420034857585642019666316239414643433246
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.47274132182009552384235003920304463229123295154760145080655938446713451472181
Short name T442
Test name
Test status
Simulation time 19976788 ps
CPU time 0.88 seconds
Started Oct 18 01:31:17 PM PDT 23
Finished Oct 18 01:31:19 PM PDT 23
Peak memory 215092 kb
Host smart-b4870544-1ca0-4d47-869f-59946ef4bb07
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47274132182009552384235003920304463229123295154760145080655938446713451472181 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.edn_disable.47274132182009552384235003920304463229123295154760145080655938446713451472181
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.82779877247835986636252357259018466722338279184725031222253053676481095522337
Short name T472
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:31:19 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 215276 kb
Host smart-eb57dbcc-979a-457a-9850-d4ff34395c92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82779877247835986636252357259018466722338279184725031222253053676481095522337 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.8277987724783598663625235725901846672233827918472503122225
3053676481095522337
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.105320281804513595598297277214657133564008421429405481142761629333966799254087
Short name T343
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:20 PM PDT 23
Finished Oct 18 01:31:21 PM PDT 23
Peak memory 215196 kb
Host smart-bedaeab9-cfa5-4fac-82d7-4ca082732e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105320281804513595598297277214657133564008421429405481142761629333966799254087 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.edn_err.105320281804513595598297277214657133564008421429405481142761629333966799254087
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.32585081563730040621347838719648861552695158423942003307559569524478674185684
Short name T640
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 205680 kb
Host smart-b9492009-5c61-4a20-ae4b-e155ac92ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32585081563730040621347838719648861552695158423942003307559569524478674185684 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.edn_genbits.32585081563730040621347838719648861552695158423942003307559569524478674185684
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.98172836888526896084705897190670500730964204695307890776195091028986359823219
Short name T426
Test name
Test status
Simulation time 22372583 ps
CPU time 1.01 seconds
Started Oct 18 01:31:24 PM PDT 23
Finished Oct 18 01:31:25 PM PDT 23
Peak memory 222864 kb
Host smart-9a68aa2a-18f5-4aea-a39f-79e5d9d4c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98172836888526896084705897190670500730964204695307890776195091028986359823219 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.edn_intr.98172836888526896084705897190670500730964204695307890776195091028986359823219
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.49121418993083394103454658182514803867212311816649358412306335518310740855764
Short name T637
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:31:08 PM PDT 23
Finished Oct 18 01:31:09 PM PDT 23
Peak memory 205656 kb
Host smart-b83680bd-06c2-4e1e-8be6-2d2ecbd70f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49121418993083394103454658182514803867212311816649358412306335518310740855764 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_smoke.49121418993083394103454658182514803867212311816649358412306335518310740855764
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.98277270377169499346232752814485494149736570924602647322015627722701850272265
Short name T558
Test name
Test status
Simulation time 299451483 ps
CPU time 3.66 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 206448 kb
Host smart-f3620cae-8771-43cf-a2ff-78638ce92158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98277270377169499346232752814485494149736570924602647322015627722701850272265 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.98277270377169499346232752814485494149736570924602647322015627722701850272265
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.35571474679835742097739318509607986951994671910079615350826991136717929371869
Short name T5
Test name
Test status
Simulation time 86880545330 ps
CPU time 1081.31 seconds
Started Oct 18 01:31:23 PM PDT 23
Finished Oct 18 01:49:25 PM PDT 23
Peak memory 218680 kb
Host smart-e0a88a6b-a597-4130-b4d3-cbd2567d9d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355714746798357420977393185
09607986951994671910079615350826991136717929371869 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.35571474679
835742097739318509607986951994671910079615350826991136717929371869
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.61559170116674344910206473099744327374792648935486805054416262058131999948726
Short name T650
Test name
Test status
Simulation time 32330757 ps
CPU time 0.9 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:09 PM PDT 23
Peak memory 205948 kb
Host smart-f3fec863-8d59-4fef-9573-ae45d1fc2df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61559170116674344910206473099744327374792648935486805054416262058131999948726 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_alert.61559170116674344910206473099744327374792648935486805054416262058131999948726
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.100966754581908190095255006166930726754821456095124096816417122631057826515588
Short name T524
Test name
Test status
Simulation time 16111390 ps
CPU time 0.92 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 205988 kb
Host smart-ca9c9a5e-bff7-4100-8179-696f6989fa2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100966754581908190095255006166930726754821456095124096816417122631057826515588 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.edn_alert_test.100966754581908190095255006166930726754821456095124096816417122631057826515588
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.115370052589446143037350439552683330684281351921585169662133020404863025548367
Short name T596
Test name
Test status
Simulation time 19976788 ps
CPU time 0.81 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:04 PM PDT 23
Peak memory 215040 kb
Host smart-fe27bac5-c314-4be6-a74d-dd3b31e5d3a1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115370052589446143037350439552683330684281351921585169662133020404863025548367 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 44.edn_disable.115370052589446143037350439552683330684281351921585169662133020404863025548367
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.92371929144418308166244510312390403023031577467530807999903734291062093392905
Short name T469
Test name
Test status
Simulation time 30622451 ps
CPU time 0.94 seconds
Started Oct 18 01:31:24 PM PDT 23
Finished Oct 18 01:31:26 PM PDT 23
Peak memory 215260 kb
Host smart-209c0978-489c-4ecf-8a80-150555cb0eab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92371929144418308166244510312390403023031577467530807999903734291062093392905 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.9237192914441830816624451031239040302303157746753080799990
3734291062093392905
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.40230244623524027915670825632740381300329246871609945668400327325258650124614
Short name T389
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:10 PM PDT 23
Peak memory 215320 kb
Host smart-a7676476-90eb-4631-af24-fbbc6e3d8dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40230244623524027915670825632740381300329246871609945668400327325258650124614 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.edn_err.40230244623524027915670825632740381300329246871609945668400327325258650124614
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.20476190769918732296597007606290299154678261923669262793149424001584410445583
Short name T104
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:31:17 PM PDT 23
Finished Oct 18 01:31:19 PM PDT 23
Peak memory 205772 kb
Host smart-d2a8a254-fa4e-46fa-9997-627503c42d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20476190769918732296597007606290299154678261923669262793149424001584410445583 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.edn_genbits.20476190769918732296597007606290299154678261923669262793149424001584410445583
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.8000086364863758927478828175473658793241269645879162151234637660669771019765
Short name T193
Test name
Test status
Simulation time 22372583 ps
CPU time 1.05 seconds
Started Oct 18 01:31:13 PM PDT 23
Finished Oct 18 01:31:15 PM PDT 23
Peak memory 222884 kb
Host smart-892f9289-2805-4d23-b6e2-163d7b565fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8000086364863758927478828175473658793241269645879162151234637660669771019765 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.edn_intr.8000086364863758927478828175473658793241269645879162151234637660669771019765
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.87902861683800555353659158615932874310289726043062702743601984490390986595510
Short name T544
Test name
Test status
Simulation time 21768426 ps
CPU time 0.88 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:58 PM PDT 23
Peak memory 205608 kb
Host smart-14c265ba-0dce-49cd-a049-360493883829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87902861683800555353659158615932874310289726043062702743601984490390986595510 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_smoke.87902861683800555353659158615932874310289726043062702743601984490390986595510
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.95759133453048143963092830025681944903111603829949302253110706159515521203636
Short name T627
Test name
Test status
Simulation time 299451483 ps
CPU time 3.62 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 206452 kb
Host smart-1329d518-d3a4-4cae-9709-654dc7485fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95759133453048143963092830025681944903111603829949302253110706159515521203636 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.95759133453048143963092830025681944903111603829949302253110706159515521203636
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.57081745407151647315049753582751243993157218466163676942882447641213763886891
Short name T540
Test name
Test status
Simulation time 86880545330 ps
CPU time 1106.05 seconds
Started Oct 18 01:31:26 PM PDT 23
Finished Oct 18 01:49:52 PM PDT 23
Peak memory 218644 kb
Host smart-75387cb4-4324-440d-93eb-cc5ebc89a0dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570817454071516473150497535
82751243993157218466163676942882447641213763886891 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.57081745407
151647315049753582751243993157218466163676942882447641213763886891
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.50568594437604284307671069016168835506942917623107014274140122597296167960993
Short name T155
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:31:00 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 205948 kb
Host smart-743ed11c-c320-44d5-9786-e7a40d4ae0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50568594437604284307671069016168835506942917623107014274140122597296167960993 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.edn_alert.50568594437604284307671069016168835506942917623107014274140122597296167960993
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.40664798663441178913868307270597960001992228309606421055971073123180094620888
Short name T195
Test name
Test status
Simulation time 16111390 ps
CPU time 0.87 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:31:03 PM PDT 23
Peak memory 205972 kb
Host smart-84ff57a1-06dc-4516-87c3-50a002dd3283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664798663441178913868307270597960001992228309606421055971073123180094620888 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_alert_test.40664798663441178913868307270597960001992228309606421055971073123180094620888
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.71828366647746014980430331854880006655351261595504889806277817277547027273250
Short name T481
Test name
Test status
Simulation time 19976788 ps
CPU time 0.87 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:14 PM PDT 23
Peak memory 215096 kb
Host smart-c46e7c56-e948-49e0-b830-22d0fe8c4ed7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71828366647746014980430331854880006655351261595504889806277817277547027273250 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.edn_disable.71828366647746014980430331854880006655351261595504889806277817277547027273250
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.94375062729952244493156976471256531566264223998029316851184379235586002965833
Short name T584
Test name
Test status
Simulation time 30622451 ps
CPU time 0.93 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 215288 kb
Host smart-eb2a4e17-11f9-434b-94c7-61852e3d478f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94375062729952244493156976471256531566264223998029316851184379235586002965833 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.9437506272995224449315697647125653156626422399802931685118
4379235586002965833
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.108873375932824629509585530409891677417609121926991359482372931491672773194458
Short name T657
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 215228 kb
Host smart-60671a1b-f6bf-4d49-9393-ba40af2d8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108873375932824629509585530409891677417609121926991359482372931491672773194458 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.edn_err.108873375932824629509585530409891677417609121926991359482372931491672773194458
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.34002109460311972155582776836287855151168778075443642319249032131425516517933
Short name T509
Test name
Test status
Simulation time 22643412 ps
CPU time 0.93 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 205692 kb
Host smart-494c0caa-b38e-4c9f-a54b-b51e4c5d4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34002109460311972155582776836287855151168778075443642319249032131425516517933 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.edn_genbits.34002109460311972155582776836287855151168778075443642319249032131425516517933
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.8710079759191495951512458135615331289635436273525281092031903492956009096293
Short name T624
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 222876 kb
Host smart-3a0b05b4-d2ab-489e-a212-b34c0167354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8710079759191495951512458135615331289635436273525281092031903492956009096293 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.edn_intr.8710079759191495951512458135615331289635436273525281092031903492956009096293
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.84263445154889553285322096396515763436333417372436255071848621925034511778127
Short name T350
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 205668 kb
Host smart-2553550f-62a4-4844-a644-ffedc0396be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84263445154889553285322096396515763436333417372436255071848621925034511778127 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.edn_smoke.84263445154889553285322096396515763436333417372436255071848621925034511778127
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.107519096977261891355562789401469258155003875257679600936909415504015458812794
Short name T604
Test name
Test status
Simulation time 299451483 ps
CPU time 3.82 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 206524 kb
Host smart-3b847dea-5825-4366-9375-50caeb74075b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107519096977261891355562789401469258155003875257679600936909415504015458812794 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.107519096977261891355562789401469258155003875257679600936909415504015458812794
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.26642600034578177767016529070530603005507245722258283636554597099543585972590
Short name T146
Test name
Test status
Simulation time 86880545330 ps
CPU time 1090.02 seconds
Started Oct 18 01:31:13 PM PDT 23
Finished Oct 18 01:49:23 PM PDT 23
Peak memory 218644 kb
Host smart-0f7d63b9-658f-4474-8846-f4a685da7d03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266426000345781777670165290
70530603005507245722258283636554597099543585972590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.26642600034
578177767016529070530603005507245722258283636554597099543585972590
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.71473988052103826497320629076364327596878149677422046895973655907206344648240
Short name T197
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 206004 kb
Host smart-8c5c1aae-afb2-4849-a1c6-f909f60a6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71473988052103826497320629076364327596878149677422046895973655907206344648240 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.edn_alert.71473988052103826497320629076364327596878149677422046895973655907206344648240
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.78822589356583363372568936805146181568164237673058754583355331138986483957201
Short name T465
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 205932 kb
Host smart-793860a8-f469-4e62-8e98-e4e10dd4adcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78822589356583363372568936805146181568164237673058754583355331138986483957201 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_alert_test.78822589356583363372568936805146181568164237673058754583355331138986483957201
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.36013544394531934059817162014608111377166316533960709983810368184491872328331
Short name T69
Test name
Test status
Simulation time 19976788 ps
CPU time 0.82 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:31:03 PM PDT 23
Peak memory 215096 kb
Host smart-4d579349-f7d2-4be3-aa2e-35349fbbe0d5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36013544394531934059817162014608111377166316533960709983810368184491872328331 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.edn_disable.36013544394531934059817162014608111377166316533960709983810368184491872328331
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.39050606054930294566550149650783400299320192590579379117946285044364312617344
Short name T447
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:31:18 PM PDT 23
Finished Oct 18 01:31:19 PM PDT 23
Peak memory 215400 kb
Host smart-c23c006c-adb0-4732-8e40-ebe25abe5536
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050606054930294566550149650783400299320192590579379117946285044364312617344 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.3905060605493029456655014965078340029932019259057937911794
6285044364312617344
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.81822233776021434595678458769712247917039999416685629567751442487057329831045
Short name T105
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:12 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 215344 kb
Host smart-ebfbd448-1cba-4ff8-8ba8-cae64393386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81822233776021434595678458769712247917039999416685629567751442487057329831045 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.edn_err.81822233776021434595678458769712247917039999416685629567751442487057329831045
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.91612965490048440332516174243785740093551131252296553066547043965744380278850
Short name T507
Test name
Test status
Simulation time 22643412 ps
CPU time 1.02 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 205732 kb
Host smart-e8679494-5d9b-4b43-8c92-7808cf7557f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91612965490048440332516174243785740093551131252296553066547043965744380278850 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.edn_genbits.91612965490048440332516174243785740093551131252296553066547043965744380278850
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.47306677314474260328755431514409654452352761322041936625324772567879392943036
Short name T677
Test name
Test status
Simulation time 22372583 ps
CPU time 1.03 seconds
Started Oct 18 01:31:17 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 222944 kb
Host smart-1f0a1119-3a09-4f0d-ba65-a473e53525e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47306677314474260328755431514409654452352761322041936625324772567879392943036 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.edn_intr.47306677314474260328755431514409654452352761322041936625324772567879392943036
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3023483887901484597824479991746934216701709630677273190457011967510050653709
Short name T593
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:31:19 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 205676 kb
Host smart-22113f51-1410-4d4c-9afc-88b9c9365dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023483887901484597824479991746934216701709630677273190457011967510050653709 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.edn_smoke.3023483887901484597824479991746934216701709630677273190457011967510050653709
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.45853056490586254985513524509731140423847898758068078883371453114679358737846
Short name T635
Test name
Test status
Simulation time 299451483 ps
CPU time 3.64 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 206380 kb
Host smart-cdf4f9c9-b0c4-473d-b356-c7564cc4ba64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45853056490586254985513524509731140423847898758068078883371453114679358737846 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.45853056490586254985513524509731140423847898758068078883371453114679358737846
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.108809869487094428139600898708053051145676419999630931151548743861451492067575
Short name T675
Test name
Test status
Simulation time 86880545330 ps
CPU time 1110.73 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:49:46 PM PDT 23
Peak memory 218620 kb
Host smart-21fbbad6-92c7-4b12-a0f5-3aff1131985b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108809869487094428139600898
708053051145676419999630931151548743861451492067575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1088098694
87094428139600898708053051145676419999630931151548743861451492067575
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.77533961829331987719416687824183581862391067327479806035245112081800756403034
Short name T362
Test name
Test status
Simulation time 32330757 ps
CPU time 1 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 205972 kb
Host smart-58811d41-227c-4116-ae55-5cbf99626fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77533961829331987719416687824183581862391067327479806035245112081800756403034 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_alert.77533961829331987719416687824183581862391067327479806035245112081800756403034
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.94461496283445827248315730315891136694922907792917796376439511470431722759968
Short name T546
Test name
Test status
Simulation time 16111390 ps
CPU time 0.98 seconds
Started Oct 18 01:31:18 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 205940 kb
Host smart-699a64bb-290e-4200-ae46-7a73ff580c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94461496283445827248315730315891136694922907792917796376439511470431722759968 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_alert_test.94461496283445827248315730315891136694922907792917796376439511470431722759968
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.37494790909759473203004275977996644390391755276948293726460029978925964788979
Short name T180
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:31:08 PM PDT 23
Finished Oct 18 01:31:09 PM PDT 23
Peak memory 215056 kb
Host smart-13f1fed4-c7f3-41b8-be5f-588fd92c19f0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37494790909759473203004275977996644390391755276948293726460029978925964788979 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.edn_disable.37494790909759473203004275977996644390391755276948293726460029978925964788979
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.102106358260035076572651762939506369047587223793247547592993138510649276811985
Short name T56
Test name
Test status
Simulation time 30622451 ps
CPU time 0.94 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:57 PM PDT 23
Peak memory 215232 kb
Host smart-0faac38f-0bfc-4488-a70d-6190ec6c923c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102106358260035076572651762939506369047587223793247547592993138510649276811985 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.102106358260035076572651762939506369047587223793247547592
993138510649276811985
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.113315239700289739759443249076661914969082224417713954433122188829711955357264
Short name T366
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:10 PM PDT 23
Peak memory 215276 kb
Host smart-b958314a-e2f5-4ff9-bf02-94e62462c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113315239700289739759443249076661914969082224417713954433122188829711955357264 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.edn_err.113315239700289739759443249076661914969082224417713954433122188829711955357264
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.60117104949808998934849132680933868022030365909794770391619216044224908563473
Short name T536
Test name
Test status
Simulation time 22643412 ps
CPU time 0.93 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:31:12 PM PDT 23
Peak memory 205716 kb
Host smart-b4cb3e1b-5af4-4d65-8920-d607d886da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60117104949808998934849132680933868022030365909794770391619216044224908563473 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.edn_genbits.60117104949808998934849132680933868022030365909794770391619216044224908563473
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.89152648408866421026573118670038251910364366507845381744849577837030162108320
Short name T185
Test name
Test status
Simulation time 22372583 ps
CPU time 1.15 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 222924 kb
Host smart-ec944695-89db-44e4-8ef8-a2f4ec1fbeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89152648408866421026573118670038251910364366507845381744849577837030162108320 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.edn_intr.89152648408866421026573118670038251910364366507845381744849577837030162108320
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.97291161139157181112227452265205591414786238827759699156476827746294918337742
Short name T386
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:03 PM PDT 23
Peak memory 205724 kb
Host smart-de39b9ed-b911-4ba5-86b8-8f6e40bee984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97291161139157181112227452265205591414786238827759699156476827746294918337742 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_smoke.97291161139157181112227452265205591414786238827759699156476827746294918337742
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.92890774026174924829118464876720183103696606141461577059433046899423435202513
Short name T172
Test name
Test status
Simulation time 299451483 ps
CPU time 3.7 seconds
Started Oct 18 01:31:13 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 206496 kb
Host smart-a9e863b7-be8d-44ad-93a5-32007f3788e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92890774026174924829118464876720183103696606141461577059433046899423435202513 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.92890774026174924829118464876720183103696606141461577059433046899423435202513
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.60070036396575299590932380080672460832630586123307238708545960673611928660835
Short name T629
Test name
Test status
Simulation time 86880545330 ps
CPU time 1117.64 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:49:55 PM PDT 23
Peak memory 218624 kb
Host smart-807bc1e5-39cb-4e17-b585-a37fd1f92a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600700363965752995909323800
80672460832630586123307238708545960673611928660835 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.60070036396
575299590932380080672460832630586123307238708545960673611928660835
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.24195407500703325297545592091453504612777234498599530935671867088563845642229
Short name T184
Test name
Test status
Simulation time 32330757 ps
CPU time 0.95 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 205968 kb
Host smart-14645c9e-453d-46d9-8163-28837fb69701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24195407500703325297545592091453504612777234498599530935671867088563845642229 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.edn_alert.24195407500703325297545592091453504612777234498599530935671867088563845642229
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.69751714297922573232154248519547285084511587444269964124751905336163791673935
Short name T18
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 206008 kb
Host smart-887fe16a-7058-4939-bffa-f192bc28a136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69751714297922573232154248519547285084511587444269964124751905336163791673935 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_alert_test.69751714297922573232154248519547285084511587444269964124751905336163791673935
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.79565496128336309594746836779761812671566989446703764547254121433756208087471
Short name T168
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:06 PM PDT 23
Peak memory 215040 kb
Host smart-2bb948da-f73d-4eca-86b3-8ba96d836413
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79565496128336309594746836779761812671566989446703764547254121433756208087471 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.edn_disable.79565496128336309594746836779761812671566989446703764547254121433756208087471
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.28063348402477435980001332421870187519062102179491890515153600746084483957001
Short name T54
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:31:17 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 215268 kb
Host smart-6a84961c-3030-4a1e-8257-2d304ea9d841
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28063348402477435980001332421870187519062102179491890515153600746084483957001 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.2806334840247743598000133242187018751906210217949189051515
3600746084483957001
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.63612676702934331859711403115954112156864891173720608585218783875470586333809
Short name T539
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:07 PM PDT 23
Peak memory 215208 kb
Host smart-6dea9fbb-0f6a-46fa-aa31-9a7733d12115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63612676702934331859711403115954112156864891173720608585218783875470586333809 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.edn_err.63612676702934331859711403115954112156864891173720608585218783875470586333809
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.76007117344687293405261513812968157661627194688696157375994804879844639892910
Short name T541
Test name
Test status
Simulation time 22643412 ps
CPU time 0.98 seconds
Started Oct 18 01:31:24 PM PDT 23
Finished Oct 18 01:31:26 PM PDT 23
Peak memory 205796 kb
Host smart-0b1014d6-04bb-499e-9e5a-e27f2bfea22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76007117344687293405261513812968157661627194688696157375994804879844639892910 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.edn_genbits.76007117344687293405261513812968157661627194688696157375994804879844639892910
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.38916246090507914598468168687137583082957908965022818955389050239623636916337
Short name T562
Test name
Test status
Simulation time 22372583 ps
CPU time 1.04 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 222880 kb
Host smart-d08d1a2a-d417-4891-b31c-c2130a30b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38916246090507914598468168687137583082957908965022818955389050239623636916337 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.edn_intr.38916246090507914598468168687137583082957908965022818955389050239623636916337
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.35580141167714166019011674761738488614458743061725209001373988178701840442257
Short name T693
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:31:22 PM PDT 23
Finished Oct 18 01:31:23 PM PDT 23
Peak memory 205664 kb
Host smart-25aed96b-270d-443d-8cf2-6ff0569a8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35580141167714166019011674761738488614458743061725209001373988178701840442257 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.edn_smoke.35580141167714166019011674761738488614458743061725209001373988178701840442257
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.113553935882027907888731867830753158562712839150598006618093497511076956110487
Short name T166
Test name
Test status
Simulation time 299451483 ps
CPU time 3.78 seconds
Started Oct 18 01:31:13 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 206504 kb
Host smart-7ac21fa3-da0c-4c3c-80ec-306780c1efe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113553935882027907888731867830753158562712839150598006618093497511076956110487 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.113553935882027907888731867830753158562712839150598006618093497511076956110487
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.26738610943647652633235783589353674083651573102891268469660099740903729198802
Short name T615
Test name
Test status
Simulation time 86880545330 ps
CPU time 1096.14 seconds
Started Oct 18 01:31:02 PM PDT 23
Finished Oct 18 01:49:19 PM PDT 23
Peak memory 218624 kb
Host smart-261b473f-40c6-4598-b34d-2e59bd22ecc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267386109436476526332357835
89353674083651573102891268469660099740903729198802 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.26738610943
647652633235783589353674083651573102891268469660099740903729198802
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.79132364037096592873766263668809127345429646860984537470135133474286825678199
Short name T178
Test name
Test status
Simulation time 32330757 ps
CPU time 0.96 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 205984 kb
Host smart-0ef7a2d9-fd48-4e5e-b200-96841e96b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79132364037096592873766263668809127345429646860984537470135133474286825678199 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_alert.79132364037096592873766263668809127345429646860984537470135133474286825678199
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.18299384968542290341281704865938054410480429887358695145826258147031864531714
Short name T71
Test name
Test status
Simulation time 16111390 ps
CPU time 0.89 seconds
Started Oct 18 01:31:18 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 206008 kb
Host smart-8fa92b8a-229c-43e6-958e-d361d8d1ca25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18299384968542290341281704865938054410480429887358695145826258147031864531714 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_alert_test.18299384968542290341281704865938054410480429887358695145826258147031864531714
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.56427829880793877913010634113022009173415557944050331476917134838358281232886
Short name T135
Test name
Test status
Simulation time 19976788 ps
CPU time 0.87 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 215084 kb
Host smart-cb865dfc-ed52-4043-a193-0bdb32675ea7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56427829880793877913010634113022009173415557944050331476917134838358281232886 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.edn_disable.56427829880793877913010634113022009173415557944050331476917134838358281232886
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.102951711853542290792403586092511213973707760976798454595565755296591875931961
Short name T59
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 215304 kb
Host smart-7f8af0d1-4e2c-49e9-8196-04775ff2b112
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102951711853542290792403586092511213973707760976798454595565755296591875931961 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.102951711853542290792403586092511213973707760976798454595
565755296591875931961
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.35174382825702245720464176550915202293378981321161386421453951498921964267855
Short name T160
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:31:25 PM PDT 23
Finished Oct 18 01:31:27 PM PDT 23
Peak memory 215252 kb
Host smart-acf8eefc-0c5d-432f-82ee-420c6d5c5e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35174382825702245720464176550915202293378981321161386421453951498921964267855 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.edn_err.35174382825702245720464176550915202293378981321161386421453951498921964267855
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.90489658284680438034477123020402662376607131872425689052175191637197756497794
Short name T136
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:07 PM PDT 23
Peak memory 205804 kb
Host smart-5ad631a6-0f7f-414d-80ae-24c37d7f6034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90489658284680438034477123020402662376607131872425689052175191637197756497794 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.edn_genbits.90489658284680438034477123020402662376607131872425689052175191637197756497794
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.91121610951274936516731585659498653246701997612089249625236375830390949906308
Short name T622
Test name
Test status
Simulation time 22372583 ps
CPU time 1.07 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 222808 kb
Host smart-b8cf3915-211a-4c59-a069-559a777c48bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91121610951274936516731585659498653246701997612089249625236375830390949906308 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.edn_intr.91121610951274936516731585659498653246701997612089249625236375830390949906308
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.42179116550928892735395843026253245080140191913056101021349032006841623752432
Short name T592
Test name
Test status
Simulation time 21768426 ps
CPU time 0.84 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 205660 kb
Host smart-e7b640ef-526b-4cdd-b120-9d511ba2ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42179116550928892735395843026253245080140191913056101021349032006841623752432 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_smoke.42179116550928892735395843026253245080140191913056101021349032006841623752432
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.72507811434364417908860195343740700169044783898798045228333198726291897940633
Short name T727
Test name
Test status
Simulation time 299451483 ps
CPU time 3.79 seconds
Started Oct 18 01:31:14 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 206520 kb
Host smart-f85c1838-f7db-4606-9c99-c9d46b56dff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72507811434364417908860195343740700169044783898798045228333198726291897940633 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.72507811434364417908860195343740700169044783898798045228333198726291897940633
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2557827819172281460123002368273904823323204112029188427158982701674152420547
Short name T9
Test name
Test status
Simulation time 86880545330 ps
CPU time 1142.85 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:50:20 PM PDT 23
Peak memory 218648 kb
Host smart-3d8e1a11-2b07-4287-a51f-bc4117af821f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255782781917228146012300236
8273904823323204112029188427158982701674152420547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.255782781917
2281460123002368273904823323204112029188427158982701674152420547
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.48433301542940655437399471656669301158560633397051848220843883043196191020899
Short name T590
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:30 PM PDT 23
Peak memory 205928 kb
Host smart-86c7fc01-b32a-44d5-8abf-c5362e933666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48433301542940655437399471656669301158560633397051848220843883043196191020899 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_alert.48433301542940655437399471656669301158560633397051848220843883043196191020899
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.5548639831427795704198417618533445324332888171188740007608710461716498043454
Short name T570
Test name
Test status
Simulation time 16111390 ps
CPU time 0.9 seconds
Started Oct 18 01:30:32 PM PDT 23
Finished Oct 18 01:30:34 PM PDT 23
Peak memory 206020 kb
Host smart-443cd22f-2656-49dc-b3fe-c88d860819d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5548639831427795704198417618533445324332888171188740007608710461716498043454 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_alert_test.5548639831427795704198417618533445324332888171188740007608710461716498043454
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.72370743363778358030293122669310248920052020509628666649631264908090357868804
Short name T681
Test name
Test status
Simulation time 19976788 ps
CPU time 0.82 seconds
Started Oct 18 01:30:34 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 215048 kb
Host smart-f74b2eea-eba6-4d5e-b94a-d723730a8d10
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72370743363778358030293122669310248920052020509628666649631264908090357868804 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_disable.72370743363778358030293122669310248920052020509628666649631264908090357868804
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.109926023212966448430433308515923012442705992023328435538378725807007428100471
Short name T460
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:30:55 PM PDT 23
Finished Oct 18 01:30:56 PM PDT 23
Peak memory 215276 kb
Host smart-9c2a9d46-1341-44bc-92f8-edfccbfd55fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109926023212966448430433308515923012442705992023328435538378725807007428100471 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.1099260232129664484304333085159230124427059920233284355383
78725807007428100471
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.70599551957866007601711090974497031011939446210346912991666236610458824758986
Short name T383
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:30:36 PM PDT 23
Finished Oct 18 01:30:37 PM PDT 23
Peak memory 215216 kb
Host smart-33489371-0fd6-4e22-a605-3a215589d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70599551957866007601711090974497031011939446210346912991666236610458824758986 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
edn_err.70599551957866007601711090974497031011939446210346912991666236610458824758986
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.8437510881771835056924320192827023152120415828996795220894009445374638054608
Short name T49
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:30:26 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 205672 kb
Host smart-20891d41-d323-4b90-9843-3c185d859a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8437510881771835056924320192827023152120415828996795220894009445374638054608 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.edn_genbits.8437510881771835056924320192827023152120415828996795220894009445374638054608
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.71216947774674441386519326248493565460927284709320598830091922448725417953906
Short name T491
Test name
Test status
Simulation time 22372583 ps
CPU time 1.02 seconds
Started Oct 18 01:30:22 PM PDT 23
Finished Oct 18 01:30:24 PM PDT 23
Peak memory 222888 kb
Host smart-88da8e29-575b-443b-abb7-2afd6c67b6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71216947774674441386519326248493565460927284709320598830091922448725417953906 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.edn_intr.71216947774674441386519326248493565460927284709320598830091922448725417953906
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.33187231101272244815430408375142591033081934410858480618878270245736146615083
Short name T110
Test name
Test status
Simulation time 19018470 ps
CPU time 0.85 seconds
Started Oct 18 01:30:16 PM PDT 23
Finished Oct 18 01:30:17 PM PDT 23
Peak memory 205576 kb
Host smart-d1736550-304a-4a25-8c34-b3da87264664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33187231101272244815430408375142591033081934410858480618878270245736146615083 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.edn_regwen.33187231101272244815430408375142591033081934410858480618878270245736146615083
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.101612211356986909561174278371319864431983195410654695052228566741411380490882
Short name T719
Test name
Test status
Simulation time 21768426 ps
CPU time 0.88 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205620 kb
Host smart-9f8a4380-c030-43d3-9bf8-bd3950e2e816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101612211356986909561174278371319864431983195410654695052228566741411380490882 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.edn_smoke.101612211356986909561174278371319864431983195410654695052228566741411380490882
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.104928015748889824561053363407240839715815633590152910968857397642853505342285
Short name T711
Test name
Test status
Simulation time 299451483 ps
CPU time 3.58 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:34 PM PDT 23
Peak memory 206592 kb
Host smart-0b87771d-383e-45ce-80f4-427e61b04732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104928015748889824561053363407240839715815633590152910968857397642853505342285 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.104928015748889824561053363407240839715815633590152910968857397642853505342285
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.103386381260767065470260391461707422530191981994832266753096495924282659077719
Short name T368
Test name
Test status
Simulation time 86880545330 ps
CPU time 1106.86 seconds
Started Oct 18 01:30:12 PM PDT 23
Finished Oct 18 01:48:39 PM PDT 23
Peak memory 218684 kb
Host smart-01787266-9fa3-4d24-bdab-643e29ee13ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103386381260767065470260391
461707422530191981994832266753096495924282659077719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.10338638126
0767065470260391461707422530191981994832266753096495924282659077719
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.20800757149582584812412206460299474425297584440725858908793186866412278048219
Short name T658
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:11 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 215216 kb
Host smart-fa312277-5e00-45c2-966e-0ab7bc8b356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20800757149582584812412206460299474425297584440725858908793186866412278048219 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50
.edn_err.20800757149582584812412206460299474425297584440725858908793186866412278048219
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.1143061599005470128327602065711269631957084537870190636728189149839606507797
Short name T346
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:16 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 215268 kb
Host smart-a174b233-7f32-4339-b101-5dc21cdc0acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143061599005470128327602065711269631957084537870190636728189149839606507797 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.
edn_err.1143061599005470128327602065711269631957084537870190636728189149839606507797
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.36648710663955546091810731841203734906708724159615095105862219193024720316279
Short name T342
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:12 PM PDT 23
Finished Oct 18 01:31:14 PM PDT 23
Peak memory 215336 kb
Host smart-1bc49ca3-97ca-4698-9018-92b3ad9f51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36648710663955546091810731841203734906708724159615095105862219193024720316279 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52
.edn_err.36648710663955546091810731841203734906708724159615095105862219193024720316279
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.34165284140803891207250483209976457657329384642388703666041691789600494913302
Short name T106
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 215288 kb
Host smart-1f067bcd-0915-4d33-b0ee-3d42069ce384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34165284140803891207250483209976457657329384642388703666041691789600494913302 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53
.edn_err.34165284140803891207250483209976457657329384642388703666041691789600494913302
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.35766941965665497722167074763064361590770209716006443191504577266033434325996
Short name T148
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:31:18 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 215308 kb
Host smart-d90e623d-e09e-410f-9694-7a990e869458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35766941965665497722167074763064361590770209716006443191504577266033434325996 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54
.edn_err.35766941965665497722167074763064361590770209716006443191504577266033434325996
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.81063992605668740352243106971431404767042458341641889025989731658819869574744
Short name T340
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:07 PM PDT 23
Peak memory 215308 kb
Host smart-4e3ef363-e6fb-4dc3-b77c-d9dcac824d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81063992605668740352243106971431404767042458341641889025989731658819869574744 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55
.edn_err.81063992605668740352243106971431404767042458341641889025989731658819869574744
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.96829962676513482836624502958798232722297280172825619552805120871092709839222
Short name T52
Test name
Test status
Simulation time 29871889 ps
CPU time 0.96 seconds
Started Oct 18 01:31:18 PM PDT 23
Finished Oct 18 01:31:20 PM PDT 23
Peak memory 215184 kb
Host smart-089bfccb-3ae5-4703-ac97-00774fb11eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96829962676513482836624502958798232722297280172825619552805120871092709839222 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56
.edn_err.96829962676513482836624502958798232722297280172825619552805120871092709839222
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.76514474753719031576111696949894626819587975863695684433450617504236171965968
Short name T413
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:17 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 215284 kb
Host smart-f74d7b90-2cb9-42ca-9ba9-70dc4078e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76514474753719031576111696949894626819587975863695684433450617504236171965968 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57
.edn_err.76514474753719031576111696949894626819587975863695684433450617504236171965968
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.37264537868043142356508497069934355363231108468364641895127141221800608411626
Short name T603
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:30 PM PDT 23
Finished Oct 18 01:31:31 PM PDT 23
Peak memory 215304 kb
Host smart-346ef4c6-54d7-449c-8ecc-e1a4be1d2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37264537868043142356508497069934355363231108468364641895127141221800608411626 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58
.edn_err.37264537868043142356508497069934355363231108468364641895127141221800608411626
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.70902119572079527657271843993891108997954112644883719844933785047095968159209
Short name T415
Test name
Test status
Simulation time 29871889 ps
CPU time 0.93 seconds
Started Oct 18 01:31:13 PM PDT 23
Finished Oct 18 01:31:15 PM PDT 23
Peak memory 215264 kb
Host smart-3dd9d3c2-d989-41e9-8174-04fd8f8b0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70902119572079527657271843993891108997954112644883719844933785047095968159209 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59
.edn_err.70902119572079527657271843993891108997954112644883719844933785047095968159209
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.45653686024265393042294429307805789484466801097353388744347975083204363954642
Short name T706
Test name
Test status
Simulation time 32330757 ps
CPU time 0.97 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205976 kb
Host smart-f3b53716-8c3a-4be6-885d-526c4ca75777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45653686024265393042294429307805789484466801097353388744347975083204363954642 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_alert.45653686024265393042294429307805789484466801097353388744347975083204363954642
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.32013626352126830805549970333837912678966819605416622444787899643161268669598
Short name T660
Test name
Test status
Simulation time 16111390 ps
CPU time 0.91 seconds
Started Oct 18 01:30:13 PM PDT 23
Finished Oct 18 01:30:14 PM PDT 23
Peak memory 205976 kb
Host smart-6a0ccc42-c4d6-4305-a2c8-486a9bda7cfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32013626352126830805549970333837912678966819605416622444787899643161268669598 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_alert_test.32013626352126830805549970333837912678966819605416622444787899643161268669598
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.47230327874398597784150791091549891958352872728832724403980257871736528653666
Short name T691
Test name
Test status
Simulation time 19976788 ps
CPU time 0.81 seconds
Started Oct 18 01:30:24 PM PDT 23
Finished Oct 18 01:30:26 PM PDT 23
Peak memory 215044 kb
Host smart-376c3765-9d23-4d2a-8c74-f2caa2f04a9d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47230327874398597784150791091549891958352872728832724403980257871736528653666 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_disable.47230327874398597784150791091549891958352872728832724403980257871736528653666
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.79221860257658070883938990599264283491058514760603809211425178474185399477758
Short name T358
Test name
Test status
Simulation time 30622451 ps
CPU time 0.92 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:03 PM PDT 23
Peak memory 215288 kb
Host smart-9b22ac7e-e011-4468-a88b-7c8ca1133339
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79221860257658070883938990599264283491058514760603809211425178474185399477758 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.79221860257658070883938990599264283491058514760603809211425
178474185399477758
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.15392215342784887084717911803563795949204606161207662454598602837462094714380
Short name T555
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:31:01 PM PDT 23
Finished Oct 18 01:31:02 PM PDT 23
Peak memory 215144 kb
Host smart-11d0805a-5622-43ab-998c-70535b783680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15392215342784887084717911803563795949204606161207662454598602837462094714380 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
edn_err.15392215342784887084717911803563795949204606161207662454598602837462094714380
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.35457440787314760369564465790955236468848117164811245912570528595522563590278
Short name T40
Test name
Test status
Simulation time 22643412 ps
CPU time 0.97 seconds
Started Oct 18 01:30:25 PM PDT 23
Finished Oct 18 01:30:27 PM PDT 23
Peak memory 205764 kb
Host smart-438cf175-30f9-41a5-8976-38e6b0a47f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35457440787314760369564465790955236468848117164811245912570528595522563590278 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.edn_genbits.35457440787314760369564465790955236468848117164811245912570528595522563590278
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.47673344237387573975154511267186621584355989570975734946824117810683698697101
Short name T631
Test name
Test status
Simulation time 22372583 ps
CPU time 1.03 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 222784 kb
Host smart-c65470d5-97f3-4a9a-a69d-3e2fb7851442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47673344237387573975154511267186621584355989570975734946824117810683698697101 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.edn_intr.47673344237387573975154511267186621584355989570975734946824117810683698697101
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.44630510166073683445067117578661385771517515739183285394773388176321128418518
Short name T473
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:30:37 PM PDT 23
Finished Oct 18 01:30:38 PM PDT 23
Peak memory 205656 kb
Host smart-a2d2ad25-b71d-42c4-b5a2-ee942b2c1188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44630510166073683445067117578661385771517515739183285394773388176321128418518 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_smoke.44630510166073683445067117578661385771517515739183285394773388176321128418518
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.113967174319500427361866540025232928229801382230078743619397020319894913270947
Short name T644
Test name
Test status
Simulation time 299451483 ps
CPU time 3.66 seconds
Started Oct 18 01:30:40 PM PDT 23
Finished Oct 18 01:30:45 PM PDT 23
Peak memory 206448 kb
Host smart-83ce1557-e1f7-44da-92f1-5a5acd3aab98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113967174319500427361866540025232928229801382230078743619397020319894913270947 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.113967174319500427361866540025232928229801382230078743619397020319894913270947
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.107454616575651262669195510984555505618771567162851737491643847713403895629049
Short name T673
Test name
Test status
Simulation time 86880545330 ps
CPU time 1105.89 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:49:01 PM PDT 23
Peak memory 218724 kb
Host smart-1183f3ca-24d9-43af-ba0d-e6a93bedf8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107454616575651262669195510
984555505618771567162851737491643847713403895629049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.10745461657
5651262669195510984555505618771567162851737491643847713403895629049
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.83013207427410142594860323815555320039221565671056350993179266068002211415115
Short name T424
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:07 PM PDT 23
Finished Oct 18 01:31:18 PM PDT 23
Peak memory 215264 kb
Host smart-3760aba4-0f3a-4343-8a73-7d5054e6a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83013207427410142594860323815555320039221565671056350993179266068002211415115 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60
.edn_err.83013207427410142594860323815555320039221565671056350993179266068002211415115
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.14820282210312676517137699787661908717744715266524786521959787073403875153435
Short name T512
Test name
Test status
Simulation time 29871889 ps
CPU time 0.88 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:04 PM PDT 23
Peak memory 215332 kb
Host smart-67384aa3-c632-4bbc-a9ed-8f3941c687c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14820282210312676517137699787661908717744715266524786521959787073403875153435 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61
.edn_err.14820282210312676517137699787661908717744715266524786521959787073403875153435
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.77980878384059431536542308431035823957144457921798520354064872095865869055227
Short name T498
Test name
Test status
Simulation time 29871889 ps
CPU time 0.86 seconds
Started Oct 18 01:31:23 PM PDT 23
Finished Oct 18 01:31:24 PM PDT 23
Peak memory 215228 kb
Host smart-5c6901e2-cdab-4bf3-835b-b29e210aa387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77980878384059431536542308431035823957144457921798520354064872095865869055227 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62
.edn_err.77980878384059431536542308431035823957144457921798520354064872095865869055227
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.83255738574028325298016330334820771986887097290123578728260115429198242439821
Short name T53
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:22 PM PDT 23
Finished Oct 18 01:31:23 PM PDT 23
Peak memory 215256 kb
Host smart-8dd43e6f-62a1-4f9b-bd82-9d6374589172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83255738574028325298016330334820771986887097290123578728260115429198242439821 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63
.edn_err.83255738574028325298016330334820771986887097290123578728260115429198242439821
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.60926410064402178603261201918351572025206380221317979230844215184488966732046
Short name T470
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:21 PM PDT 23
Finished Oct 18 01:31:22 PM PDT 23
Peak memory 215232 kb
Host smart-ac280805-4430-46b7-9f04-04a640e5547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60926410064402178603261201918351572025206380221317979230844215184488966732046 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64
.edn_err.60926410064402178603261201918351572025206380221317979230844215184488966732046
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.79156084350311657892234408906891147068813755439187213026788504750004670395356
Short name T119
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 215228 kb
Host smart-12671459-6549-495f-9074-12f200fb830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79156084350311657892234408906891147068813755439187213026788504750004670395356 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65
.edn_err.79156084350311657892234408906891147068813755439187213026788504750004670395356
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.9408475998315922019908870118772592936107521515109707315137586600619331842904
Short name T381
Test name
Test status
Simulation time 29871889 ps
CPU time 0.95 seconds
Started Oct 18 01:31:26 PM PDT 23
Finished Oct 18 01:31:27 PM PDT 23
Peak memory 215292 kb
Host smart-b7965e2a-edbb-4ae4-94e8-7053387d5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9408475998315922019908870118772592936107521515109707315137586600619331842904 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.
edn_err.9408475998315922019908870118772592936107521515109707315137586600619331842904
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.108941919769066828490217227915094933311755058380214886737460432406823970679238
Short name T517
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:23 PM PDT 23
Finished Oct 18 01:31:25 PM PDT 23
Peak memory 215280 kb
Host smart-3cc0b7c4-37b6-414d-9960-a39c4947cf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108941919769066828490217227915094933311755058380214886737460432406823970679238 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
7.edn_err.108941919769066828490217227915094933311755058380214886737460432406823970679238
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.94497030539197158001560924018085960444377548168963125733016440565651270250724
Short name T19
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:21 PM PDT 23
Finished Oct 18 01:31:22 PM PDT 23
Peak memory 215272 kb
Host smart-1c33835f-357c-4590-a9e4-efe538b6d953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94497030539197158001560924018085960444377548168963125733016440565651270250724 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68
.edn_err.94497030539197158001560924018085960444377548168963125733016440565651270250724
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.88822449130085910808695070797086583284810876425309728912912110712130821311444
Short name T429
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:23 PM PDT 23
Finished Oct 18 01:31:25 PM PDT 23
Peak memory 215260 kb
Host smart-fa671f0f-c6e8-4997-9d13-201a62ad13b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88822449130085910808695070797086583284810876425309728912912110712130821311444 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69
.edn_err.88822449130085910808695070797086583284810876425309728912912110712130821311444
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.30576126788429495107408936964068333677149432805770546115111068024611537970953
Short name T170
Test name
Test status
Simulation time 32330757 ps
CPU time 0.97 seconds
Started Oct 18 01:30:42 PM PDT 23
Finished Oct 18 01:30:43 PM PDT 23
Peak memory 206028 kb
Host smart-eaf9973d-b5e2-4225-8657-d345530208a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30576126788429495107408936964068333677149432805770546115111068024611537970953 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_alert.30576126788429495107408936964068333677149432805770546115111068024611537970953
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.108812400982300421761748919284189121778513774806175433115269950790198256205719
Short name T647
Test name
Test status
Simulation time 16111390 ps
CPU time 0.97 seconds
Started Oct 18 01:31:20 PM PDT 23
Finished Oct 18 01:31:27 PM PDT 23
Peak memory 206000 kb
Host smart-3b798cbd-b19f-400e-9081-4eb0505b85e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108812400982300421761748919284189121778513774806175433115269950790198256205719 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.edn_alert_test.108812400982300421761748919284189121778513774806175433115269950790198256205719
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.36458667578595462458387895358813954797264961030373147279238366028496924543485
Short name T400
Test name
Test status
Simulation time 19976788 ps
CPU time 0.86 seconds
Started Oct 18 01:30:54 PM PDT 23
Finished Oct 18 01:30:56 PM PDT 23
Peak memory 215048 kb
Host smart-f246dad4-875a-477f-bdb4-c16ecec6d43d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36458667578595462458387895358813954797264961030373147279238366028496924543485 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_disable.36458667578595462458387895358813954797264961030373147279238366028496924543485
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.16714138887044478097907887127426193906655231585810541908209840551589697138455
Short name T619
Test name
Test status
Simulation time 30622451 ps
CPU time 0.93 seconds
Started Oct 18 01:31:00 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 215228 kb
Host smart-f1050365-e77a-4b71-9c8d-7d0b4761eb29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16714138887044478097907887127426193906655231585810541908209840551589697138455 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.16714138887044478097907887127426193906655231585810541908209
840551589697138455
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.34505352891491836395454074074221579826645452689342289783514276451269268141944
Short name T559
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 215156 kb
Host smart-cb4166f7-3a0b-4a4f-bf33-b4c6956cd2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34505352891491836395454074074221579826645452689342289783514276451269268141944 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
edn_err.34505352891491836395454074074221579826645452689342289783514276451269268141944
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.35010028341882837811175322628211838619179239425791077847118974963922852399737
Short name T678
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:29:32 PM PDT 23
Finished Oct 18 01:29:33 PM PDT 23
Peak memory 205760 kb
Host smart-12e8361b-a102-4af2-aaf8-ecbf1c6d436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35010028341882837811175322628211838619179239425791077847118974963922852399737 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.edn_genbits.35010028341882837811175322628211838619179239425791077847118974963922852399737
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.38996374639674040226748242032217564039659486877294265932733807223765146448172
Short name T502
Test name
Test status
Simulation time 22372583 ps
CPU time 1 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:30:57 PM PDT 23
Peak memory 222912 kb
Host smart-5c957e9e-98aa-4f44-9904-4cacafdf36fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38996374639674040226748242032217564039659486877294265932733807223765146448172 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.edn_intr.38996374639674040226748242032217564039659486877294265932733807223765146448172
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.87780289934601546673236757930219510282858084614070235399032020894435871384140
Short name T480
Test name
Test status
Simulation time 19018470 ps
CPU time 0.84 seconds
Started Oct 18 01:30:54 PM PDT 23
Finished Oct 18 01:30:55 PM PDT 23
Peak memory 205700 kb
Host smart-12104bc1-89eb-466b-82b7-431a773b4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87780289934601546673236757930219510282858084614070235399032020894435871384140 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.edn_regwen.87780289934601546673236757930219510282858084614070235399032020894435871384140
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.35125606947901715765233920372918485943553724691578236878180467533049997517785
Short name T568
Test name
Test status
Simulation time 21768426 ps
CPU time 0.86 seconds
Started Oct 18 01:30:46 PM PDT 23
Finished Oct 18 01:30:52 PM PDT 23
Peak memory 205684 kb
Host smart-b7b04b4b-aed1-44c3-8d8b-fc0b94feef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35125606947901715765233920372918485943553724691578236878180467533049997517785 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_smoke.35125606947901715765233920372918485943553724691578236878180467533049997517785
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.94155217633476860605567368516270261245207485689635550903700078030888705642442
Short name T173
Test name
Test status
Simulation time 299451483 ps
CPU time 3.59 seconds
Started Oct 18 01:31:03 PM PDT 23
Finished Oct 18 01:31:08 PM PDT 23
Peak memory 206468 kb
Host smart-9fc7ff82-418c-45fd-8891-c4c708ca9c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94155217633476860605567368516270261245207485689635550903700078030888705642442 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.94155217633476860605567368516270261245207485689635550903700078030888705642442
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.109572888726211367471230924826870083425301651933029354113037248988539251731554
Short name T8
Test name
Test status
Simulation time 86880545330 ps
CPU time 1113.38 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:49:45 PM PDT 23
Peak memory 218580 kb
Host smart-d84a96c2-ae39-46c2-92c7-972309b1b9ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109572888726211367471230924
826870083425301651933029354113037248988539251731554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.10957288872
6211367471230924826870083425301651933029354113037248988539251731554
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.9098736686452399901050413116030131515397358557457416586688246532610766927982
Short name T628
Test name
Test status
Simulation time 29871889 ps
CPU time 0.96 seconds
Started Oct 18 01:31:14 PM PDT 23
Finished Oct 18 01:31:15 PM PDT 23
Peak memory 215284 kb
Host smart-475ac358-8c98-4306-bfad-d99910c3c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9098736686452399901050413116030131515397358557457416586688246532610766927982 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.
edn_err.9098736686452399901050413116030131515397358557457416586688246532610766927982
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.25683508252597059320967217601766993040495489743714699215850946374790625585053
Short name T443
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:11 PM PDT 23
Peak memory 215176 kb
Host smart-493849b9-7aee-48f5-b5dc-99c987f77f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25683508252597059320967217601766993040495489743714699215850946374790625585053 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71
.edn_err.25683508252597059320967217601766993040495489743714699215850946374790625585053
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.29041209639409638794038380921683423239612566509524607830769018916191433794354
Short name T683
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:06 PM PDT 23
Finished Oct 18 01:31:07 PM PDT 23
Peak memory 215332 kb
Host smart-6df0fd92-f20b-47bb-86d4-99588a0fb3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29041209639409638794038380921683423239612566509524607830769018916191433794354 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72
.edn_err.29041209639409638794038380921683423239612566509524607830769018916191433794354
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.58696899366121038666817649209844189753775917753098582696644992071996421392931
Short name T142
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:28 PM PDT 23
Finished Oct 18 01:31:29 PM PDT 23
Peak memory 215276 kb
Host smart-61be69ce-c97e-4aa9-9421-b5f2f94ba9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58696899366121038666817649209844189753775917753098582696644992071996421392931 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73
.edn_err.58696899366121038666817649209844189753775917753098582696644992071996421392931
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.114173177813786490442228126570273920011580945270239393574657554342895070049173
Short name T729
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:16 PM PDT 23
Peak memory 215156 kb
Host smart-9294e1c4-3efd-4f26-a903-2e9b7401b915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114173177813786490442228126570273920011580945270239393574657554342895070049173 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
4.edn_err.114173177813786490442228126570273920011580945270239393574657554342895070049173
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.68604706295245426048350710678570476692935999980085482379621236220364298860490
Short name T398
Test name
Test status
Simulation time 29871889 ps
CPU time 0.93 seconds
Started Oct 18 01:31:13 PM PDT 23
Finished Oct 18 01:31:15 PM PDT 23
Peak memory 215192 kb
Host smart-a821717f-ca79-44c7-b745-e1831891d446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68604706295245426048350710678570476692935999980085482379621236220364298860490 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75
.edn_err.68604706295245426048350710678570476692935999980085482379621236220364298860490
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.100092150206172578870980021310835106664051991111774175870026713431787801262210
Short name T571
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:10 PM PDT 23
Peak memory 215304 kb
Host smart-6b0cb813-e06d-4f97-bd85-ee6f121a9bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100092150206172578870980021310835106664051991111774175870026713431787801262210 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
6.edn_err.100092150206172578870980021310835106664051991111774175870026713431787801262210
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.75052361092094115271759159978106206037663178072202418246467201255662226606950
Short name T459
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:37 PM PDT 23
Finished Oct 18 01:31:38 PM PDT 23
Peak memory 215316 kb
Host smart-9c415c1b-bf4d-478e-a936-040fbc94cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75052361092094115271759159978106206037663178072202418246467201255662226606950 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77
.edn_err.75052361092094115271759159978106206037663178072202418246467201255662226606950
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.26195975933511935904105581996177781125604253957866862003939524714331956659596
Short name T115
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:30:59 PM PDT 23
Peak memory 215500 kb
Host smart-1317cfb1-32bf-45d0-9caf-ebc6649b0e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26195975933511935904105581996177781125604253957866862003939524714331956659596 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78
.edn_err.26195975933511935904105581996177781125604253957866862003939524714331956659596
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.32230247234938166811902476918033484588088082709829695891825714407554160809869
Short name T684
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:10 PM PDT 23
Finished Oct 18 01:31:12 PM PDT 23
Peak memory 215500 kb
Host smart-94ba4e2b-0291-4d05-babe-8ba0d8c42d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32230247234938166811902476918033484588088082709829695891825714407554160809869 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79
.edn_err.32230247234938166811902476918033484588088082709829695891825714407554160809869
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.85453147182658172915866922924167132008327022706778762553162163051325001121616
Short name T22
Test name
Test status
Simulation time 32330757 ps
CPU time 0.94 seconds
Started Oct 18 01:30:31 PM PDT 23
Finished Oct 18 01:30:32 PM PDT 23
Peak memory 205972 kb
Host smart-75749ba4-9a89-4081-8e2f-e2aea7cd6f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85453147182658172915866922924167132008327022706778762553162163051325001121616 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.edn_alert.85453147182658172915866922924167132008327022706778762553162163051325001121616
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.66408454175414288980631104620957451860087840173560393583560276186477978405243
Short name T145
Test name
Test status
Simulation time 16111390 ps
CPU time 0.92 seconds
Started Oct 18 01:29:51 PM PDT 23
Finished Oct 18 01:29:53 PM PDT 23
Peak memory 205912 kb
Host smart-a6d27271-12b4-471b-a1df-c177216995db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66408454175414288980631104620957451860087840173560393583560276186477978405243 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_alert_test.66408454175414288980631104620957451860087840173560393583560276186477978405243
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.58084633902845248548136899176904471878535906330942587737706904616488009227068
Short name T401
Test name
Test status
Simulation time 30622451 ps
CPU time 0.94 seconds
Started Oct 18 01:29:48 PM PDT 23
Finished Oct 18 01:29:54 PM PDT 23
Peak memory 215252 kb
Host smart-aabf0013-eb6e-44ca-a4ff-13b4f32c2b6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58084633902845248548136899176904471878535906330942587737706904616488009227068 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.58084633902845248548136899176904471878535906330942587737706
904616488009227068
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.13089713787581145491847405051137024079200981645520615020664533465729421928764
Short name T108
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:30:07 PM PDT 23
Finished Oct 18 01:30:08 PM PDT 23
Peak memory 215312 kb
Host smart-cc1efaec-81da-41c6-87a3-1132f67addf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13089713787581145491847405051137024079200981645520615020664533465729421928764 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
edn_err.13089713787581145491847405051137024079200981645520615020664533465729421928764
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.73078365834791792296963814736021817012374996704061560771942276824561811908368
Short name T600
Test name
Test status
Simulation time 22643412 ps
CPU time 0.96 seconds
Started Oct 18 01:30:45 PM PDT 23
Finished Oct 18 01:30:48 PM PDT 23
Peak memory 205628 kb
Host smart-9fc0110e-0f97-4de1-a086-e3d98b62c4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73078365834791792296963814736021817012374996704061560771942276824561811908368 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.edn_genbits.73078365834791792296963814736021817012374996704061560771942276824561811908368
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.8927071653982229754721743700607147007054318059650362335659303031961308082151
Short name T36
Test name
Test status
Simulation time 22372583 ps
CPU time 0.99 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:16 PM PDT 23
Peak memory 222928 kb
Host smart-a609720d-15b7-4639-9f08-0a54aa79a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8927071653982229754721743700607147007054318059650362335659303031961308082151 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.edn_intr.8927071653982229754721743700607147007054318059650362335659303031961308082151
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.17863748225820920588364874758829067893676684437870032628160863905557422999268
Short name T534
Test name
Test status
Simulation time 19018470 ps
CPU time 0.82 seconds
Started Oct 18 01:30:07 PM PDT 23
Finished Oct 18 01:30:08 PM PDT 23
Peak memory 205660 kb
Host smart-956499a3-90a4-4c39-8866-5f7a30c45b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17863748225820920588364874758829067893676684437870032628160863905557422999268 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.edn_regwen.17863748225820920588364874758829067893676684437870032628160863905557422999268
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.25460245867697662935947936852213061383472753359852504176882834740825599553670
Short name T192
Test name
Test status
Simulation time 21768426 ps
CPU time 0.83 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:29:45 PM PDT 23
Peak memory 205608 kb
Host smart-009927fb-b8e5-4689-8bc8-31fce06d2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25460245867697662935947936852213061383472753359852504176882834740825599553670 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.edn_smoke.25460245867697662935947936852213061383472753359852504176882834740825599553670
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.73348808644940240800112319823561796746166685919141643754405964338939109004319
Short name T390
Test name
Test status
Simulation time 299451483 ps
CPU time 3.56 seconds
Started Oct 18 01:30:56 PM PDT 23
Finished Oct 18 01:31:00 PM PDT 23
Peak memory 206556 kb
Host smart-eb9c4d29-6c57-4b71-890b-c81b54376746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73348808644940240800112319823561796746166685919141643754405964338939109004319 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.73348808644940240800112319823561796746166685919141643754405964338939109004319
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.75672450270852403999952531451745265208239017683383693594878389663786123094685
Short name T2
Test name
Test status
Simulation time 86880545330 ps
CPU time 1127.53 seconds
Started Oct 18 01:30:06 PM PDT 23
Finished Oct 18 01:48:54 PM PDT 23
Peak memory 218628 kb
Host smart-a607eacc-85e5-41ba-8895-5e26554ac81e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756724502708524039999525314
51745265208239017683383693594878389663786123094685 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.756724502708
52403999952531451745265208239017683383693594878389663786123094685
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.36683398051536893700434960097847273189516067189997040819611448023667394773469
Short name T156
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:55 PM PDT 23
Finished Oct 18 01:31:57 PM PDT 23
Peak memory 215248 kb
Host smart-2c09e789-074b-4c3e-973b-afcd6def6ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36683398051536893700434960097847273189516067189997040819611448023667394773469 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80
.edn_err.36683398051536893700434960097847273189516067189997040819611448023667394773469
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.102995166562285471523937241516267135303047907936768360286297215770158196018544
Short name T594
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:12 PM PDT 23
Finished Oct 18 01:31:13 PM PDT 23
Peak memory 215240 kb
Host smart-382ffa34-1b6d-44d9-a0b5-d69473a07748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102995166562285471523937241516267135303047907936768360286297215770158196018544 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
1.edn_err.102995166562285471523937241516267135303047907936768360286297215770158196018544
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.22141179134419839236523284830566684751159037060231397960126015181545854624535
Short name T359
Test name
Test status
Simulation time 29871889 ps
CPU time 0.97 seconds
Started Oct 18 01:31:46 PM PDT 23
Finished Oct 18 01:31:47 PM PDT 23
Peak memory 215284 kb
Host smart-044591f6-57db-4e81-8127-5da5ca85a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22141179134419839236523284830566684751159037060231397960126015181545854624535 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82
.edn_err.22141179134419839236523284830566684751159037060231397960126015181545854624535
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.64057248700239749175261363363138729425105996419514785536518314040454329262569
Short name T117
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:31:22 PM PDT 23
Finished Oct 18 01:31:23 PM PDT 23
Peak memory 215284 kb
Host smart-0dd6f17f-eb21-4b9c-ae27-4aa42b566eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64057248700239749175261363363138729425105996419514785536518314040454329262569 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83
.edn_err.64057248700239749175261363363138729425105996419514785536518314040454329262569
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.52603349804186981035705551554575997523125158638316259488823034134504547026101
Short name T636
Test name
Test status
Simulation time 29871889 ps
CPU time 0.93 seconds
Started Oct 18 01:31:29 PM PDT 23
Finished Oct 18 01:31:30 PM PDT 23
Peak memory 215332 kb
Host smart-51d767b9-eb46-4ac8-8a6f-a1567265edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52603349804186981035705551554575997523125158638316259488823034134504547026101 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84
.edn_err.52603349804186981035705551554575997523125158638316259488823034134504547026101
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.31551000533323294454898072209748566113632450678904833379674653573003192334876
Short name T716
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:31:34 PM PDT 23
Finished Oct 18 01:31:35 PM PDT 23
Peak memory 215284 kb
Host smart-1aadf4bc-c100-4906-8317-17fe242c1dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31551000533323294454898072209748566113632450678904833379674653573003192334876 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85
.edn_err.31551000533323294454898072209748566113632450678904833379674653573003192334876
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.111107853922770067448158135504995428230027652755762733930778127391663325548530
Short name T488
Test name
Test status
Simulation time 29871889 ps
CPU time 0.92 seconds
Started Oct 18 01:31:38 PM PDT 23
Finished Oct 18 01:31:39 PM PDT 23
Peak memory 215284 kb
Host smart-c6b441e0-0f01-4bbc-bdad-f28bff154a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111107853922770067448158135504995428230027652755762733930778127391663325548530 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
6.edn_err.111107853922770067448158135504995428230027652755762733930778127391663325548530
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.99491774554775524326686059529935393607103707783663047991511627750586010225107
Short name T560
Test name
Test status
Simulation time 29871889 ps
CPU time 0.94 seconds
Started Oct 18 01:31:22 PM PDT 23
Finished Oct 18 01:31:23 PM PDT 23
Peak memory 215296 kb
Host smart-214d09b0-2a6d-4165-a3c5-5cd4538eda00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99491774554775524326686059529935393607103707783663047991511627750586010225107 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87
.edn_err.99491774554775524326686059529935393607103707783663047991511627750586010225107
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.11550418336494743962511928493487824343456135397074725627934951198254069173527
Short name T194
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:09 PM PDT 23
Finished Oct 18 01:31:10 PM PDT 23
Peak memory 215256 kb
Host smart-2c285919-1d16-4bab-9183-9636dc9af399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11550418336494743962511928493487824343456135397074725627934951198254069173527 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88
.edn_err.11550418336494743962511928493487824343456135397074725627934951198254069173527
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.87754045328443201550460594619939080760423194788846759954973482639263636804776
Short name T199
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:31:15 PM PDT 23
Finished Oct 18 01:31:17 PM PDT 23
Peak memory 215212 kb
Host smart-4498c5ce-a051-4c0a-abcc-da0805ba9541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87754045328443201550460594619939080760423194788846759954973482639263636804776 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89
.edn_err.87754045328443201550460594619939080760423194788846759954973482639263636804776
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.17358978666512258462761212023322501252114780358692104069813611596726815494078
Short name T634
Test name
Test status
Simulation time 32330757 ps
CPU time 1 seconds
Started Oct 18 01:29:45 PM PDT 23
Finished Oct 18 01:29:47 PM PDT 23
Peak memory 205952 kb
Host smart-2987c1ee-7f4a-41fc-b6c7-0d2a298bf868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17358978666512258462761212023322501252114780358692104069813611596726815494078 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.edn_alert.17358978666512258462761212023322501252114780358692104069813611596726815494078
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4730071431572724748780824633427498672381058952244675038700555674298647476175
Short name T356
Test name
Test status
Simulation time 16111390 ps
CPU time 0.93 seconds
Started Oct 18 01:30:30 PM PDT 23
Finished Oct 18 01:30:32 PM PDT 23
Peak memory 206024 kb
Host smart-1e9b0177-5673-490e-ad0e-b48dbbb2ebeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4730071431572724748780824633427498672381058952244675038700555674298647476175 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_alert_test.4730071431572724748780824633427498672381058952244675038700555674298647476175
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.95851191858190109474396625001360302373880125691166718091709104012690992137527
Short name T385
Test name
Test status
Simulation time 19976788 ps
CPU time 0.83 seconds
Started Oct 18 01:29:44 PM PDT 23
Finished Oct 18 01:29:45 PM PDT 23
Peak memory 215040 kb
Host smart-01e79909-cf11-454d-b3b0-add3c90bcfda
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95851191858190109474396625001360302373880125691166718091709104012690992137527 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_disable.95851191858190109474396625001360302373880125691166718091709104012690992137527
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.79603339189508583074372752887072278158469651159203359784020169064374153966226
Short name T602
Test name
Test status
Simulation time 30622451 ps
CPU time 0.89 seconds
Started Oct 18 01:30:14 PM PDT 23
Finished Oct 18 01:30:15 PM PDT 23
Peak memory 215264 kb
Host smart-46ad91d3-38fe-4826-aeb2-b4458380198d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79603339189508583074372752887072278158469651159203359784020169064374153966226 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.79603339189508583074372752887072278158469651159203359784020
169064374153966226
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.101935035703662077412962678441326696943457746120704553371038294289779846981638
Short name T484
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:29:43 PM PDT 23
Finished Oct 18 01:29:44 PM PDT 23
Peak memory 215184 kb
Host smart-712cc714-8423-4d71-ac97-1308b4c21bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101935035703662077412962678441326696943457746120704553371038294289779846981638 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.edn_err.101935035703662077412962678441326696943457746120704553371038294289779846981638
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.52588505605711655844167135735712420500579587107301973173770675321787749779534
Short name T118
Test name
Test status
Simulation time 22643412 ps
CPU time 0.95 seconds
Started Oct 18 01:30:28 PM PDT 23
Finished Oct 18 01:30:29 PM PDT 23
Peak memory 205736 kb
Host smart-7044d6a6-5902-4fc0-a63c-e599d1460577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52588505605711655844167135735712420500579587107301973173770675321787749779534 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.edn_genbits.52588505605711655844167135735712420500579587107301973173770675321787749779534
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.66003491985125367018702246006651866694738998759905144529563798252743073231548
Short name T379
Test name
Test status
Simulation time 22372583 ps
CPU time 1 seconds
Started Oct 18 01:30:19 PM PDT 23
Finished Oct 18 01:30:21 PM PDT 23
Peak memory 222716 kb
Host smart-f1b3aae3-28ea-49fc-b4bf-e9131091eb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66003491985125367018702246006651866694738998759905144529563798252743073231548 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.edn_intr.66003491985125367018702246006651866694738998759905144529563798252743073231548
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.85200546932303094816056204224650350036433769445457492373515550116086848210224
Short name T574
Test name
Test status
Simulation time 19018470 ps
CPU time 0.83 seconds
Started Oct 18 01:29:37 PM PDT 23
Finished Oct 18 01:29:38 PM PDT 23
Peak memory 205696 kb
Host smart-7e012f6a-47b6-480d-b992-ba74c2e033cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85200546932303094816056204224650350036433769445457492373515550116086848210224 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.edn_regwen.85200546932303094816056204224650350036433769445457492373515550116086848210224
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.109950027158043438402234776563115972379359561133375167955872123572823023302820
Short name T432
Test name
Test status
Simulation time 21768426 ps
CPU time 0.85 seconds
Started Oct 18 01:30:03 PM PDT 23
Finished Oct 18 01:30:04 PM PDT 23
Peak memory 205696 kb
Host smart-2419d9b9-96da-470a-b702-f7791647a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109950027158043438402234776563115972379359561133375167955872123572823023302820 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.edn_smoke.109950027158043438402234776563115972379359561133375167955872123572823023302820
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.101803794861667412810322870099718843449399471465893616258953577563506684253788
Short name T153
Test name
Test status
Simulation time 299451483 ps
CPU time 3.58 seconds
Started Oct 18 01:30:31 PM PDT 23
Finished Oct 18 01:30:35 PM PDT 23
Peak memory 206404 kb
Host smart-49e05a8b-94d5-4283-84c7-25cca46c0571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101803794861667412810322870099718843449399471465893616258953577563506684253788 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.101803794861667412810322870099718843449399471465893616258953577563506684253788
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.64437580566440791823917280128817192135997690347764323227299424465667880699694
Short name T518
Test name
Test status
Simulation time 86880545330 ps
CPU time 1028.7 seconds
Started Oct 18 01:29:45 PM PDT 23
Finished Oct 18 01:46:55 PM PDT 23
Peak memory 218628 kb
Host smart-30ef6682-9dca-4ca6-8da0-5989295d40a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644375805664407918239172801
28817192135997690347764323227299424465667880699694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.644375805664
40791823917280128817192135997690347764323227299424465667880699694
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.84971590747668252803403197454271311629987971917269593654337126413100055186096
Short name T477
Test name
Test status
Simulation time 29871889 ps
CPU time 0.93 seconds
Started Oct 18 01:31:39 PM PDT 23
Finished Oct 18 01:31:41 PM PDT 23
Peak memory 215224 kb
Host smart-28e4f01e-fccb-48c0-92f6-33bbaf2de029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84971590747668252803403197454271311629987971917269593654337126413100055186096 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90
.edn_err.84971590747668252803403197454271311629987971917269593654337126413100055186096
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.2134213602198588350247842674290646811339409009910685506101378846222936930701
Short name T656
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:31:27 PM PDT 23
Finished Oct 18 01:31:29 PM PDT 23
Peak memory 215312 kb
Host smart-5af72101-e712-42ee-8449-8b37ab4501dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134213602198588350247842674290646811339409009910685506101378846222936930701 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.
edn_err.2134213602198588350247842674290646811339409009910685506101378846222936930701
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.38641386235412057881799684284979832225563917730099501472250660575606496622899
Short name T183
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:30 PM PDT 23
Finished Oct 18 01:31:32 PM PDT 23
Peak memory 215336 kb
Host smart-67bb2d0c-f9ad-4ff2-8f75-27c54b947f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38641386235412057881799684284979832225563917730099501472250660575606496622899 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92
.edn_err.38641386235412057881799684284979832225563917730099501472250660575606496622899
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.45809396187528463458831588337709078675915924931615478155425087562344156695979
Short name T394
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:31:20 PM PDT 23
Finished Oct 18 01:31:21 PM PDT 23
Peak memory 215300 kb
Host smart-0e40e00d-feff-45cd-a167-d24c2b353185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45809396187528463458831588337709078675915924931615478155425087562344156695979 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93
.edn_err.45809396187528463458831588337709078675915924931615478155425087562344156695979
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.25115421390588183819210343751902735537862928690296383683583460916476685272334
Short name T406
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:08 PM PDT 23
Finished Oct 18 01:31:10 PM PDT 23
Peak memory 215264 kb
Host smart-cd59f782-7195-4ad8-93a6-8cdb67613ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25115421390588183819210343751902735537862928690296383683583460916476685272334 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94
.edn_err.25115421390588183819210343751902735537862928690296383683583460916476685272334
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.77253873084927295188142281861858626361348047114036823687554274163765074687997
Short name T715
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:19 PM PDT 23
Finished Oct 18 01:31:21 PM PDT 23
Peak memory 215344 kb
Host smart-05fe194c-1e68-4589-802f-0cfa6b4abbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77253873084927295188142281861858626361348047114036823687554274163765074687997 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95
.edn_err.77253873084927295188142281861858626361348047114036823687554274163765074687997
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.5067520036578616176712495478567301301835676323834105234308612119939590878053
Short name T696
Test name
Test status
Simulation time 29871889 ps
CPU time 0.9 seconds
Started Oct 18 01:31:34 PM PDT 23
Finished Oct 18 01:31:40 PM PDT 23
Peak memory 215304 kb
Host smart-3766c4af-6773-42cb-adc9-24a5bbfaeaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5067520036578616176712495478567301301835676323834105234308612119939590878053 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.
edn_err.5067520036578616176712495478567301301835676323834105234308612119939590878053
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.78738348705107974556649940807022524136152356489923663928370070455754670030160
Short name T668
Test name
Test status
Simulation time 29871889 ps
CPU time 0.91 seconds
Started Oct 18 01:31:27 PM PDT 23
Finished Oct 18 01:31:28 PM PDT 23
Peak memory 215256 kb
Host smart-d34b6dde-8819-4cd3-84f9-0a1d60aa5c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78738348705107974556649940807022524136152356489923663928370070455754670030160 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97
.edn_err.78738348705107974556649940807022524136152356489923663928370070455754670030160
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.39406919739088197861442399076387225933229894665639696515878191684249697498853
Short name T132
Test name
Test status
Simulation time 29871889 ps
CPU time 0.87 seconds
Started Oct 18 01:30:58 PM PDT 23
Finished Oct 18 01:30:59 PM PDT 23
Peak memory 215264 kb
Host smart-878919b3-2b9d-4f52-a4b9-30e0d75d2e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39406919739088197861442399076387225933229894665639696515878191684249697498853 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98
.edn_err.39406919739088197861442399076387225933229894665639696515878191684249697498853
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.98821400989722563914212700356635123841664721868925404921990184615845562831292
Short name T339
Test name
Test status
Simulation time 29871889 ps
CPU time 0.89 seconds
Started Oct 18 01:31:28 PM PDT 23
Finished Oct 18 01:31:30 PM PDT 23
Peak memory 215304 kb
Host smart-c8cf275d-ae2e-4d41-a0b3-bf6f11a17c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98821400989722563914212700356635123841664721868925404921990184615845562831292 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99
.edn_err.98821400989722563914212700356635123841664721868925404921990184615845562831292
Directory /workspace/99.edn_err/latest
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