Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	918345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6514350

1

T13

29

T14

29

T15

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2047100	1			T13	212		T14	212		T15	50
values[0x0]	2501670	1			T13	8		T14	8		T15	3
values[0x1]	2883925	1			T13	20		T14	20		T15	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	478390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6954305

1

T13

103

T14

103

T15

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28350	1			T18	3		T1	561		T19	3
valid_sources[0x01]	31170	1			T17	2		T18	2		T1	599
valid_sources[0x02]	28600	1			T13	8		T14	8		T24	8
valid_sources[0x03]	32200	1			T16	12		T25	13		T17	4
valid_sources[0x04]	21700	1			T1	434		T34	434		T45	434
valid_sources[0x05]	30050	1			T17	2		T18	1		T1	597
valid_sources[0x06]	27670	1			T15	11		T40	11		T17	3
valid_sources[0x07]	29150	1			T17	11		T18	6		T1	548
valid_sources[0x08]	31410	1			T13	12		T14	12		T15	1
valid_sources[0x09]	24300	1			T18	2		T1	480		T19	2
valid_sources[0x0a]	32750	1			T1	655		T34	655		T45	655
valid_sources[0x0b]	32000	1			T17	20		T18	4		T1	612
valid_sources[0x0c]	23900	1			T18	4		T1	470		T19	4
valid_sources[0x0d]	30500	1			T17	7		T18	2		T1	599
valid_sources[0x0e]	26875	1			T13	9		T14	9		T24	9
valid_sources[0x0f]	30250	1			T17	6		T1	599		T34	599
valid_sources[0x10]	24850	1			T13	2		T14	2		T24	2
valid_sources[0x11]	27000	1			T18	1		T1	538		T19	1
valid_sources[0x12]	31675	1			T18	2		T1	624		T4	12
valid_sources[0x13]	33350	1			T17	8		T1	659		T34	659
valid_sources[0x14]	26500	1			T17	18		T1	502		T21	10
valid_sources[0x15]	32390	1			T13	12		T14	12		T24	12
valid_sources[0x16]	29050	1			T1	581		T34	581		T45	581
valid_sources[0x17]	27875	1			T18	1		T1	554		T98	15
valid_sources[0x18]	27850	1			T17	5		T18	3		T1	544
valid_sources[0x19]	30910	1			T17	1		T18	2		T1	610
valid_sources[0x1a]	32050	1			T13	6		T14	6		T24	6
valid_sources[0x1b]	26100	1			T17	22		T1	497		T21	3
valid_sources[0x1c]	29435	1			T18	3		T1	582		T84	7
valid_sources[0x1d]	32685	1			T18	1		T1	651		T84	7
valid_sources[0x1e]	26340	1			T17	8		T1	506		T80	12
valid_sources[0x1f]	34150	1			T17	19		T18	1		T1	662
valid_sources[0x20]	36150	1			T18	1		T1	721		T19	1
valid_sources[0x21]	29100	1			T1	582		T34	582		T45	582
valid_sources[0x22]	30600	1			T1	612		T34	612		T45	612
valid_sources[0x23]	35290	1			T17	7		T1	696		T80	7
valid_sources[0x24]	26450	1			T18	1		T1	527		T19	1
valid_sources[0x25]	29300	1			T1	586		T34	586		T45	586
valid_sources[0x26]	29335	1			T17	1		T1	585		T84	7
valid_sources[0x27]	27750	1			T13	2		T14	2		T24	2
valid_sources[0x28]	27500	1			T17	3		T1	547		T34	547
valid_sources[0x29]	27785	1			T16	4		T17	7		T18	2
valid_sources[0x2a]	29750	1			T18	1		T1	593		T19	1
valid_sources[0x2b]	24300	1			T1	486		T34	486		T45	486
valid_sources[0x2c]	29600	1			T18	1		T1	590		T19	1
valid_sources[0x2d]	29550	1			T17	8		T1	583		T34	583
valid_sources[0x2e]	30450	1			T13	5		T14	5		T24	5
valid_sources[0x2f]	26650	1			T18	1		T1	531		T19	1
valid_sources[0x30]	28250	1			T17	10		T1	555		T34	555
valid_sources[0x31]	28350	1			T17	10		T18	5		T1	547
valid_sources[0x32]	34100	1			T17	16		T18	1		T1	664
valid_sources[0x33]	33300	1			T18	2		T1	662		T19	2
valid_sources[0x34]	29800	1			T13	2		T14	2		T24	2
valid_sources[0x35]	23500	1			T17	5		T18	1		T1	463
valid_sources[0x36]	25570	1			T17	6		T1	495		T4	26
valid_sources[0x37]	28800	1			T17	8		T18	4		T1	560
valid_sources[0x38]	35950	1			T17	7		T1	712		T34	712
valid_sources[0x39]	31950	1			T17	1		T1	632		T4	15
valid_sources[0x3a]	32050	1			T17	9		T1	632		T34	632
valid_sources[0x3b]	29000	1			T17	1		T18	2		T1	575
valid_sources[0x3c]	27400	1			T17	8		T1	540		T34	540
valid_sources[0x3d]	28470	1			T18	1		T1	559		T11	21
valid_sources[0x3e]	26100	1			T17	1		T1	521		T34	521
valid_sources[0x3f]	28650	1			T17	9		T18	1		T1	562
valid_sources[0x40]	25900	1			T1	518		T34	518		T45	518
valid_sources[0x41]	28850	1			T17	11		T18	2		T1	562
valid_sources[0x42]	33350	1			T18	5		T1	657		T19	5
valid_sources[0x43]	34750	1			T13	7		T14	7		T15	4
valid_sources[0x44]	30100	1			T13	11		T14	11		T24	11
valid_sources[0x45]	31150	1			T17	9		T1	614		T34	614
valid_sources[0x46]	26400	1			T1	528		T34	528		T45	528
valid_sources[0x47]	31135	1			T17	11		T1	611		T84	7
valid_sources[0x48]	28850	1			T18	4		T1	563		T4	15
valid_sources[0x49]	33760	1			T13	13		T14	13		T24	13
valid_sources[0x4a]	34200	1			T17	7		T1	677		T34	677
valid_sources[0x4b]	28450	1			T17	9		T18	2		T1	556
valid_sources[0x4c]	28360	1			T17	5		T18	7		T1	545
valid_sources[0x4d]	27700	1			T17	1		T18	1		T1	551
valid_sources[0x4e]	28350	1			T1	567		T34	567		T45	567
valid_sources[0x4f]	31100	1			T13	2		T14	2		T24	2
valid_sources[0x50]	24300	1			T18	1		T1	484		T19	1
valid_sources[0x51]	23250	1			T17	18		T18	2		T1	443
valid_sources[0x52]	34340	1			T1	674		T49	128		T99	128
valid_sources[0x53]	26300	1			T13	1		T14	1		T24	1
valid_sources[0x54]	24650	1			T17	20		T18	3		T1	467
valid_sources[0x55]	29250	1			T1	585		T34	585		T45	585
valid_sources[0x56]	26300	1			T17	21		T1	505		T34	505
valid_sources[0x57]	32850	1			T17	1		T18	2		T1	652
valid_sources[0x58]	31750	1			T17	3		T1	632		T34	632
valid_sources[0x59]	28125	1			T1	557		T80	12		T12	12
valid_sources[0x5a]	27250	1			T1	545		T34	545		T45	545
valid_sources[0x5b]	28900	1			T13	14		T14	14		T24	14
valid_sources[0x5c]	21750	1			T13	3		T14	3		T24	3
valid_sources[0x5d]	25500	1			T17	2		T1	508		T34	508
valid_sources[0x5e]	30150	1			T18	1		T1	601		T19	1
valid_sources[0x5f]	28560	1			T17	16		T1	553		T21	2
valid_sources[0x60]	37950	1			T13	19		T14	19		T24	19
valid_sources[0x61]	28650	1			T18	3		T1	567		T19	3
valid_sources[0x62]	28910	1			T17	7		T18	1		T1	569
valid_sources[0x63]	36350	1			T17	17		T18	5		T1	700
valid_sources[0x64]	27350	1			T17	5		T1	542		T34	542
valid_sources[0x65]	28730	1			T18	3		T1	537		T49	256
valid_sources[0x66]	28040	1			T18	2		T1	544		T49	128
valid_sources[0x67]	29950	1			T17	5		T1	594		T34	594
valid_sources[0x68]	24800	1			T18	1		T1	494		T19	1
valid_sources[0x69]	30535	1			T13	1		T14	1		T24	1
valid_sources[0x6a]	32450	1			T17	3		T1	646		T34	646
valid_sources[0x6b]	30000	1			T1	600		T34	600		T45	600
valid_sources[0x6c]	23600	1			T15	11		T16	7		T40	11
valid_sources[0x6d]	24410	1			T17	2		T18	1		T1	477
valid_sources[0x6e]	32100	1			T17	2		T18	2		T1	636
valid_sources[0x6f]	25500	1			T16	6		T17	1		T18	1
valid_sources[0x70]	24410	1			T17	3		T18	1		T1	482
valid_sources[0x71]	23530	1			T1	467		T80	9		T12	9
valid_sources[0x72]	38050	1			T1	761		T34	761		T45	761
valid_sources[0x73]	36050	1			T18	5		T1	711		T19	5
valid_sources[0x74]	25750	1			T17	6		T18	5		T1	499
valid_sources[0x75]	29210	1			T13	4		T14	4		T24	4
valid_sources[0x76]	37550	1			T13	8		T14	8		T24	8
valid_sources[0x77]	32530	1			T17	21		T1	628		T80	4
valid_sources[0x78]	27060	1			T17	20		T18	6		T1	509
valid_sources[0x79]	29500	1			T1	590		T34	590		T45	590
valid_sources[0x7a]	39550	1			T13	13		T14	13		T24	13
valid_sources[0x7b]	35050	1			T17	6		T18	2		T1	691
valid_sources[0x7c]	26900	1			T17	5		T1	533		T34	533
valid_sources[0x7d]	31210	1			T17	4		T1	619		T80	3
valid_sources[0x7e]	26220	1			T17	2		T1	520		T34	520
valid_sources[0x7f]	27130	1			T17	7		T18	2		T1	531
valid_sources[0x80]	31935	1			T13	8		T14	8		T24	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1622345

1

T13

4

T14

4

T15

7

values[0x0]

all_enables

biggest_size

2448775

1

T13

7

T14

7

T15

3

values[0x1]

all_enables

biggest_size

2443230

1

T13

18

T14

18

T15

2