Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
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Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
67.65 67.65 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 67.65 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
67.65 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 22 27 55.10


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 8 5 38.46 100 1 1 0
cr_instantiate_intended 13 5 8 61.54 100 1 1 0
cr_reseed_intended 12 4 8 66.67 100 1 1 0
cr_update_intended 4 2 2 50.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 3 2 40.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 5810 1 T1 78 T11 1 T2 78
auto[RES] 1250 1 T1 14 T2 14 T15 3
auto[GEN] 5410 1 T1 68 T11 2 T2 68
auto[UPD] 750 1 T1 12 T2 12 T15 3
auto[UNI] 5460 1 T1 78 T2 78 T14 2


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 6800 1 T1 89 T2 89 T14 2
no_cmd_data 11880 1 T1 161 T11 3 T2 161


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 17180 1 T1 250 T11 3 T2 250
reseed_cmd 400 1 T19 3 T20 3 T21 3
generate_cmd 400 1 T19 3 T20 3 T21 3
boot_gen_cmd 350 1 T14 1 T16 1 T17 1
boot_ins_cmd 350 1 T14 1 T16 1 T17 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 5600 1 T1 72 T11 3 T2 72
false 13080 1 T1 178 T2 178 T14 5


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1350 1 T14 3 T16 3 T17 3
one 2560 1 T1 32 T11 2 T2 32


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 15930 1 T1 250 T2 250 T14 1
boot_mode 1600 1 T14 5 T16 5 T17 5
auto_mode 1150 1 T11 3 T19 7 T20 7


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 8 5 38.46 8
Automatically Generated Cross Bins 13 8 5 38.46 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Uncovered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTNUMBERSTATUS
[auto[GEN]] [some_cmd_data] [multiple] [sw_mode] [sw_cmd_req] 0 1 1
[auto[GEN]] [some_cmd_data] [multiple] [auto_mode] [generate_cmd] 0 1 1
[auto[GEN]] [some_cmd_data] [one] [sw_mode , boot_mode] [sw_cmd_req] -- -- 2
[auto[GEN]] [no_cmd_data] [multiple] [sw_mode , boot_mode] [sw_cmd_req] -- -- 2
[auto[GEN]] [no_cmd_data] [multiple] [auto_mode] [generate_cmd] 0 1 1
[auto[GEN]] [no_cmd_data] [one] [boot_mode] [sw_cmd_req] 0 1 1


Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 300 1 T14 1 T16 1 T17 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 300 1 T19 2 T20 2 T21 2
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 300 1 T14 1 T16 1 T17 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 2010 1 T1 32 T2 32 T15 6
auto[GEN] no_cmd_data one auto_mode generate_cmd 100 1 T19 1 T20 1 T21 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 5 8 61.54 5
Automatically Generated Cross Bins 13 5 8 61.54 5
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Uncovered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTNUMBERSTATUS
[auto[INS]] [some_cmd_data] [true] [boot_mode] [sw_cmd_req] 0 1 1
[auto[INS]] [some_cmd_data] [false] [auto_mode] [sw_cmd_req] 0 1 1
[auto[INS]] [no_cmd_data] [true] [boot_mode] [sw_cmd_req] 0 1 1
[auto[INS]] [no_cmd_data] [false] [boot_mode] [sw_cmd_req] 0 1 1
[auto[INS]] [no_cmd_data] [false] [boot_mode] [boot_ins_cmd] 0 1 1


Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 1050 1 T1 18 T2 18 T15 3
auto[INS] some_cmd_data true auto_mode sw_cmd_req 50 1 T22 1 T23 1 T24 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 1300 1 T1 20 T2 20 T15 6
auto[INS] some_cmd_data false boot_mode sw_cmd_req 300 1 T14 1 T16 1 T17 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 350 1 T1 5 T2 5 T15 2
auto[INS] no_cmd_data true auto_mode sw_cmd_req 100 1 T11 1 T42 1 T22 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 2210 1 T1 35 T2 35 T15 7
auto[INS] no_cmd_data false auto_mode sw_cmd_req 100 1 T19 1 T20 1 T21 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 4 8 66.67 4
Automatically Generated Cross Bins 12 4 8 66.67 4
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Element holes
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTNUMBERSTATUS
[auto[RES]] * * [boot_mode] [sw_cmd_req] -- -- 4


Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 250 1 T1 4 T2 4 T15 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 150 1 T19 1 T20 1 T21 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 400 1 T1 6 T2 6 T15 2
auto[RES] some_cmd_data false auto_mode reseed_cmd 50 1 T22 1 T23 1 T24 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 100 1 T1 2 T2 2 T44 2
auto[RES] no_cmd_data true auto_mode reseed_cmd 100 1 T19 1 T20 1 T21 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 100 1 T1 2 T2 2 T44 2
auto[RES] no_cmd_data false auto_mode reseed_cmd 100 1 T19 1 T20 1 T21 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 2 2 50.00 2
Automatically Generated Cross Bins 4 2 2 50.00 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Element holes
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTNUMBERSTATUS
[auto[UPD]] * [boot_mode] [sw_cmd_req] -- -- 2


Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 700 1 T1 11 T2 11 T15 3
auto[UPD] no_cmd_data sw_mode sw_cmd_req 50 1 T1 1 T2 1 T44 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 5160 1 T1 78 T2 78 T14 1
auto[UNI] boot_mode sw_cmd_req 300 1 T14 1 T16 1 T17 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 3 2 40.00 3
Automatically Generated Cross Bins 5 3 2 40.00 3
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Uncovered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTNUMBERSTATUS
[auto[RES]] [auto_mode] [sw_cmd_req] 0 1 1
[auto[UPD] , auto[UNI]] [auto_mode] [sw_cmd_req] -- -- 2


Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 250 1 T11 1 T19 1 T20 1
auto[GEN] auto_mode sw_cmd_req 100 1 T11 2 T42 2 T43 2


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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