Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	918345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6514350

1

T1

128910

T11

12

T12

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2047100	1			T1	37598		T11	50		T12	1
values[0x0]	2501670	1			T1	49462		T11	3		T12	11
values[0x1]	2883925	1			T1	56996		T11	8		T12	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	478390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6954305

1

T1

136662

T11

27

T12

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28350	1			T1	561		T2	561		T44	561
valid_sources[0x01]	31170	1			T1	599		T2	599		T15	2
valid_sources[0x02]	28600	1			T1	489		T2	489		T14	8
valid_sources[0x03]	32200	1			T1	607		T2	607		T15	4
valid_sources[0x04]	21700	1			T1	434		T2	434		T44	434
valid_sources[0x05]	30050	1			T1	597		T2	597		T15	2
valid_sources[0x06]	27670	1			T1	531		T11	11		T2	531
valid_sources[0x07]	29150	1			T1	548		T2	548		T15	11
valid_sources[0x08]	31410	1			T1	540		T11	1		T2	540
valid_sources[0x09]	24300	1			T1	480		T2	480		T44	480
valid_sources[0x0a]	32750	1			T1	655		T2	655		T44	655
valid_sources[0x0b]	32000	1			T1	612		T2	612		T15	20
valid_sources[0x0c]	23900	1			T1	470		T2	470		T44	470
valid_sources[0x0d]	30500	1			T1	599		T2	599		T15	7
valid_sources[0x0e]	26875	1			T1	450		T2	450		T14	9
valid_sources[0x0f]	30250	1			T1	599		T2	599		T15	6
valid_sources[0x10]	24850	1			T1	480		T2	480		T14	2
valid_sources[0x11]	27000	1			T1	538		T2	538		T44	538
valid_sources[0x12]	31675	1			T1	624		T2	624		T4	12
valid_sources[0x13]	33350	1			T1	659		T2	659		T15	8
valid_sources[0x14]	26500	1			T1	502		T2	502		T15	18
valid_sources[0x15]	32390	1			T1	528		T2	528		T14	12
valid_sources[0x16]	29050	1			T1	581		T2	581		T44	581
valid_sources[0x17]	27875	1			T1	554		T2	554		T71	15
valid_sources[0x18]	27850	1			T1	544		T2	544		T15	5
valid_sources[0x19]	30910	1			T1	610		T2	610		T15	1
valid_sources[0x1a]	32050	1			T1	596		T2	596		T14	6
valid_sources[0x1b]	26100	1			T1	497		T2	497		T15	22
valid_sources[0x1c]	29435	1			T1	582		T2	582		T84	7
valid_sources[0x1d]	32685	1			T1	651		T2	651		T84	7
valid_sources[0x1e]	26340	1			T1	506		T2	506		T15	8
valid_sources[0x1f]	34150	1			T1	662		T2	662		T15	19
valid_sources[0x20]	36150	1			T1	721		T2	721		T44	721
valid_sources[0x21]	29100	1			T1	582		T2	582		T44	582
valid_sources[0x22]	30600	1			T1	612		T2	612		T44	612
valid_sources[0x23]	35290	1			T1	696		T2	696		T15	7
valid_sources[0x24]	26450	1			T1	527		T2	527		T44	527
valid_sources[0x25]	29300	1			T1	586		T2	586		T44	586
valid_sources[0x26]	29335	1			T1	585		T2	585		T15	1
valid_sources[0x27]	27750	1			T1	533		T2	533		T14	2
valid_sources[0x28]	27500	1			T1	547		T2	547		T15	3
valid_sources[0x29]	27785	1			T1	540		T2	540		T15	7
valid_sources[0x2a]	29750	1			T1	593		T2	593		T44	593
valid_sources[0x2b]	24300	1			T1	486		T2	486		T44	486
valid_sources[0x2c]	29600	1			T1	590		T2	590		T44	590
valid_sources[0x2d]	29550	1			T1	583		T2	583		T15	8
valid_sources[0x2e]	30450	1			T1	551		T2	551		T14	5
valid_sources[0x2f]	26650	1			T1	531		T2	531		T44	531
valid_sources[0x30]	28250	1			T1	555		T2	555		T15	10
valid_sources[0x31]	28350	1			T1	547		T2	547		T15	10
valid_sources[0x32]	34100	1			T1	664		T2	664		T15	16
valid_sources[0x33]	33300	1			T1	662		T2	662		T44	662
valid_sources[0x34]	29800	1			T1	583		T2	583		T14	2
valid_sources[0x35]	23500	1			T1	463		T2	463		T15	5
valid_sources[0x36]	25570	1			T1	495		T2	495		T15	6
valid_sources[0x37]	28800	1			T1	560		T2	560		T15	8
valid_sources[0x38]	35950	1			T1	712		T2	712		T15	7
valid_sources[0x39]	31950	1			T1	632		T2	632		T15	1
valid_sources[0x3a]	32050	1			T1	632		T2	632		T15	9
valid_sources[0x3b]	29000	1			T1	575		T2	575		T15	1
valid_sources[0x3c]	27400	1			T1	540		T2	540		T15	8
valid_sources[0x3d]	28470	1			T1	559		T2	559		T76	21
valid_sources[0x3e]	26100	1			T1	521		T2	521		T15	1
valid_sources[0x3f]	28650	1			T1	562		T2	562		T15	9
valid_sources[0x40]	25900	1			T1	518		T2	518		T44	518
valid_sources[0x41]	28850	1			T1	562		T2	562		T15	11
valid_sources[0x42]	33350	1			T1	657		T2	657		T44	657
valid_sources[0x43]	34750	1			T1	644		T11	4		T2	644
valid_sources[0x44]	30100	1			T1	521		T2	521		T14	11
valid_sources[0x45]	31150	1			T1	614		T2	614		T15	9
valid_sources[0x46]	26400	1			T1	528		T2	528		T44	528
valid_sources[0x47]	31135	1			T1	611		T2	611		T15	11
valid_sources[0x48]	28850	1			T1	563		T2	563		T4	15
valid_sources[0x49]	33760	1			T1	592		T2	592		T14	13
valid_sources[0x4a]	34200	1			T1	677		T2	677		T15	7
valid_sources[0x4b]	28450	1			T1	556		T2	556		T15	9
valid_sources[0x4c]	28360	1			T1	545		T2	545		T15	5
valid_sources[0x4d]	27700	1			T1	551		T2	551		T15	1
valid_sources[0x4e]	28350	1			T1	567		T2	567		T44	567
valid_sources[0x4f]	31100	1			T1	609		T2	609		T14	2
valid_sources[0x50]	24300	1			T1	484		T2	484		T44	484
valid_sources[0x51]	23250	1			T1	443		T2	443		T15	18
valid_sources[0x52]	34340	1			T1	674		T2	674		T99	128
valid_sources[0x53]	26300	1			T1	520		T2	520		T14	1
valid_sources[0x54]	24650	1			T1	467		T2	467		T15	20
valid_sources[0x55]	29250	1			T1	585		T2	585		T44	585
valid_sources[0x56]	26300	1			T1	505		T2	505		T15	21
valid_sources[0x57]	32850	1			T1	652		T2	652		T15	1
valid_sources[0x58]	31750	1			T1	632		T2	632		T15	3
valid_sources[0x59]	28125	1			T1	557		T2	557		T68	12
valid_sources[0x5a]	27250	1			T1	545		T2	545		T44	545
valid_sources[0x5b]	28900	1			T1	492		T2	492		T14	14
valid_sources[0x5c]	21750	1			T1	415		T2	415		T14	3
valid_sources[0x5d]	25500	1			T1	508		T2	508		T15	2
valid_sources[0x5e]	30150	1			T1	601		T2	601		T44	601
valid_sources[0x5f]	28560	1			T1	553		T2	553		T15	16
valid_sources[0x60]	37950	1			T1	591		T2	591		T14	19
valid_sources[0x61]	28650	1			T1	567		T2	567		T44	567
valid_sources[0x62]	28910	1			T1	569		T2	569		T15	7
valid_sources[0x63]	36350	1			T1	700		T2	700		T15	17
valid_sources[0x64]	27350	1			T1	542		T2	542		T15	5
valid_sources[0x65]	28730	1			T1	537		T2	537		T4	15
valid_sources[0x66]	28040	1			T1	544		T2	544		T99	128
valid_sources[0x67]	29950	1			T1	594		T2	594		T15	5
valid_sources[0x68]	24800	1			T1	494		T2	494		T44	494
valid_sources[0x69]	30535	1			T1	603		T2	603		T14	1
valid_sources[0x6a]	32450	1			T1	646		T2	646		T15	3
valid_sources[0x6b]	30000	1			T1	600		T2	600		T44	600
valid_sources[0x6c]	23600	1			T1	429		T11	11		T2	429
valid_sources[0x6d]	24410	1			T1	477		T2	477		T15	2
valid_sources[0x6e]	32100	1			T1	636		T2	636		T15	2
valid_sources[0x6f]	25500	1			T1	501		T2	501		T15	1
valid_sources[0x70]	24410	1			T1	482		T2	482		T15	3
valid_sources[0x71]	23530	1			T1	467		T2	467		T68	9
valid_sources[0x72]	38050	1			T1	761		T2	761		T44	761
valid_sources[0x73]	36050	1			T1	711		T2	711		T44	711
valid_sources[0x74]	25750	1			T1	499		T2	499		T15	6
valid_sources[0x75]	29210	1			T1	555		T2	555		T14	4
valid_sources[0x76]	37550	1			T1	696		T2	696		T14	8
valid_sources[0x77]	32530	1			T1	628		T2	628		T15	21
valid_sources[0x78]	27060	1			T1	509		T2	509		T15	20
valid_sources[0x79]	29500	1			T1	590		T2	590		T44	590
valid_sources[0x7a]	39550	1			T1	706		T2	706		T14	13
valid_sources[0x7b]	35050	1			T1	691		T2	691		T15	6
valid_sources[0x7c]	26900	1			T1	533		T2	533		T15	5
valid_sources[0x7d]	31210	1			T1	619		T2	619		T15	4
valid_sources[0x7e]	26220	1			T1	520		T2	520		T15	2
valid_sources[0x7f]	27130	1			T1	531		T2	531		T15	7
valid_sources[0x80]	31935	1			T1	588		T2	588		T14	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1622345

1

T1

32083

T11

7

T2

32083

values[0x0]

all_enables

biggest_size

2448775

1

T1

48499

T11

3

T12

6

values[0x1]

all_enables

biggest_size

2443230

1

T1

48328

T11

2

T2

48328