Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
71.43	75.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[edn_reg_block]	75.00	1	100	1	64	64

---

Group Instance : tl_intg_err_cgs_wrap[edn_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_cgs_wrap[edn_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	4	10	75.00

Variables for Group Instance tl_intg_err_cgs_wrap[edn_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	2	2	50.00	100	1	1	0
cp_num_data_err_bits	4	1	3	75.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
[auto[1]]	0	0			-	-		-	-		-	-
auto[0]	20833065	0			T1	411611		T11	61		T12	24

---

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_num_cmd_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[1]	0	1	1
values[2]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0]

20832825

1

T1

411611

T11

61

T12

24

values[3]

140

1

T4

7

T6

7

T8

7

---

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	1	3	75.00

User Defined Bins for cp_num_data_err_bits

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	20832825	1			T1	411611		T11	61		T12	24
values[1]	40	1			T4	2		T6	2		T8	2
values[3]	120	1			T4	6		T6	6		T8	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20832665	1			T1	411611		T11	61		T12	24
auto[TlIntgErrCmd]	160	1			T4	8		T6	8		T8	8
auto[TlIntgErrData]	160	1			T4	8		T6	8		T8	8
auto[TlIntgErrBoth]	80	1			T4	4		T6	4		T8	4