Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.19	92.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	92.19	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.19	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	5	47	90.38

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	5	47	90.38	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	3250	1		T1	48	T2	48	T14	1
non_zero_bins[1]	3300	1		T1	41	T2	41	T14	1
zero	11530	1		T1	161	T11	3	T2	161

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	750	1		T1	12	T2	12	T15	3
uni	5460	1		T1	78	T2	78	T14	2
gen	5160	1		T1	68	T11	2	T2	68
res	1000	1		T1	14	T2	14	T15	3
ins	5710	1		T1	78	T11	1	T2	78

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

12680

178

T14

mubi_true

5400

T11

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

10080

129

T11

129

pass

8000

121

T14

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	5	47	90.38	5
Automatically Generated Cross Bins	52	5	47	90.38	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	[zero]	[fail]	*	--	--	2

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	[non_zero_bins[1]]	[pass]	[mubi_true]	0	1	1
[upd]	[zero]	[pass]	[mubi_true]	0	1	1
[res]	[non_zero_bins[0]]	[pass]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	100	1		T1	2	T2	2	T44	2
upd	non_zero_bins[0]	fail	mubi_true	50	1		T1	1	T2	1	T44	1
upd	non_zero_bins[0]	pass	mubi_false	200	1		T1	4	T2	4	T44	4
upd	non_zero_bins[0]	pass	mubi_true	50	1		T1	1	T2	1	T44	1
upd	non_zero_bins[1]	fail	mubi_false	100	1		T1	1	T2	1	T15	1
upd	non_zero_bins[1]	fail	mubi_true	150	1		T1	1	T2	1	T15	2
upd	non_zero_bins[1]	pass	mubi_false	50	1		T1	1	T2	1	T44	1
upd	zero	pass	mubi_false	50	1		T1	1	T2	1	T44	1
uni	zero	fail	mubi_false	1910	1		T1	26	T2	26	T14	1
uni	zero	fail	mubi_true	600	1		T1	9	T2	9	T15	2
uni	zero	pass	mubi_false	2250	1		T1	32	T2	32	T14	1
uni	zero	pass	mubi_true	700	1		T1	11	T2	11	T15	3
gen	non_zero_bins[0]	fail	mubi_false	200	1		T1	4	T2	4	T44	4
gen	non_zero_bins[0]	fail	mubi_true	400	1		T1	5	T2	5	T15	3
gen	non_zero_bins[0]	pass	mubi_false	250	1		T1	3	T2	3	T15	2
gen	non_zero_bins[0]	pass	mubi_true	200	1		T1	3	T2	3	T15	1
gen	non_zero_bins[1]	fail	mubi_false	500	1		T1	4	T2	4	T14	1
gen	non_zero_bins[1]	fail	mubi_true	400	1		T1	6	T2	6	T15	1
gen	non_zero_bins[1]	pass	mubi_false	250	1		T1	3	T2	3	T15	2
gen	non_zero_bins[1]	pass	mubi_true	150	1		T1	2	T2	2	T44	2
gen	zero	fail	mubi_false	1560	1		T1	15	T2	15	T14	1
gen	zero	fail	mubi_true	250	1		T1	3	T11	2	T2	3
gen	zero	pass	mubi_false	950	1		T1	19	T2	19	T44	19
gen	zero	pass	mubi_true	50	1		T1	1	T2	1	T44	1
res	non_zero_bins[0]	fail	mubi_false	50	1		T15	1	T97	1	T85	1
res	non_zero_bins[0]	fail	mubi_true	50	1		T1	1	T2	1	T44	1
res	non_zero_bins[0]	pass	mubi_false	100	1		T1	2	T2	2	T44	2
res	non_zero_bins[1]	fail	mubi_false	50	1		T1	1	T2	1	T44	1
res	non_zero_bins[1]	fail	mubi_true	200	1		T1	2	T2	2	T44	2
res	non_zero_bins[1]	pass	mubi_false	200	1		T1	3	T2	3	T15	1
res	non_zero_bins[1]	pass	mubi_true	150	1		T1	1	T2	1	T15	1
res	zero	fail	mubi_false	50	1		T1	1	T2	1	T44	1
res	zero	fail	mubi_true	50	1		T1	1	T2	1	T44	1
res	zero	pass	mubi_false	50	1		T1	1	T2	1	T44	1
res	zero	pass	mubi_true	50	1		T1	1	T2	1	T44	1
ins	non_zero_bins[0]	fail	mubi_false	450	1		T1	8	T2	8	T15	1
ins	non_zero_bins[0]	fail	mubi_true	450	1		T1	7	T2	7	T15	1
ins	non_zero_bins[0]	pass	mubi_false	500	1		T1	3	T2	3	T14	1
ins	non_zero_bins[0]	pass	mubi_true	200	1		T1	4	T2	4	T44	4
ins	non_zero_bins[1]	fail	mubi_false	400	1		T1	6	T2	6	T15	2
ins	non_zero_bins[1]	fail	mubi_true	250	1		T1	4	T2	4	T15	1
ins	non_zero_bins[1]	pass	mubi_false	250	1		T1	3	T2	3	T15	2
ins	non_zero_bins[1]	pass	mubi_true	200	1		T1	3	T2	3	T15	1
ins	zero	fail	mubi_false	1160	1		T1	17	T2	17	T15	4
ins	zero	fail	mubi_true	700	1		T1	4	T11	1	T2	4
ins	zero	pass	mubi_false	1050	1		T1	18	T2	18	T15	3
ins	zero	pass	mubi_true	100	1		T1	1	T2	1	T15	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded