Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_output	89.81	100.00	69.23			90.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.19	100.00	80.77			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.06	100.00	69.23			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	100.00	79.72			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	100.00	79.72			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	100.00	79.72			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T19,T20,T21

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T11,T12

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T11,T12

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T22,T23,T24
1	1	0	Not Covered
1	1	1	Covered	T1,T14,T16

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T14,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T14,T16

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T11,T12
1	1	Covered	T1,T11,T12

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Not Covered
1	1	Covered	T1,T14,T16

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T19,T20,T21

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T1,T11,T12

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T14,T16
1	Covered	T1,T11,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T20,T21
0	1	Covered	T1,T11,T12
0	0	Covered	T1,T2,T14

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T14,T16

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
0	0	Covered	T1,T11,T12

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T16
0	Covered	T1,T11,T12

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	631454280	264090	0	0
DepthKnown_A	631795980	631272450	0	0
RvalidKnown_A	631795980	631272450	0	0
WreadyKnown_A	631795980	631272450	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	631795980	333790	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631454280	264090	0	0
T1	417080	1147	0	0
T2	417080	1147	0	0
T11	1823	3	0	0
T12	1352	0	0	0
T13	1352	0	0	0
T14	3594	42	0	0
T15	30892	343	0	0
T16	3594	42	0	0
T17	3594	42	0	0
T18	2438	28	0	0
T19	135	25	0	0
T20	135	25	0	0
T21	135	25	0	0
T22	0	1624	0	0
T25	148	3	0	0
T26	148	0	0	0
T28	0	20	0	0
T34	0	25	0	0
T35	0	25	0	0
T37	1797	10	0	0
T38	1303	0	0	0
T39	0	10	0	0
T40	0	10	0	0
T45	1352	0	0	0
T56	1797	42	0	0
T57	0	10	0	0
T85	15446	0	0	0
T86	1797	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631795980	631272450	0	0
T1	1251240	1251207	0	0
T2	1251240	1251207	0	0
T11	5469	5283	0	0
T12	4056	3870	0	0
T13	4056	3870	0	0
T14	5391	5205	0	0
T15	46338	43872	0	0
T16	5391	5205	0	0
T17	5391	5205	0	0
T18	3657	3477	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631795980	631272450	0	0
T1	1251240	1251207	0	0
T2	1251240	1251207	0	0
T11	5469	5283	0	0
T12	4056	3870	0	0
T13	4056	3870	0	0
T14	5391	5205	0	0
T15	46338	43872	0	0
T16	5391	5205	0	0
T17	5391	5205	0	0
T18	3657	3477	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	631795980	631272450	0	0
T1	1251240	1251207	0	0
T2	1251240	1251207	0	0
T11	5469	5283	0	0
T12	4056	3870	0	0
T13	4056	3870	0	0
T14	5391	5205	0	0
T15	46338	43872	0	0
T16	5391	5205	0	0
T17	5391	5205	0	0
T18	3657	3477	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	631795980	333790	0	0
T1	417080	1147	0	0
T2	417080	1147	0	0
T11	1823	3	0	0
T12	1352	0	0	0
T13	1352	0	0	0
T14	3594	42	0	0
T15	30892	343	0	0
T16	3594	42	0	0
T17	3594	42	0	0
T18	2438	28	0	0
T19	997	364	0	0
T20	997	364	0	0
T21	997	364	0	0
T22	0	1624	0	0
T25	1841	3	0	0
T26	1841	0	0	0
T28	0	20	0	0
T34	0	364	0	0
T35	0	364	0	0
T37	1797	10	0	0
T38	1303	0	0	0
T39	0	10	0	0
T40	0	10	0	0
T45	1352	0	0	0
T56	1797	42	0	0
T57	0	10	0	0
T85	15446	0	0	0
T86	1797	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T11,T12

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T11,T12

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T2

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T11,T2
1	1	0	Not Covered
1	1	1	Covered	T1,T11,T2

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T11,T12
1	1	Covered	T1,T11,T12

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Not Covered
1	1	Covered	T1,T11,T2

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T1,T11,T12

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T11,T2
1	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T11,T12
0	0	Covered	T1,T2,T14

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T1,T11,T2

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
0	0	Covered	T1,T11,T12

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T2
0	Covered	T1,T11,T12

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210598660	90540	0	0
DepthKnown_A	210598660	210424150	0	0
RvalidKnown_A	210598660	210424150	0	0
WreadyKnown_A	210598660	210424150	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	210598660	90540	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	90540	0	0
T1	417080	1147	0	0
T2	417080	1147	0	0
T11	1823	3	0	0
T12	1352	0	0	0
T13	1352	0	0	0
T14	1797	32	0	0
T15	15446	343	0	0
T16	1797	32	0	0
T17	1797	32	0	0
T18	1219	8	0	0
T25	0	3	0	0
T56	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	90540	0	0
T1	417080	1147	0	0
T2	417080	1147	0	0
T11	1823	3	0	0
T12	1352	0	0	0
T13	1352	0	0	0
T14	1797	32	0	0
T15	15446	343	0	0
T16	1797	32	0	0
T17	1797	32	0	0
T18	1219	8	0	0
T25	0	3	0	0
T56	0	32	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	26	21	80.77
Logical	26	21	80.77
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T22,T23,T24

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T11,T12

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T11,T12

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T19,T20,T21

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T20,T21
1	1	0	Not Covered
1	1	1	Covered	T22,T23,T24

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T1,T11,T12
1	1	Covered	T1,T11,T12

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Not Covered
1	1	Covered	T19,T20,T21

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T22,T23,T24

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T1,T11,T12

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T22,T23,T24
0	1	Covered	T1,T11,T12
0	0	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
0	0	Covered	T1,T11,T12

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T1,T11,T12

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210427810	83700	0	0
DepthKnown_A	210598660	210424150	0	0
RvalidKnown_A	210598660	210424150	0	0
WreadyKnown_A	210598660	210424150	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	210598660	117600	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210427810	83700	0	0
T19	135	25	0	0
T20	135	25	0	0
T21	135	25	0	0
T22	0	1624	0	0
T34	135	25	0	0
T35	0	25	0	0
T45	1352	0	0	0
T85	15446	0	0	0
T86	1797	0	0	0
T87	0	25	0	0
T88	0	25	0	0
T89	0	25	0	0
T90	0	25	0	0
T91	1797	0	0	0
T92	1173	0	0	0
T93	1303	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	117600	0	0
T19	997	364	0	0
T20	997	364	0	0
T21	997	364	0	0
T22	0	1624	0	0
T34	997	364	0	0
T35	0	364	0	0
T45	1352	0	0	0
T85	15446	0	0	0
T86	1797	0	0	0
T87	0	364	0	0
T88	0	364	0	0
T89	0	364	0	0
T90	0	364	0	0
T91	1797	0	0	0
T92	1173	0	0	0
T93	1303	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	26	22	84.62
Logical	26	22	84.62
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T19,T20,T21

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T11,T12

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T11,T12

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T22,T23,T24
1	1	0	Not Covered
1	1	1	Covered	T14,T16,T17

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T16,T17
1	1	0	Not Covered
1	1	1	Covered	T14,T16,T17

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T1,T11,T12
1	1	Covered	T1,T11,T12

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T12
1	0	Not Covered
1	1	Covered	T14,T16,T17

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T19,T20,T21

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T1,T11,T12

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T14,T16,T17
1	Covered	T1,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T20,T21
0	1	Covered	T1,T11,T12
0	0	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T12
0	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T11,T12
0	1	Covered	T1,T11,T12
0	0	Covered	T1,T11,T12

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T17
0	Covered	T1,T11,T12

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	210427810	89850	0	0
DepthKnown_A	210598660	210424150	0	0
RvalidKnown_A	210598660	210424150	0	0
WreadyKnown_A	210598660	210424150	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	210598660	125650	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210427810	89850	0	0
T14	1797	10	0	0
T15	15446	0	0	0
T16	1797	10	0	0
T17	1797	10	0	0
T18	1219	20	0	0
T25	148	0	0	0
T26	148	0	0	0
T28	0	20	0	0
T37	1797	10	0	0
T38	1303	0	0	0
T39	0	10	0	0
T40	0	10	0	0
T56	1797	10	0	0
T57	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	125650	0	0
T14	1797	10	0	0
T15	15446	0	0	0
T16	1797	10	0	0
T17	1797	10	0	0
T18	1219	20	0	0
T25	1841	0	0	0
T26	1841	0	0	0
T28	0	20	0	0
T37	1797	10	0	0
T38	1303	0	0	0
T39	0	10	0	0
T40	0	10	0	0
T56	1797	10	0	0
T57	0	10	0	0