Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27		83.33	96.49			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.27		83.33	96.49			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.27		83.33	96.49			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.03	98.64	88.52	94.40	59.21	96.62	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	12.50						12.50
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	94.54	100.00				85.71	97.90
u_edn_core	85.28	99.77	85.67	69.31	59.21	98.82	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.80	96.04	95.27	100.00		92.69	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Not Covered
1	0	Covered	T11,T42,T43

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T30,T31,T32
1	0	Covered	T25,T26,T27

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	61	88.41
Total Bits	1168	1127	96.49
Total Bits 0->1	584	574	98.29
Total Bits 1->0	584	553	94.69

Ports	69	61	88.41
Port Bits	1168	1127	96.49
Port Bits 0->1	584	574	98.29
Port Bits 1->0	584	553	94.69

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
rst_ni	Yes	Yes	T1,T2,T15	Yes	T1,T11,T12	INPUT
tl_i.d_ready	Yes	Yes	T1,T12,T13	Yes	T1,T11,T12	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_i.a_valid	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
tl_o.a_ready	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T11,*T12	Yes	T1,T11,T12	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T11,*T2	Yes	T1,T11,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
edn_i[1].edn_req	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	INPUT
edn_i[2].edn_req	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	INPUT
edn_i[3].edn_req	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	INPUT
edn_i[4].edn_req	Yes	Yes	T11,T14,T16	Yes	T11,T14,T16	INPUT
edn_i[5].edn_req	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
edn_o[1].edn_bus[8:0]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[9]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[10]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[11]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[15:12]	Yes	Yes	T25,T26,T27	Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[16]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[17]	No	No		No		OUTPUT
edn_o[1].edn_bus[21:18]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[22]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[29:23]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_bus[30]	No	No		No		OUTPUT
edn_o[1].edn_bus[31]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[0]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[1]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[3:2]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[4]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[5]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[6]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[10:7]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[12:11]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[13]	No	No		No		OUTPUT
edn_o[2].edn_bus[16:14]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[17]	No	No		No		OUTPUT
edn_o[2].edn_bus[18]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[19]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[20]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[21]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[22]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[28:23]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[29]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[30]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_bus[31]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[2].edn_fips	No	No		No		OUTPUT
edn_o[2].edn_ack	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[8:0]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[9]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[10]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[11]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[12]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[13]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[14]	Yes	Yes	*T14,*T16,*T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[15]	No	No		No		OUTPUT
edn_o[3].edn_bus[16]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[19:17]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[20]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[27:21]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[28]	No	No		Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_bus[31:29]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[3].edn_fips	No	No		No		OUTPUT
edn_o[3].edn_ack	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T11,T14,T16	Yes	T11,T14,T16	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T11,T14,T16	Yes	T11,T14,T16	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	OUTPUT
edn_o[6].edn_bus[23:0]	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	OUTPUT
edn_o[6].edn_bus[24]	No	No		No		OUTPUT
edn_o[6].edn_bus[26:25]	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	OUTPUT
edn_o[6].edn_bus[27]	No	No		No		OUTPUT
edn_o[6].edn_bus[31:28]	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	OUTPUT
edn_o[6].edn_fips	No	No		No		OUTPUT
edn_o[6].edn_ack	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T11,T2	Yes	T1,T11,T2	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T12,T13,T25	Yes	T12,T13,T25	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T11,T12	Yes	T1,T11,T12	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T12,T13,T25	Yes	T12,T13,T25	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	210598660	210424150	0	0
CsrngAppIfOut_A	210598660	210424150	0	0
FpvSecCmCntAlertCheck_A	210598660	250	0	0
FpvSecCmMainFsmCheck_A	210598660	100	0	0
FpvSecCmRegWeOnehotCheck_A	210598660	100	0	0
IntrEdnCmdReqDoneKnownO_A	210598660	210424150	0	0
TlAReadyKnownO_A	210598660	210424150	0	0
TlDValidKnownO_A	210598660	210424150	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	210598660	100	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[0].EdnDataStable_A	210598660	8130	0	360
gen_edn_if_asserts[0].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	210598660	173290	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[1].EdnDataStable_A	210598660	900	0	300
gen_edn_if_asserts[1].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	210598660	173290	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[2].EdnDataStable_A	210598660	900	0	300
gen_edn_if_asserts[2].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	210598660	173290	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[3].EdnDataStable_A	210598660	900	0	300
gen_edn_if_asserts[3].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	210598660	173290	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[4].EdnDataStable_A	210598660	4700	0	350
gen_edn_if_asserts[4].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	210598660	173290	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[5].EdnDataStable_A	210598660	6750	0	300
gen_edn_if_asserts[5].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	210598660	173290	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	210598660	435620	0	0
gen_edn_if_asserts[6].EdnDataStable_A	210598660	150	0	0
gen_edn_if_asserts[6].EdnEndPointOut_A	210598660	210424150	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	210598660	173290	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	250	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	1841	1	0	0
T26	1841	1	0	0
T27	1841	1	0	0
T28	1219	0	0	0
T33	1841	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	100	0	0
T30	34426	20	0	0
T31	34426	20	0	0
T32	0	20	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	1797	0	0	0
T49	1841	0	0	0
T50	1797	0	0	0
T51	1797	0	0	0
T52	1797	0	0	0
T53	997	0	0	0
T54	1303	0	0	0
T55	1797	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	8130	0	360
T1	417080	122	0	0
T2	417080	122	0	0
T11	1823	0	0	0
T12	1352	0	0	0
T13	1352	0	0	0
T14	1797	3	0	1
T15	15446	19	0	0
T16	1797	3	0	1
T17	1797	3	0	1
T18	1219	0	0	0
T37	0	3	0	1
T38	0	3	0	1
T39	0	0	0	1
T40	0	0	0	1
T41	0	0	0	1
T44	0	122	0	0
T56	0	3	0	1
T57	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	900	0	300
T14	1797	3	0	1
T15	15446	0	0	0
T16	1797	3	0	1
T17	1797	3	0	1
T18	1219	0	0	0
T25	1841	0	0	0
T26	1841	0	0	0
T37	1797	3	0	1
T38	1303	0	0	0
T39	0	3	0	1
T40	0	3	0	1
T41	0	3	0	1
T56	1797	3	0	1
T57	0	3	0	1
T58	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	900	0	300
T14	1797	3	0	1
T15	15446	0	0	0
T16	1797	3	0	1
T17	1797	3	0	1
T18	1219	0	0	0
T25	1841	0	0	0
T26	1841	0	0	0
T37	1797	3	0	1
T38	1303	0	0	0
T39	0	3	0	1
T40	0	3	0	1
T41	0	3	0	1
T56	1797	3	0	1
T57	0	3	0	1
T58	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	900	0	300
T14	1797	3	0	1
T15	15446	0	0	0
T16	1797	3	0	1
T17	1797	3	0	1
T18	1219	0	0	0
T25	1841	0	0	0
T26	1841	0	0	0
T37	1797	3	0	1
T38	1303	0	0	0
T39	0	3	0	1
T40	0	3	0	1
T41	0	3	0	1
T56	1797	3	0	1
T57	0	3	0	1
T58	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	4700	0	350
T2	417080	0	0	0
T11	1823	4	0	1
T12	1352	0	0	0
T13	1352	0	0	0
T14	1797	15	0	1
T15	15446	0	0	0
T16	1797	15	0	1
T17	1797	15	0	1
T18	1219	0	0	0
T37	0	15	0	1
T39	0	15	0	1
T40	0	15	0	1
T41	0	15	0	1
T56	1797	15	0	1
T57	0	15	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	6750	0	300
T14	1797	22	0	1
T15	15446	0	0	0
T16	1797	22	0	1
T17	1797	22	0	1
T18	1219	0	0	0
T25	1841	0	0	0
T26	1841	0	0	0
T37	1797	22	0	1
T38	1303	0	0	0
T39	0	22	0	1
T40	0	22	0	1
T41	0	22	0	1
T56	1797	22	0	1
T57	0	22	0	1
T58	0	22	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	435620	0	0
T1	417080	1556	0	0
T2	417080	1556	0	0
T11	1823	13	0	0
T12	1352	1289	0	0
T13	1352	1289	0	0
T14	1797	17	0	0
T15	15446	924	0	0
T16	1797	17	0	0
T17	1797	17	0	0
T18	1219	33	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	150	0	0
T18	1219	3	0	0
T25	1841	0	0	0
T26	1841	0	0	0
T28	1219	3	0	0
T29	0	3	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T41	1797	0	0	0
T56	1797	0	0	0
T58	1797	0	0	0
T59	0	3	0	0
T60	0	3	0	0
T61	0	3	0	0
T62	0	3	0	0
T63	0	3	0	0
T64	0	3	0	0
T65	0	3	0	0
T66	1797	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	210424150	0	0
T1	417080	417069	0	0
T2	417080	417069	0	0
T11	1823	1761	0	0
T12	1352	1290	0	0
T13	1352	1290	0	0
T14	1797	1735	0	0
T15	15446	14624	0	0
T16	1797	1735	0	0
T17	1797	1735	0	0
T18	1219	1159	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210598660	173290	0	0
T19	0	532	0	0
T20	0	532	0	0
T21	0	532	0	0
T25	1841	1110	0	0
T26	1841	1110	0	0
T27	1841	1110	0	0
T28	1219	0	0	0
T33	1841	1110	0	0
T34	0	532	0	0
T35	0	532	0	0
T36	0	1110	0	0
T37	1797	0	0	0
T38	1303	0	0	0
T39	1797	0	0	0
T40	1797	0	0	0
T41	1797	0	0	0