Group : tb.dut.u_edn_cov_if::edn_cfg_cg
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Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
33.33 33.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 33.33 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
33.33 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 6 6 50.00
Crosses 21 16 5 23.81


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 1 1 50.00 100 1 1 0
cp_num_endpoints 7 5 2 28.57 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 16 5 23.81 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 350 1 T17 1 T25 1 T26 1
auto_req_mode 50 1 T21 1 T22 1 T23 1
sw_mode 4210 1 T16 1 T20 15 T1 68



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_num_boot_reqs

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
single 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 400 1 T17 1 T25 1 T21 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 5 2 28.57


Automatically Generated Bins for cp_num_endpoints

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[2] - auto[6]] -- -- 5


Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 160 1 T16 1 T21 1 T22 1
auto[7] 4450 1 T17 1 T25 1 T26 1



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 16 5 23.81 16


Automatically Generated Cross Bins for cr_num_endpoints_mode

Element holes
cp_num_endpointscp_modeCOUNTAT LEASTNUMBERSTATUS
[auto[2] - auto[6]] * -- -- 15


Uncovered bins
cp_num_endpointscp_modeCOUNTAT LEASTNUMBERSTATUS
[auto[7]] [auto_req_mode] 0 1 1


Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 50 1 T27 1 T28 1 T29 1
auto[1] auto_req_mode 50 1 T21 1 T22 1 T23 1
auto[1] sw_mode 60 1 T16 1 T97 1 T72 1
auto[7] boot_req_mode 300 1 T17 1 T25 1 T26 1
auto[7] sw_mode 4150 1 T20 15 T1 68 T34 15

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