Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	918345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6514050

1

T16

5

T17

29

T18

55

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2047100	1			T16	42		T17	212		T18	262
values[0x0]	2501420	1			T16	3		T17	8		T18	26
values[0x1]	2883875	1			T16	4		T17	20		T18	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	478290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6954105

1

T16

21

T17

103

T18

148

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28350	1			T18	3		T19	3		T1	561
valid_sources[0x01]	31170	1			T18	2		T19	2		T20	2
valid_sources[0x02]	28600	1			T17	8		T18	3		T25	8
valid_sources[0x03]	32200	1			T16	13		T18	4		T19	4
valid_sources[0x04]	21700	1			T1	434		T44	434		T45	434
valid_sources[0x05]	30050	1			T18	1		T19	1		T20	2
valid_sources[0x06]	27670	1			T18	4		T19	4		T20	3
valid_sources[0x07]	29150	1			T18	6		T21	12		T19	6
valid_sources[0x08]	31410	1			T17	12		T18	3		T25	12
valid_sources[0x09]	24200	1			T18	2		T19	2		T1	480
valid_sources[0x0a]	32750	1			T1	655		T44	655		T45	655
valid_sources[0x0b]	32000	1			T18	4		T19	4		T20	20
valid_sources[0x0c]	23900	1			T18	4		T19	4		T1	470
valid_sources[0x0d]	30500	1			T18	2		T19	2		T20	7
valid_sources[0x0e]	26575	1			T17	9		T18	3		T25	9
valid_sources[0x0f]	30250	1			T20	6		T1	599		T34	6
valid_sources[0x10]	24850	1			T17	2		T25	2		T26	2
valid_sources[0x11]	27000	1			T18	1		T19	1		T1	538
valid_sources[0x12]	31675	1			T18	2		T19	2		T1	624
valid_sources[0x13]	33350	1			T20	8		T1	659		T34	8
valid_sources[0x14]	26300	1			T21	6		T20	18		T1	502
valid_sources[0x15]	32390	1			T17	12		T18	3		T25	12
valid_sources[0x16]	29050	1			T1	581		T44	581		T45	581
valid_sources[0x17]	27875	1			T18	1		T19	1		T1	554
valid_sources[0x18]	27850	1			T18	3		T21	2		T19	3
valid_sources[0x19]	30910	1			T18	2		T19	2		T20	1
valid_sources[0x1a]	32050	1			T17	6		T18	1		T25	6
valid_sources[0x1b]	26100	1			T21	3		T20	22		T1	497
valid_sources[0x1c]	29435	1			T18	3		T19	3		T1	582
valid_sources[0x1d]	32685	1			T18	1		T19	1		T1	651
valid_sources[0x1e]	25940	1			T20	8		T1	506		T49	12
valid_sources[0x1f]	34200	1			T18	1		T21	1		T19	1
valid_sources[0x20]	36150	1			T18	1		T19	1		T1	721
valid_sources[0x21]	29100	1			T1	582		T44	582		T45	582
valid_sources[0x22]	30600	1			T1	612		T44	612		T45	612
valid_sources[0x23]	35290	1			T20	7		T1	696		T49	7
valid_sources[0x24]	26450	1			T18	1		T19	1		T1	527
valid_sources[0x25]	29300	1			T1	586		T44	586		T45	586
valid_sources[0x26]	29335	1			T20	1		T1	585		T99	7
valid_sources[0x27]	27750	1			T17	2		T18	2		T25	2
valid_sources[0x28]	27500	1			T20	3		T1	547		T34	3
valid_sources[0x29]	27785	1			T18	2		T19	2		T20	7
valid_sources[0x2a]	29750	1			T18	1		T19	1		T1	593
valid_sources[0x2b]	24300	1			T1	486		T44	486		T45	486
valid_sources[0x2c]	29600	1			T18	1		T19	1		T1	590
valid_sources[0x2d]	29550	1			T20	8		T1	583		T34	8
valid_sources[0x2e]	30450	1			T17	5		T25	5		T26	5
valid_sources[0x2f]	26650	1			T18	1		T19	1		T1	531
valid_sources[0x30]	28250	1			T20	10		T1	555		T34	10
valid_sources[0x31]	28350	1			T18	5		T19	5		T20	10
valid_sources[0x32]	34100	1			T18	1		T19	1		T20	16
valid_sources[0x33]	33300	1			T18	2		T19	2		T1	662
valid_sources[0x34]	29800	1			T17	2		T25	2		T26	2
valid_sources[0x35]	23500	1			T18	1		T19	1		T20	5
valid_sources[0x36]	25570	1			T20	6		T1	495		T4	26
valid_sources[0x37]	28800	1			T18	4		T19	4		T20	8
valid_sources[0x38]	35950	1			T20	7		T1	712		T34	7
valid_sources[0x39]	31950	1			T20	1		T1	632		T4	15
valid_sources[0x3a]	32050	1			T20	9		T1	632		T34	9
valid_sources[0x3b]	29000	1			T18	2		T19	2		T20	1
valid_sources[0x3c]	27400	1			T20	8		T1	540		T34	8
valid_sources[0x3d]	28470	1			T18	1		T19	1		T1	559
valid_sources[0x3e]	26100	1			T20	1		T1	521		T34	1
valid_sources[0x3f]	28650	1			T18	1		T19	1		T20	9
valid_sources[0x40]	25900	1			T1	518		T44	518		T45	518
valid_sources[0x41]	28850	1			T18	2		T19	2		T20	11
valid_sources[0x42]	33350	1			T18	5		T19	5		T1	657
valid_sources[0x43]	34750	1			T17	7		T25	7		T26	7
valid_sources[0x44]	30100	1			T17	11		T18	5		T25	11
valid_sources[0x45]	31150	1			T20	9		T1	614		T34	9
valid_sources[0x46]	26400	1			T1	528		T44	528		T45	528
valid_sources[0x47]	31135	1			T20	11		T1	611		T99	7
valid_sources[0x48]	28850	1			T18	4		T19	4		T1	563
valid_sources[0x49]	33760	1			T17	13		T18	1		T25	13
valid_sources[0x4a]	34200	1			T20	7		T1	677		T34	7
valid_sources[0x4b]	28450	1			T18	2		T19	2		T20	9
valid_sources[0x4c]	28360	1			T18	7		T19	7		T20	5
valid_sources[0x4d]	27700	1			T18	1		T19	1		T20	1
valid_sources[0x4e]	28350	1			T1	567		T44	567		T45	567
valid_sources[0x4f]	31100	1			T17	2		T25	2		T26	2
valid_sources[0x50]	24300	1			T18	1		T19	1		T1	484
valid_sources[0x51]	23250	1			T18	2		T19	2		T20	18
valid_sources[0x52]	34340	1			T1	674		T100	128		T101	128
valid_sources[0x53]	26300	1			T17	1		T25	1		T26	1
valid_sources[0x54]	24650	1			T18	3		T19	3		T20	20
valid_sources[0x55]	29250	1			T1	585		T44	585		T45	585
valid_sources[0x56]	26300	1			T20	21		T1	505		T34	21
valid_sources[0x57]	32850	1			T18	2		T19	2		T20	1
valid_sources[0x58]	31750	1			T20	3		T1	632		T34	3
valid_sources[0x59]	28125	1			T1	557		T49	12		T15	12
valid_sources[0x5a]	27350	1			T21	2		T1	545		T44	545
valid_sources[0x5b]	28900	1			T17	14		T18	1		T25	14
valid_sources[0x5c]	21750	1			T17	3		T18	1		T25	3
valid_sources[0x5d]	25500	1			T20	2		T1	508		T34	2
valid_sources[0x5e]	30150	1			T18	1		T19	1		T1	601
valid_sources[0x5f]	28460	1			T20	16		T1	553		T34	16
valid_sources[0x60]	37600	1			T16	5		T17	19		T25	19
valid_sources[0x61]	28650	1			T18	3		T19	3		T1	567
valid_sources[0x62]	28910	1			T18	1		T19	1		T20	7
valid_sources[0x63]	36350	1			T18	5		T19	5		T20	17
valid_sources[0x64]	27350	1			T20	5		T1	542		T34	5
valid_sources[0x65]	28730	1			T18	3		T19	3		T1	537
valid_sources[0x66]	28690	1			T18	2		T21	13		T19	2
valid_sources[0x67]	29950	1			T20	5		T1	594		T34	5
valid_sources[0x68]	24800	1			T18	1		T19	1		T1	494
valid_sources[0x69]	30535	1			T17	1		T25	1		T26	1
valid_sources[0x6a]	32450	1			T20	3		T1	646		T34	3
valid_sources[0x6b]	30000	1			T1	600		T44	600		T45	600
valid_sources[0x6c]	23600	1			T20	25		T24	7		T1	429
valid_sources[0x6d]	24410	1			T18	1		T19	1		T20	2
valid_sources[0x6e]	32100	1			T18	2		T19	2		T20	2
valid_sources[0x6f]	25500	1			T18	1		T19	1		T20	1
valid_sources[0x70]	24410	1			T18	1		T19	1		T20	3
valid_sources[0x71]	23530	1			T1	467		T49	9		T15	9
valid_sources[0x72]	38050	1			T1	761		T44	761		T45	761
valid_sources[0x73]	36050	1			T18	5		T19	5		T1	711
valid_sources[0x74]	25750	1			T18	5		T19	5		T20	6
valid_sources[0x75]	29210	1			T17	4		T25	4		T26	4
valid_sources[0x76]	37550	1			T17	8		T18	3		T25	8
valid_sources[0x77]	32530	1			T20	21		T1	628		T49	4
valid_sources[0x78]	27060	1			T18	6		T19	6		T20	20
valid_sources[0x79]	29500	1			T1	590		T44	590		T45	590
valid_sources[0x7a]	39500	1			T17	13		T18	3		T25	13
valid_sources[0x7b]	35050	1			T18	2		T19	2		T20	6
valid_sources[0x7c]	26900	1			T20	5		T1	533		T34	5
valid_sources[0x7d]	31210	1			T20	4		T1	619		T49	3
valid_sources[0x7e]	26220	1			T20	2		T1	520		T34	2
valid_sources[0x7f]	27130	1			T18	2		T19	2		T20	7
valid_sources[0x80]	31935	1			T17	8		T25	8		T26	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1622345

1

T16

1

T17

4

T25

4

values[0x0]

all_enables

biggest_size

2448425

1

T16

2

T17

7

T18

23

values[0x1]

all_enables

biggest_size

2443280

1

T16

2

T17

18

T18

32