Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
71.43 75.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[edn_reg_block] 75.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[edn_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[edn_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 4 10 75.00


Variables for Group Instance tl_intg_err_cgs_wrap[edn_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 2 2 50.00 100 1 1 0
cp_num_data_err_bits 4 1 3 75.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 20832765 0 T16 49 T17 240 T18 322



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 2 2 50.00


User Defined Bins for cp_num_cmd_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[1] 0 1 1
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 20832525 1 T16 49 T17 240 T18 322
values[3] 140 1 T4 7 T9 7 T10 7



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_num_data_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 20832525 1 T16 49 T17 240 T18 322
values[1] 40 1 T4 2 T9 2 T10 2
values[3] 120 1 T4 6 T9 6 T10 6



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 20832365 1 T16 49 T17 240 T18 322
auto[TlIntgErrCmd] 160 1 T4 8 T9 8 T10 8
auto[TlIntgErrData] 160 1 T4 8 T9 8 T10 8
auto[TlIntgErrBoth] 80 1 T4 4 T9 4 T10 4

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