Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
92.19 92.19 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 92.19 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.19 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 5 47 90.38


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 5 47 90.38 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 3300 1 T17 1 T25 1 T21 2
non_zero_bins[1] 3200 1 T17 1 T25 1 T21 3
zero 11580 1 T16 3 T17 4 T25 4



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 750 1 T20 3 T1 12 T34 3
uni 5460 1 T16 1 T17 2 T25 2
gen 5160 1 T16 1 T17 2 T25 2
res 1000 1 T21 3 T20 3 T1 14
ins 5710 1 T16 1 T17 2 T25 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 12830 1 T16 2 T17 5 T25 5
mubi_true 5250 1 T16 1 T17 1 T25 1



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 10080 1 T16 3 T17 4 T25 4
pass 8000 1 T17 2 T25 2 T21 2



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 5 47 90.38 5
Automatically Generated Cross Bins 52 5 47 90.38 5
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] [zero] [fail] * -- -- 2


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] [non_zero_bins[1]] [pass] [mubi_true] 0 1 1
[upd] [zero] [pass] [mubi_true] 0 1 1
[res] [non_zero_bins[0]] [pass] [mubi_true] 0 1 1


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] fail mubi_false 100 1 T1 2 T44 2 T45 2
upd non_zero_bins[0] fail mubi_true 50 1 T1 1 T44 1 T45 1
upd non_zero_bins[0] pass mubi_false 200 1 T1 4 T44 4 T45 4
upd non_zero_bins[0] pass mubi_true 50 1 T1 1 T44 1 T45 1
upd non_zero_bins[1] fail mubi_false 100 1 T20 1 T1 1 T34 1
upd non_zero_bins[1] fail mubi_true 150 1 T20 2 T1 1 T34 2
upd non_zero_bins[1] pass mubi_false 50 1 T1 1 T44 1 T45 1
upd zero pass mubi_false 50 1 T1 1 T44 1 T45 1
uni zero fail mubi_false 1910 1 T17 1 T25 1 T26 1
uni zero fail mubi_true 600 1 T16 1 T20 2 T1 9
uni zero pass mubi_false 2250 1 T17 1 T25 1 T26 1
uni zero pass mubi_true 700 1 T20 3 T1 11 T34 3
gen non_zero_bins[0] fail mubi_false 250 1 T21 1 T1 4 T44 4
gen non_zero_bins[0] fail mubi_true 400 1 T20 3 T1 5 T34 3
gen non_zero_bins[0] pass mubi_false 300 1 T21 1 T20 2 T1 3
gen non_zero_bins[0] pass mubi_true 200 1 T20 1 T1 3 T34 1
gen non_zero_bins[1] fail mubi_false 500 1 T17 1 T25 1 T26 1
gen non_zero_bins[1] fail mubi_true 350 1 T20 1 T1 6 T34 1
gen non_zero_bins[1] pass mubi_false 250 1 T20 2 T1 3 T34 2
gen non_zero_bins[1] pass mubi_true 100 1 T1 2 T44 2 T45 2
gen zero fail mubi_false 1560 1 T16 1 T17 1 T25 1
gen zero fail mubi_true 250 1 T1 3 T44 3 T45 3
gen zero pass mubi_false 950 1 T1 19 T44 19 T45 19
gen zero pass mubi_true 50 1 T1 1 T44 1 T45 1
res non_zero_bins[0] fail mubi_false 50 1 T20 1 T34 1 T98 1
res non_zero_bins[0] fail mubi_true 50 1 T1 1 T44 1 T45 1
res non_zero_bins[0] pass mubi_false 100 1 T1 2 T44 2 T45 2
res non_zero_bins[1] fail mubi_false 50 1 T1 1 T44 1 T45 1
res non_zero_bins[1] fail mubi_true 200 1 T21 2 T1 2 T44 2
res non_zero_bins[1] pass mubi_false 200 1 T20 1 T1 3 T34 1
res non_zero_bins[1] pass mubi_true 150 1 T21 1 T20 1 T1 1
res zero fail mubi_false 50 1 T1 1 T44 1 T45 1
res zero fail mubi_true 50 1 T1 1 T44 1 T45 1
res zero pass mubi_false 50 1 T1 1 T44 1 T45 1
res zero pass mubi_true 50 1 T1 1 T44 1 T45 1
ins non_zero_bins[0] fail mubi_false 450 1 T20 1 T1 8 T34 1
ins non_zero_bins[0] fail mubi_true 400 1 T20 1 T1 7 T34 1
ins non_zero_bins[0] pass mubi_false 500 1 T17 1 T25 1 T26 1
ins non_zero_bins[0] pass mubi_true 200 1 T1 4 T44 4 T45 4
ins non_zero_bins[1] fail mubi_false 400 1 T20 2 T1 6 T34 2
ins non_zero_bins[1] fail mubi_true 250 1 T20 1 T1 4 T34 1
ins non_zero_bins[1] pass mubi_false 250 1 T20 2 T1 3 T34 2
ins non_zero_bins[1] pass mubi_true 200 1 T20 1 T1 3 T34 1
ins zero fail mubi_false 1210 1 T16 1 T21 1 T20 4
ins zero fail mubi_true 700 1 T17 1 T25 1 T26 1
ins zero pass mubi_false 1050 1 T20 3 T1 18 T34 3
ins zero pass mubi_true 100 1 T20 1 T1 1 T34 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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