Unified Coverage Report :: Group :: csrng_agent_pkg::device_genbits_cg

Group : csrng_agent_pkg::device_genbits_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
50.00	50.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg	50.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_genbits_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	2	4	66.67
Crosses	8	5	3	37.50

Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_glen	4	2	2	50.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_genbits_cross	8	5	3	37.50	100	1	1	0

Summary for Variable csrng_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for csrng_glen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
glens[1]	0	1	1
glens[3]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

glens[0]

2610

1

T16

1

T17

1

T25

1

glens[2]

300

1

T17

1

T25

1

T26

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

3310

1

T16

1

T17

2

T25

2

pass

1850

1

T21

1

T20

5

T1

31

---

Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	5	3	37.50	5

Automatically Generated Cross Bins for csrng_genbits_cross

Element holes

csrng_glen	csrng_sts	COUNT	AT LEAST	NUMBER	STATUS
[glens[1]]	*	--	--	2
[glens[3]]	*	--	--	2

Uncovered bins

csrng_glen	csrng_sts	COUNT	AT LEAST	NUMBER	STATUS
[glens[2]]	[pass]	0	1	1

Covered bins

csrng_glen

csrng_sts

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

glens[0]

fail

1610

1

T16

1

T17

1

T25

1

glens[0]

pass

1000

1

T21

1

T1

19

T44

19

glens[2]

fail

300

1

T17

1

T25

1

T26

1