Module Definition
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Module : edn_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
12.50 12.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.edn_csr_assert 12.50 12.50



Module Instance : tb.dut.edn_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
12.50 12.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
12.50 12.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.47 83.33 97.09 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : edn_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 1 12.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 1 12.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 211229270 11960890 0 0
boot_gen_cmd_rd_A 211229270 0 0 0
boot_ins_cmd_rd_A 211229270 0 0 0
ctrl_rd_A 211229270 0 0 0
err_code_test_rd_A 211229270 0 0 0
intr_enable_rd_A 211229270 0 0 0
max_num_reqs_between_reseeds_rd_A 211229270 0 0 0
regwen_rd_A 211229270 0 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 11960890 0 0
T1 417080 238857 0 0
T2 9795 825 0 0
T3 9795 825 0 0
T4 7465 11 0 0
T5 2455 66 0 0
T6 0 66 0 0
T7 0 825 0 0
T8 0 825 0 0
T9 0 11 0 0
T10 0 11 0 0
T11 997 0 0 0
T12 1797 0 0 0
T13 1841 0 0 0
T14 1224 0 0 0
T15 2974 0 0 0

boot_gen_cmd_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

boot_ins_cmd_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

err_code_test_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

max_num_reqs_between_reseeds_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211229270 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%