Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		71.43	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	94.29	100.00	100.00		71.43	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		71.43	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		71.43	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.64	100.00	77.91			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	10	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T16,T17,T25
DataWait	75	Covered	T16,T17,T18
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T16,T17,T25
DataWait->AckPls	80	Covered	T16,T17,T25
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T18,T19,T11
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T16,T17,T18
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T16,T17,T25
Idle	-	1	0	-	Covered	T16,T17,T18
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T16,T17,T25
DataWait	-	-	-	0	Covered	T16,T17,T18
AckPls	-	-	-	-	Covered	T16,T17,T25
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1474108370	1198330	0	0
FpvSecCmErrorStEscalate_A	1474108370	1205680	0	0
u_state_regs_A	1474089570	1472868000	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474108370	1198330	0	0
T1	2919560	0	0	0
T11	0	3710	0	0
T13	0	7756	0	0
T18	6979	3710	0	0
T19	6979	3710	0	0
T20	108122	0	0	0
T21	10458	0	0	0
T24	12887	7756	0	0
T25	12579	0	0	0
T26	12579	0	0	0
T33	0	7756	0	0
T35	0	3710	0	0
T36	0	7756	0	0
T37	0	7756	0	0
T38	0	3710	0	0
T39	12579	0	0	0
T40	12579	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474108370	1205680	0	0
T1	2919560	0	0	0
T11	0	3717	0	0
T13	0	7763	0	0
T18	6979	3717	0	0
T19	6979	3717	0	0
T20	108122	0	0	0
T21	10458	0	0	0
T24	12887	7763	0	0
T25	12579	0	0	0
T26	12579	0	0	0
T33	0	7763	0	0
T35	0	3717	0	0
T36	0	7763	0	0
T37	0	7763	0	0
T38	0	3717	0	0
T39	12579	0	0	0
T40	12579	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1474089570	1472868000	0	0
T16	9121	8687	0	0
T17	12579	12145	0	0
T18	6847	6007	0	0
T19	6847	6007	0	0
T20	108122	102368	0	0
T21	10458	10038	0	0
T25	12579	12145	0	0
T26	12579	12145	0	0
T39	12579	12145	0	0
T40	12579	12145	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T25,T21
DataWait	75	Covered	T17,T25,T21
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17,T25,T21
DataWait->AckPls	80	Covered	T17,T25,T21
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T17,T25,T21
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T17,T25,T21
Idle	-	1	0	-	Covered	T17,T25,T21
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T17,T25,T21
DataWait	-	-	-	0	Covered	T17,T25,T21
AckPls	-	-	-	-	Covered	T17,T25,T21
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210586910	210412400	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	210412400	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	997	877	0	0
T19	997	877	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T25,T26
DataWait	75	Covered	T17,T25,T26
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17,T25,T26
DataWait->AckPls	80	Covered	T17,T25,T26
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T17,T25,T26
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T17,T25,T26
Idle	-	1	0	-	Covered	T17,T25,T26
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T17,T25,T26
DataWait	-	-	-	0	Covered	T17,T25,T26
AckPls	-	-	-	-	Covered	T17,T25,T26
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210586910	210412400	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	210412400	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	997	877	0	0
T19	997	877	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T25,T26
DataWait	75	Covered	T17,T25,T26
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17,T25,T26
DataWait->AckPls	80	Covered	T17,T25,T26
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T17,T25,T26
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T17,T25,T26
Idle	-	1	0	-	Covered	T17,T25,T26
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T17,T25,T26
DataWait	-	-	-	0	Covered	T17,T25,T26
AckPls	-	-	-	-	Covered	T17,T25,T26
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210586910	210412400	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	210412400	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	997	877	0	0
T19	997	877	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T25,T26
DataWait	75	Covered	T17,T25,T26
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17,T25,T26
DataWait->AckPls	80	Covered	T17,T25,T26
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T17,T25,T26
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T17,T25,T26
Idle	-	1	0	-	Covered	T17,T25,T26
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T17,T25,T26
DataWait	-	-	-	0	Covered	T17,T25,T26
AckPls	-	-	-	-	Covered	T17,T25,T26
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210586910	210412400	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	210412400	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	997	877	0	0
T19	997	877	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T25,T26
DataWait	75	Covered	T17,T25,T26
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17,T25,T26
DataWait->AckPls	80	Covered	T17,T25,T26
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T17,T25,T26
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T17,T25,T26
Idle	-	1	0	-	Covered	T17,T25,T26
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T17,T25,T26
DataWait	-	-	-	0	Covered	T17,T25,T26
AckPls	-	-	-	-	Covered	T17,T25,T26
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210586910	210412400	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	210412400	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	997	877	0	0
T19	997	877	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T28,T29
DataWait	75	Covered	T27,T28,T29
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T27,T28,T29
DataWait->AckPls	80	Covered	T27,T28,T29
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T27,T28,T29
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T18,T19,T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T27,T28,T29
Idle	-	1	0	-	Covered	T27,T28,T29
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T27,T28,T29
DataWait	-	-	-	0	Covered	T27,T28,T29
AckPls	-	-	-	-	Covered	T27,T28,T29
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210586910	210412400	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	210412400	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	997	877	0	0
T19	997	877	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T21,T22,T23

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	10	71.43
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T16,T17,T25
DataWait	75	Covered	T16,T17,T18
Disabled	107	Covered	T16,T17,T18
EndPointClear	63	Covered	T16,T17,T18
Error	99	Covered	T18,T19,T24
Idle	68	Covered	T16,T17,T18

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T16,T17,T25
DataWait->AckPls	80	Covered	T16,T17,T25
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T18,T19,T11
Disabled->EndPointClear	63	Covered	T16,T17,T18
Disabled->Error	99	Covered	T30,T31,T32
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T30,T31,T32
EndPointClear->Idle	68	Covered	T16,T17,T18
Idle->DataWait	75	Covered	T16,T17,T18
Idle->Disabled	107	Covered	T21,T20,T1
Idle->Error	99	Covered	T24,T13,T33

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T16,T17,T18
Disabled	0	-	-	-	Covered	T16,T17,T18
EndPointClear	-	-	-	-	Covered	T16,T17,T18
Idle	-	1	1	-	Covered	T16,T17,T25
Idle	-	1	0	-	Covered	T16,T17,T18
Idle	-	0	-	-	Covered	T16,T17,T18
DataWait	-	-	-	1	Covered	T16,T17,T25
DataWait	-	-	-	0	Covered	T16,T17,T18
AckPls	-	-	-	-	Covered	T16,T17,T25
Error	-	-	-	-	Covered	T18,T19,T24
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T24
0	1	Covered	T21,T22,T23
0	0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	210586910	171190	0	0
FpvSecCmErrorStEscalate_A	210586910	172240	0	0
u_state_regs_A	210568110	210393600	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	171190	0	0
T1	417080	0	0	0
T11	0	530	0	0
T13	0	1108	0	0
T18	997	530	0	0
T19	997	530	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1108	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1108	0	0
T35	0	530	0	0
T36	0	1108	0	0
T37	0	1108	0	0
T38	0	530	0	0
T39	1797	0	0	0
T40	1797	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210586910	172240	0	0
T1	417080	0	0	0
T11	0	531	0	0
T13	0	1109	0	0
T18	997	531	0	0
T19	997	531	0	0
T20	15446	0	0	0
T21	1494	0	0	0
T24	1841	1109	0	0
T25	1797	0	0	0
T26	1797	0	0	0
T33	0	1109	0	0
T35	0	531	0	0
T36	0	1109	0	0
T37	0	1109	0	0
T38	0	531	0	0
T39	1797	0	0	0
T40	1797	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210568110	210393600	0	0
T16	1303	1241	0	0
T17	1797	1735	0	0
T18	865	745	0	0
T19	865	745	0	0
T20	15446	14624	0	0
T21	1494	1434	0	0
T25	1797	1735	0	0
T26	1797	1735	0	0
T39	1797	1735	0	0
T40	1797	1735	0	0