Module Definition
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Module : prim_intr_hw
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done 100.00 100.00 100.00 100.00 100.00
tb.dut.u_edn_core.u_intr_hw_edn_fatal_err 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.64 100.00 77.91 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.u_intr_hw_edn_fatal_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.64 100.00 77.91 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Module : prim_intr_hw
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T17,T18
10CoveredT20,T1,T34

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT20,T1,T34
11CoveredT20,T1,T34

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T17,T25
10CoveredT16,T17,T18

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT20,T24,T1
10CoveredT16,T17,T18
11CoveredT20,T24,T1

Branch Coverage for Module : prim_intr_hw
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1630 1630 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1630 1630 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0
T25 2 2 0 0
T26 2 2 0 0
T39 2 2 0 0
T40 2 2 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T17,T25
10CoveredT20,T1,T34

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT20,T1,T34
11CoveredT20,T1,T34

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T17,T25
10CoveredT16,T17,T25

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT20,T24,T1
10CoveredT16,T17,T25
11CoveredT20,T1,T34

Branch Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 815 815 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_fatal_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5411100.00
ALWAYS8033100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 1 1
49 1 1
52 1 1
54 1 1
80 1 1
81 1 1
83 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_fatal_err
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT18,T19,T24
10CoveredT20,T1,T34

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT20,T1,T34
11CoveredT20,T1,T34

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT20,T1,T34
10CoveredT18,T19,T20

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT20,T24,T1
10CoveredT18,T19,T20
11CoveredT20,T24,T1

Branch Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_fatal_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 80 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 80 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_edn_core.u_intr_hw_edn_fatal_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 815 815 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

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