Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T21,T24,T13 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T16,T17,T25 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T21,T24,T13 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T25 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T21,T22,T23 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T25 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T25 |
| 1 | 0 | Covered | T16,T17,T25 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T16,T17,T25 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T25 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T25 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T16,T17,T25 |
| 0 |
0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1684695280 |
187795020 |
0 |
6520 |
| T1 |
0 |
368694 |
0 |
0 |
| T12 |
0 |
9394 |
0 |
0 |
| T13 |
0 |
1113 |
0 |
0 |
| T16 |
1303 |
1191 |
0 |
1 |
| T17 |
10782 |
9394 |
0 |
6 |
| T18 |
5982 |
0 |
0 |
6 |
| T19 |
5982 |
0 |
0 |
6 |
| T20 |
92676 |
6014 |
0 |
6 |
| T21 |
8964 |
987 |
0 |
6 |
| T24 |
9205 |
1113 |
0 |
5 |
| T25 |
10782 |
9394 |
0 |
6 |
| T26 |
10782 |
9394 |
0 |
6 |
| T27 |
1219 |
45 |
0 |
1 |
| T28 |
0 |
45 |
0 |
0 |
| T29 |
0 |
45 |
0 |
0 |
| T30 |
34426 |
0 |
0 |
1 |
| T39 |
10782 |
9394 |
0 |
6 |
| T40 |
10782 |
9394 |
0 |
6 |
| T54 |
1797 |
0 |
0 |
1 |
| T61 |
0 |
9394 |
0 |
0 |
| T62 |
0 |
6023 |
0 |
0 |
| T63 |
0 |
6023 |
0 |
0 |
| T64 |
0 |
6023 |
0 |
0 |
| T65 |
0 |
45 |
0 |
0 |
| T66 |
0 |
45 |
0 |
0 |
| T72 |
1303 |
0 |
0 |
1 |
| T73 |
1797 |
0 |
0 |
1 |
| T74 |
1352 |
0 |
0 |
1 |
| T75 |
1797 |
0 |
0 |
1 |
| T76 |
1841 |
0 |
0 |
1 |
| T77 |
1797 |
0 |
0 |
1 |
| T78 |
1797 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1684695280 |
187795020 |
0 |
0 |
| T1 |
0 |
368694 |
0 |
0 |
| T12 |
0 |
9394 |
0 |
0 |
| T13 |
0 |
1113 |
0 |
0 |
| T16 |
1303 |
1191 |
0 |
0 |
| T17 |
10782 |
9394 |
0 |
0 |
| T18 |
5982 |
0 |
0 |
0 |
| T19 |
5982 |
0 |
0 |
0 |
| T20 |
92676 |
6014 |
0 |
0 |
| T21 |
8964 |
987 |
0 |
0 |
| T24 |
9205 |
1113 |
0 |
0 |
| T25 |
10782 |
9394 |
0 |
0 |
| T26 |
10782 |
9394 |
0 |
0 |
| T27 |
1219 |
45 |
0 |
0 |
| T28 |
0 |
45 |
0 |
0 |
| T29 |
0 |
45 |
0 |
0 |
| T30 |
34426 |
0 |
0 |
0 |
| T39 |
10782 |
9394 |
0 |
0 |
| T40 |
10782 |
9394 |
0 |
0 |
| T54 |
1797 |
0 |
0 |
0 |
| T61 |
0 |
9394 |
0 |
0 |
| T62 |
0 |
6023 |
0 |
0 |
| T63 |
0 |
6023 |
0 |
0 |
| T64 |
0 |
6023 |
0 |
0 |
| T65 |
0 |
45 |
0 |
0 |
| T66 |
0 |
45 |
0 |
0 |
| T72 |
1303 |
0 |
0 |
0 |
| T73 |
1797 |
0 |
0 |
0 |
| T74 |
1352 |
0 |
0 |
0 |
| T75 |
1797 |
0 |
0 |
0 |
| T76 |
1841 |
0 |
0 |
0 |
| T77 |
1797 |
0 |
0 |
0 |
| T78 |
1797 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T21,T24,T13 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T16,T17,T25 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T21,T24,T13 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T25 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T21,T22,T23 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T25 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
12 |
85.71 |
| TERNARY |
141 |
4 |
3 |
75.00 |
| TERNARY |
146 |
3 |
2 |
66.67 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T16,T17,T25 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
78300 |
0 |
815 |
| T1 |
417080 |
0 |
0 |
1 |
| T11 |
997 |
0 |
0 |
1 |
| T12 |
1797 |
0 |
0 |
1 |
| T13 |
0 |
40 |
0 |
0 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
0 |
0 |
1 |
| T21 |
1494 |
434 |
0 |
1 |
| T22 |
0 |
434 |
0 |
0 |
| T23 |
0 |
434 |
0 |
0 |
| T24 |
1841 |
40 |
0 |
1 |
| T26 |
1797 |
0 |
0 |
1 |
| T33 |
0 |
40 |
0 |
0 |
| T36 |
0 |
40 |
0 |
0 |
| T37 |
0 |
40 |
0 |
0 |
| T39 |
1797 |
0 |
0 |
1 |
| T40 |
1797 |
0 |
0 |
1 |
| T41 |
0 |
52 |
0 |
0 |
| T42 |
0 |
52 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
78300 |
0 |
0 |
| T1 |
417080 |
0 |
0 |
0 |
| T11 |
997 |
0 |
0 |
0 |
| T12 |
1797 |
0 |
0 |
0 |
| T13 |
0 |
40 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
0 |
0 |
0 |
| T21 |
1494 |
434 |
0 |
0 |
| T22 |
0 |
434 |
0 |
0 |
| T23 |
0 |
434 |
0 |
0 |
| T24 |
1841 |
40 |
0 |
0 |
| T26 |
1797 |
0 |
0 |
0 |
| T33 |
0 |
40 |
0 |
0 |
| T36 |
0 |
40 |
0 |
0 |
| T37 |
0 |
40 |
0 |
0 |
| T39 |
1797 |
0 |
0 |
0 |
| T40 |
1797 |
0 |
0 |
0 |
| T41 |
0 |
52 |
0 |
0 |
| T42 |
0 |
52 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T25 |
| 1 | 0 | Covered | T16,T17,T25 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T16,T17,T25 |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T25 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T25 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T16,T17,T25 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T25 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T16,T17,T25 |
| 0 |
0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T16,T17,T25 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
185226320 |
0 |
815 |
| T1 |
0 |
368694 |
0 |
0 |
| T12 |
0 |
1694 |
0 |
0 |
| T16 |
1303 |
1191 |
0 |
1 |
| T17 |
1797 |
1694 |
0 |
1 |
| T18 |
997 |
0 |
0 |
1 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
6014 |
0 |
1 |
| T21 |
1494 |
0 |
0 |
1 |
| T25 |
1797 |
1694 |
0 |
1 |
| T26 |
1797 |
1694 |
0 |
1 |
| T39 |
1797 |
1694 |
0 |
1 |
| T40 |
1797 |
1694 |
0 |
1 |
| T61 |
0 |
1694 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
185226320 |
0 |
0 |
| T1 |
0 |
368694 |
0 |
0 |
| T12 |
0 |
1694 |
0 |
0 |
| T16 |
1303 |
1191 |
0 |
0 |
| T17 |
1797 |
1694 |
0 |
0 |
| T18 |
997 |
0 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
6014 |
0 |
0 |
| T21 |
1494 |
0 |
0 |
0 |
| T25 |
1797 |
1694 |
0 |
0 |
| T26 |
1797 |
1694 |
0 |
0 |
| T39 |
1797 |
1694 |
0 |
0 |
| T40 |
1797 |
1694 |
0 |
0 |
| T61 |
0 |
1694 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T17,T25,T21 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T21 |
| 1 | 0 | Covered | T17,T25,T21 |
| 1 | 1 | Covered | T17,T25,T21 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T21 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T21 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T17,T25,T21 |
| 1 | 1 | Covered | T17,T25,T21 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T21 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T21 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T21 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T21 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T21 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T21 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T25,T21 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T17,T25,T21 |
| 0 |
0 |
1 |
Covered |
T17,T25,T21 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T21 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T21 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
608100 |
0 |
815 |
| T12 |
0 |
1677 |
0 |
0 |
| T13 |
0 |
1113 |
0 |
0 |
| T17 |
1797 |
1677 |
0 |
1 |
| T18 |
997 |
0 |
0 |
1 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
0 |
0 |
1 |
| T21 |
1494 |
987 |
0 |
1 |
| T24 |
1841 |
1113 |
0 |
1 |
| T25 |
1797 |
1677 |
0 |
1 |
| T26 |
1797 |
1677 |
0 |
1 |
| T39 |
1797 |
1677 |
0 |
1 |
| T40 |
1797 |
1677 |
0 |
1 |
| T61 |
0 |
1677 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
608100 |
0 |
0 |
| T12 |
0 |
1677 |
0 |
0 |
| T13 |
0 |
1113 |
0 |
0 |
| T17 |
1797 |
1677 |
0 |
0 |
| T18 |
997 |
0 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
0 |
0 |
0 |
| T21 |
1494 |
987 |
0 |
0 |
| T24 |
1841 |
1113 |
0 |
0 |
| T25 |
1797 |
1677 |
0 |
0 |
| T26 |
1797 |
1677 |
0 |
0 |
| T39 |
1797 |
1677 |
0 |
0 |
| T40 |
1797 |
1677 |
0 |
0 |
| T61 |
0 |
1677 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T25,T26 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T17,T25,T26 |
| 0 |
0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
495900 |
0 |
815 |
| T12 |
0 |
1653 |
0 |
0 |
| T17 |
1797 |
1653 |
0 |
1 |
| T18 |
997 |
0 |
0 |
1 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
0 |
0 |
1 |
| T21 |
1494 |
0 |
0 |
1 |
| T24 |
1841 |
0 |
0 |
1 |
| T25 |
1797 |
1653 |
0 |
1 |
| T26 |
1797 |
1653 |
0 |
1 |
| T39 |
1797 |
1653 |
0 |
1 |
| T40 |
1797 |
1653 |
0 |
1 |
| T61 |
0 |
1653 |
0 |
0 |
| T62 |
0 |
1653 |
0 |
0 |
| T63 |
0 |
1653 |
0 |
0 |
| T64 |
0 |
1653 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
495900 |
0 |
0 |
| T12 |
0 |
1653 |
0 |
0 |
| T17 |
1797 |
1653 |
0 |
0 |
| T18 |
997 |
0 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
0 |
0 |
0 |
| T21 |
1494 |
0 |
0 |
0 |
| T24 |
1841 |
0 |
0 |
0 |
| T25 |
1797 |
1653 |
0 |
0 |
| T26 |
1797 |
1653 |
0 |
0 |
| T39 |
1797 |
1653 |
0 |
0 |
| T40 |
1797 |
1653 |
0 |
0 |
| T61 |
0 |
1653 |
0 |
0 |
| T62 |
0 |
1653 |
0 |
0 |
| T63 |
0 |
1653 |
0 |
0 |
| T64 |
0 |
1653 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T25,T26 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T17,T25,T26 |
| 0 |
0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
466800 |
0 |
815 |
| T12 |
0 |
1556 |
0 |
0 |
| T17 |
1797 |
1556 |
0 |
1 |
| T18 |
997 |
0 |
0 |
1 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
0 |
0 |
1 |
| T21 |
1494 |
0 |
0 |
1 |
| T24 |
1841 |
0 |
0 |
1 |
| T25 |
1797 |
1556 |
0 |
1 |
| T26 |
1797 |
1556 |
0 |
1 |
| T39 |
1797 |
1556 |
0 |
1 |
| T40 |
1797 |
1556 |
0 |
1 |
| T61 |
0 |
1556 |
0 |
0 |
| T62 |
0 |
1556 |
0 |
0 |
| T63 |
0 |
1556 |
0 |
0 |
| T64 |
0 |
1556 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
466800 |
0 |
0 |
| T12 |
0 |
1556 |
0 |
0 |
| T17 |
1797 |
1556 |
0 |
0 |
| T18 |
997 |
0 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
0 |
0 |
0 |
| T21 |
1494 |
0 |
0 |
0 |
| T24 |
1841 |
0 |
0 |
0 |
| T25 |
1797 |
1556 |
0 |
0 |
| T26 |
1797 |
1556 |
0 |
0 |
| T39 |
1797 |
1556 |
0 |
0 |
| T40 |
1797 |
1556 |
0 |
0 |
| T61 |
0 |
1556 |
0 |
0 |
| T62 |
0 |
1556 |
0 |
0 |
| T63 |
0 |
1556 |
0 |
0 |
| T64 |
0 |
1556 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T25,T26 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T17,T25,T26 |
| 0 |
0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
501550 |
0 |
815 |
| T12 |
0 |
1428 |
0 |
0 |
| T17 |
1797 |
1428 |
0 |
1 |
| T18 |
997 |
0 |
0 |
1 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
0 |
0 |
1 |
| T21 |
1494 |
0 |
0 |
1 |
| T24 |
1841 |
0 |
0 |
1 |
| T25 |
1797 |
1428 |
0 |
1 |
| T26 |
1797 |
1428 |
0 |
1 |
| T39 |
1797 |
1428 |
0 |
1 |
| T40 |
1797 |
1428 |
0 |
1 |
| T61 |
0 |
1428 |
0 |
0 |
| T62 |
0 |
1428 |
0 |
0 |
| T63 |
0 |
1428 |
0 |
0 |
| T64 |
0 |
1428 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
501550 |
0 |
0 |
| T12 |
0 |
1428 |
0 |
0 |
| T17 |
1797 |
1428 |
0 |
0 |
| T18 |
997 |
0 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
0 |
0 |
0 |
| T21 |
1494 |
0 |
0 |
0 |
| T24 |
1841 |
0 |
0 |
0 |
| T25 |
1797 |
1428 |
0 |
0 |
| T26 |
1797 |
1428 |
0 |
0 |
| T39 |
1797 |
1428 |
0 |
0 |
| T40 |
1797 |
1428 |
0 |
0 |
| T61 |
0 |
1428 |
0 |
0 |
| T62 |
0 |
1428 |
0 |
0 |
| T63 |
0 |
1428 |
0 |
0 |
| T64 |
0 |
1428 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 39 | 92.86 |
| Logical | 42 | 39 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T17,T25,T26 |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T17,T25,T26 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T25,T26 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T25,T26 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T17,T25,T26 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T17,T25,T26 |
| 0 |
0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T17,T25,T26 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
415800 |
0 |
815 |
| T12 |
0 |
1386 |
0 |
0 |
| T17 |
1797 |
1386 |
0 |
1 |
| T18 |
997 |
0 |
0 |
1 |
| T19 |
997 |
0 |
0 |
1 |
| T20 |
15446 |
0 |
0 |
1 |
| T21 |
1494 |
0 |
0 |
1 |
| T24 |
1841 |
0 |
0 |
1 |
| T25 |
1797 |
1386 |
0 |
1 |
| T26 |
1797 |
1386 |
0 |
1 |
| T39 |
1797 |
1386 |
0 |
1 |
| T40 |
1797 |
1386 |
0 |
1 |
| T61 |
0 |
1386 |
0 |
0 |
| T62 |
0 |
1386 |
0 |
0 |
| T63 |
0 |
1386 |
0 |
0 |
| T64 |
0 |
1386 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
415800 |
0 |
0 |
| T12 |
0 |
1386 |
0 |
0 |
| T17 |
1797 |
1386 |
0 |
0 |
| T18 |
997 |
0 |
0 |
0 |
| T19 |
997 |
0 |
0 |
0 |
| T20 |
15446 |
0 |
0 |
0 |
| T21 |
1494 |
0 |
0 |
0 |
| T24 |
1841 |
0 |
0 |
0 |
| T25 |
1797 |
1386 |
0 |
0 |
| T26 |
1797 |
1386 |
0 |
0 |
| T39 |
1797 |
1386 |
0 |
0 |
| T40 |
1797 |
1386 |
0 |
0 |
| T61 |
0 |
1386 |
0 |
0 |
| T62 |
0 |
1386 |
0 |
0 |
| T63 |
0 |
1386 |
0 |
0 |
| T64 |
0 |
1386 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T27,T28,T29 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T27,T28,T29 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T16,T17,T18 |
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T27,T28,T29 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T27,T28,T29 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T27,T28,T29 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T27,T28,T29 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T28,T29 |
| 1 | 0 | Covered | T16,T17,T18 |
| 1 | 1 | Covered | T16,T17,T18 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T17,T18 |
| 1 | 0 | Covered | T27,T28,T29 |
| 1 | 1 | Covered | T27,T28,T29 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T27,T28,T29 |
| 1 | Covered | T16,T17,T18 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T16,T17,T18 |
| 1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
- |
Covered |
T27,T28,T29 |
| 0 |
0 |
1 |
Covered |
T27,T28,T29 |
| 0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T27,T28,T29 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T16,T17,T18 |
| 0 |
1 |
Covered |
T27,T28,T29 |
| 0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T16,T17,T18 |
| 0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
2250 |
0 |
815 |
| T27 |
1219 |
45 |
0 |
1 |
| T28 |
0 |
45 |
0 |
0 |
| T29 |
0 |
45 |
0 |
0 |
| T30 |
34426 |
0 |
0 |
1 |
| T54 |
1797 |
0 |
0 |
1 |
| T65 |
0 |
45 |
0 |
0 |
| T66 |
0 |
45 |
0 |
0 |
| T67 |
0 |
45 |
0 |
0 |
| T68 |
0 |
45 |
0 |
0 |
| T69 |
0 |
45 |
0 |
0 |
| T70 |
0 |
45 |
0 |
0 |
| T71 |
0 |
45 |
0 |
0 |
| T72 |
1303 |
0 |
0 |
1 |
| T73 |
1797 |
0 |
0 |
1 |
| T74 |
1352 |
0 |
0 |
1 |
| T75 |
1797 |
0 |
0 |
1 |
| T76 |
1841 |
0 |
0 |
1 |
| T77 |
1797 |
0 |
0 |
1 |
| T78 |
1797 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
210586910 |
2250 |
0 |
0 |
| T27 |
1219 |
45 |
0 |
0 |
| T28 |
0 |
45 |
0 |
0 |
| T29 |
0 |
45 |
0 |
0 |
| T30 |
34426 |
0 |
0 |
0 |
| T54 |
1797 |
0 |
0 |
0 |
| T65 |
0 |
45 |
0 |
0 |
| T66 |
0 |
45 |
0 |
0 |
| T67 |
0 |
45 |
0 |
0 |
| T68 |
0 |
45 |
0 |
0 |
| T69 |
0 |
45 |
0 |
0 |
| T70 |
0 |
45 |
0 |
0 |
| T71 |
0 |
45 |
0 |
0 |
| T72 |
1303 |
0 |
0 |
0 |
| T73 |
1797 |
0 |
0 |
0 |
| T74 |
1352 |
0 |
0 |
0 |
| T75 |
1797 |
0 |
0 |
0 |
| T76 |
1841 |
0 |
0 |
0 |
| T77 |
1797 |
0 |
0 |
0 |
| T78 |
1797 |
0 |
0 |
0 |