Module Definition
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Module : prim_count
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.31 69.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr 69.31 69.31



Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.31 69.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.31 69.31


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.64 100.00 77.91 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_count
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 202 140 69.31
Total Bits 0->1 101 70 69.31
Total Bits 1->0 101 70 69.31

Ports 8 7 87.50
Port Bits 202 140 69.31
Port Bits 0->1 101 70 69.31
Port Bits 1->0 101 70 69.31

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
rst_ni Yes Yes T18,T19,T20 Yes T16,T17,T18 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T16,T17,T18 Yes T16,T17,T18 INPUT
set_cnt_i[0] Yes Yes *T18,*T19,*T11 Yes T18,T21,T19 INPUT
set_cnt_i[31:1] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T21,T22,T23 Yes T21,T22,T23 INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T18,T21,T19 Yes T18,T21,T19 OUTPUT
cnt_next_o[31:0] Yes Yes T18,T21,T19 Yes T18,T21,T19 OUTPUT
err_o Yes Yes T18,T19,T24 Yes T18,T19,T24 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%