Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	141	1			T17	1		T18	1		T20	1
auto_req_mode	135	1			T8	1		T9	1		T100	1
sw_mode	2407	1			T1	1		T3	1		T4	7

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

295

1

T1

1

T3

1

T18

1

single

101

1

T17

1

T35

1

T28

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1110	1			T3	1		T17	1		T4	7
auto[2]	135	1			T68	1		T248	1		T249	1
auto[3]	57	1			T71	1		T250	1		T251	4
auto[4]	266	1			T29	1		T93	59		T252	1
auto[5]	108	1			T253	1		T254	1		T255	12
auto[6]	79	1			T256	1		T257	23		T258	1
auto[7]	928	1			T1	1		T18	1		T19	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[6]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	72	1			T17	1		T35	1		T72	1
auto[1]	auto_req_mode	82	1			T100	1		T110	1		T76	1
auto[1]	sw_mode	956	1			T3	1		T4	7		T61	1
auto[2]	boot_req_mode	7	1			T248	1		T259	1		T260	1
auto[2]	auto_req_mode	2	1			T261	1		T262	1		-	-
auto[2]	sw_mode	126	1			T68	1		T249	1		T263	1
auto[3]	boot_req_mode	6	1			T264	1		T265	1		T266	1
auto[3]	auto_req_mode	3	1			T267	1		T268	1		T269	1
auto[3]	sw_mode	48	1			T71	1		T250	1		T251	4
auto[4]	boot_req_mode	6	1			T252	1		T270	1		T271	1
auto[4]	auto_req_mode	1	1			T272	1		-	-		-	-
auto[4]	sw_mode	259	1			T29	1		T93	59		T57	55
auto[5]	boot_req_mode	2	1			T273	1		T274	1		-	-
auto[5]	auto_req_mode	6	1			T253	1		T275	1		T276	1
auto[5]	sw_mode	100	1			T254	1		T255	12		T277	18
auto[6]	auto_req_mode	5	1			T278	1		T279	1		T280	1
auto[6]	sw_mode	74	1			T256	1		T257	23		T258	1
auto[7]	boot_req_mode	48	1			T18	1		T20	1		T31	1
auto[7]	auto_req_mode	36	1			T8	1		T9	1		T109	1
auto[7]	sw_mode	844	1			T1	1		T19	1		T5	38