Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	591091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4980557

1

T1

7

T2

68

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1465733	1			T1	54		T2	12		T3	88
values[0x0]	1902741	1			T1	9		T2	41		T3	6
values[0x1]	2203174	1			T1	3		T2	31		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	290611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5281037

1

T1

27

T2

73

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23555	1			T3	99		T4	1		T26	1
valid_sources[0x01]	23025	1			T20	1		T26	1		T180	2
valid_sources[0x02]	22703	1			T180	2		T188	17		T185	3
valid_sources[0x03]	22524	1			T4	1		T19	7		T26	2
valid_sources[0x04]	21836	1			T18	1		T26	2		T180	1
valid_sources[0x05]	19987	1			T2	1		T4	1		T14	1
valid_sources[0x06]	21732	1			T179	1		T188	25		T185	1
valid_sources[0x07]	22161	1			T2	1		T14	2		T20	1
valid_sources[0x08]	20835	1			T2	1		T26	2		T211	2
valid_sources[0x09]	21842	1			T20	3		T21	2		T26	2
valid_sources[0x0a]	23016	1			T26	4		T27	5		T211	4
valid_sources[0x0b]	21887	1			T26	3		T39	1		T180	1
valid_sources[0x0c]	19878	1			T14	2		T20	1		T26	2
valid_sources[0x0d]	21544	1			T19	7		T26	2		T232	1
valid_sources[0x0e]	22221	1			T26	1		T212	2		T180	1
valid_sources[0x0f]	20834	1			T19	3		T26	2		T180	2
valid_sources[0x10]	22206	1			T2	1		T18	9		T20	3
valid_sources[0x11]	22833	1			T21	12		T27	2		T232	1
valid_sources[0x12]	23106	1			T2	1		T4	1		T26	3
valid_sources[0x13]	21549	1			T14	2		T20	10		T39	1
valid_sources[0x14]	21377	1			T2	1		T18	4		T19	1
valid_sources[0x15]	21319	1			T19	5		T26	5		T182	1
valid_sources[0x16]	21811	1			T182	4		T178	1		T211	1
valid_sources[0x17]	21149	1			T26	4		T27	4		T188	5
valid_sources[0x18]	20564	1			T19	2		T26	2		T232	1
valid_sources[0x19]	22464	1			T18	1		T19	2		T27	1
valid_sources[0x1a]	19935	1			T19	1		T212	1		T180	4
valid_sources[0x1b]	22691	1			T4	1		T26	1		T211	1
valid_sources[0x1c]	21495	1			T19	2		T26	1		T27	4
valid_sources[0x1d]	20569	1			T18	7		T26	1		T39	1
valid_sources[0x1e]	23006	1			T19	5		T26	2		T180	3
valid_sources[0x1f]	21916	1			T26	4		T182	4		T232	1
valid_sources[0x20]	21365	1			T14	2		T19	6		T26	1
valid_sources[0x21]	20235	1			T180	2		T188	7		T181	1
valid_sources[0x22]	20226	1			T20	4		T26	1		T180	4
valid_sources[0x23]	22214	1			T19	5		T20	1		T26	3
valid_sources[0x24]	21683	1			T4	1		T14	1		T19	1
valid_sources[0x25]	22480	1			T19	2		T26	4		T39	5
valid_sources[0x26]	22521	1			T26	3		T211	1		T39	1
valid_sources[0x27]	20916	1			T26	1		T232	1		T180	2
valid_sources[0x28]	22527	1			T2	1		T14	2		T26	3
valid_sources[0x29]	20772	1			T14	3		T19	1		T26	2
valid_sources[0x2a]	21665	1			T27	5		T212	4		T180	2
valid_sources[0x2b]	21696	1			T21	1		T26	1		T180	7
valid_sources[0x2c]	21934	1			T26	1		T27	1		T180	3
valid_sources[0x2d]	21601	1			T2	5		T14	2		T19	4
valid_sources[0x2e]	21448	1			T4	1		T18	2		T14	2
valid_sources[0x2f]	21416	1			T19	1		T26	3		T211	1
valid_sources[0x30]	22471	1			T4	1		T18	1		T14	3
valid_sources[0x31]	22383	1			T26	2		T38	14		T39	1
valid_sources[0x32]	21651	1			T18	4		T19	1		T40	1
valid_sources[0x33]	21908	1			T26	3		T182	2		T178	2
valid_sources[0x34]	22184	1			T26	2		T27	1		T212	1
valid_sources[0x35]	21202	1			T4	1		T20	1		T180	5
valid_sources[0x36]	22442	1			T14	2		T26	2		T27	11
valid_sources[0x37]	19914	1			T2	2		T14	1		T26	2
valid_sources[0x38]	21333	1			T26	3		T40	1		T188	13
valid_sources[0x39]	19863	1			T14	3		T19	22		T26	3
valid_sources[0x3a]	19833	1			T18	6		T19	6		T26	1
valid_sources[0x3b]	21673	1			T21	1		T26	2		T180	1
valid_sources[0x3c]	22594	1			T18	1		T14	1		T26	1
valid_sources[0x3d]	21047	1			T14	1		T21	3		T182	2
valid_sources[0x3e]	23303	1			T26	3		T39	1		T180	1
valid_sources[0x3f]	22571	1			T18	4		T19	7		T26	3
valid_sources[0x40]	23462	1			T18	1		T19	1		T26	2
valid_sources[0x41]	20784	1			T2	1		T18	11		T14	1
valid_sources[0x42]	21771	1			T14	1		T19	2		T26	1
valid_sources[0x43]	22184	1			T26	1		T179	4		T180	1
valid_sources[0x44]	21546	1			T4	347		T26	3		T212	2
valid_sources[0x45]	21121	1			T14	2		T26	4		T180	1
valid_sources[0x46]	21211	1			T26	1		T180	5		T188	2
valid_sources[0x47]	20467	1			T4	1		T26	2		T39	1
valid_sources[0x48]	22298	1			T2	3		T4	1		T19	5
valid_sources[0x49]	21055	1			T4	1		T18	1		T20	5
valid_sources[0x4a]	22282	1			T18	3		T26	4		T27	8
valid_sources[0x4b]	22929	1			T19	3		T26	2		T212	1
valid_sources[0x4c]	20987	1			T18	5		T19	11		T26	2
valid_sources[0x4d]	22499	1			T26	3		T179	2		T180	4
valid_sources[0x4e]	21753	1			T17	1		T26	2		T39	1
valid_sources[0x4f]	23841	1			T2	2		T3	1		T14	1
valid_sources[0x50]	22882	1			T14	1		T19	2		T26	6
valid_sources[0x51]	21473	1			T14	1		T19	4		T26	2
valid_sources[0x52]	20984	1			T14	1		T26	3		T211	1
valid_sources[0x53]	21633	1			T20	3		T212	1		T180	4
valid_sources[0x54]	22794	1			T26	2		T178	1		T212	1
valid_sources[0x55]	21429	1			T18	2		T26	1		T182	1
valid_sources[0x56]	21065	1			T21	2		T26	1		T211	1
valid_sources[0x57]	23433	1			T2	2		T14	3		T26	3
valid_sources[0x58]	20255	1			T18	4		T212	1		T180	4
valid_sources[0x59]	20517	1			T19	7		T26	4		T182	1
valid_sources[0x5a]	22711	1			T26	1		T180	2		T188	3
valid_sources[0x5b]	20550	1			T2	1		T18	6		T26	3
valid_sources[0x5c]	21401	1			T18	1		T26	1		T180	1
valid_sources[0x5d]	19273	1			T14	1		T26	1		T188	20
valid_sources[0x5e]	20620	1			T21	4		T26	2		T180	2
valid_sources[0x5f]	22963	1			T212	2		T180	4		T188	7
valid_sources[0x60]	23408	1			T19	1		T26	3		T180	3
valid_sources[0x61]	21202	1			T2	1		T26	6		T180	2
valid_sources[0x62]	23390	1			T26	2		T182	2		T40	1
valid_sources[0x63]	22326	1			T14	1		T19	5		T26	1
valid_sources[0x64]	22713	1			T18	7		T26	2		T180	2
valid_sources[0x65]	22906	1			T26	2		T27	40		T180	5
valid_sources[0x66]	21247	1			T179	9		T180	6		T188	9
valid_sources[0x67]	22283	1			T180	2		T188	11		T184	1
valid_sources[0x68]	22935	1			T26	1		T188	4		T184	1
valid_sources[0x69]	22575	1			T26	1		T27	1		T232	1
valid_sources[0x6a]	21671	1			T26	2		T182	2		T179	1
valid_sources[0x6b]	22702	1			T26	2		T27	1		T182	3
valid_sources[0x6c]	23000	1			T18	3		T19	15		T26	3
valid_sources[0x6d]	22330	1			T19	6		T26	1		T38	3
valid_sources[0x6e]	23003	1			T18	1		T19	7		T26	2
valid_sources[0x6f]	21463	1			T19	5		T180	3		T188	10
valid_sources[0x70]	21926	1			T2	3		T26	1		T179	6
valid_sources[0x71]	21770	1			T3	1		T26	2		T38	6
valid_sources[0x72]	21559	1			T19	12		T212	1		T180	1
valid_sources[0x73]	22527	1			T26	1		T212	3		T180	3
valid_sources[0x74]	22353	1			T17	1		T19	2		T26	3
valid_sources[0x75]	22590	1			T18	1		T26	3		T39	2
valid_sources[0x76]	20172	1			T2	3		T18	11		T26	3
valid_sources[0x77]	20635	1			T4	1		T14	1		T26	3
valid_sources[0x78]	21395	1			T4	1		T14	2		T26	1
valid_sources[0x79]	21678	1			T18	5		T26	3		T180	1
valid_sources[0x7a]	23086	1			T1	1		T2	1		T14	2
valid_sources[0x7b]	20672	1			T14	1		T19	18		T26	3
valid_sources[0x7c]	21732	1			T19	15		T20	1		T26	1
valid_sources[0x7d]	22457	1			T4	1		T19	1		T20	9
valid_sources[0x7e]	20840	1			T1	1		T2	2		T26	1
valid_sources[0x7f]	22063	1			T18	3		T212	2		T179	1
valid_sources[0x80]	20757	1			T26	3		T212	1		T188	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1250391

1

T1

1

T2

2

T3

2

values[0x0]

all_enables

biggest_size

1864667

1

T1

6

T2

39

T3

6

values[0x1]

all_enables

biggest_size

1865499

1

T2

27

T3

6

T17

1