Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2139	1		T3	1	T4	7	T5	21
non_zero_bins[1]	1552	1		T4	7	T19	1	T5	10
zero	6968	1		T1	5	T2	1	T3	3

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	418	1		T3	1	T4	3	T5	5
uni	2888	1		T1	2	T3	1	T4	8
gen	3289	1		T1	1	T3	1	T17	2
res	706	1		T4	1	T5	5	T28	1
ins	3358	1		T1	2	T2	1	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

7287

mubi_true

3372

T17

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5330

T17

pass

5329

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	53	1		T93	2	T96	1	T257	1
upd	non_zero_bins[0]	fail	mubi_true	48	1		T4	1	T93	1	T95	1
upd	non_zero_bins[0]	pass	mubi_false	49	1		T5	1	T93	2	T95	3
upd	non_zero_bins[0]	pass	mubi_true	49	1		T4	1	T5	1	T93	1
upd	non_zero_bins[1]	fail	mubi_false	36	1		T36	1	T93	1	T95	1
upd	non_zero_bins[1]	fail	mubi_true	34	1		T4	1	T95	3	T94	1
upd	non_zero_bins[1]	pass	mubi_false	22	1		T93	3	T96	2	T251	1
upd	non_zero_bins[1]	pass	mubi_true	28	1		T94	1	T286	1	T216	1
upd	zero	fail	mubi_false	16	1		T95	2	T257	1	T60	1
upd	zero	fail	mubi_true	23	1		T5	1	T93	1	T34	1
upd	zero	pass	mubi_false	32	1		T5	1	T30	1	T93	2
upd	zero	pass	mubi_true	28	1		T3	1	T5	1	T93	1
uni	zero	fail	mubi_false	1067	1		T1	1	T3	1	T4	1
uni	zero	fail	mubi_true	378	1		T4	1	T5	5	T97	1
uni	zero	pass	mubi_false	1054	1		T1	1	T4	6	T5	17
uni	zero	pass	mubi_true	389	1		T5	6	T62	1	T93	11
gen	non_zero_bins[0]	fail	mubi_false	223	1		T3	1	T5	3	T93	8
gen	non_zero_bins[0]	fail	mubi_true	160	1		T4	1	T93	4	T95	3
gen	non_zero_bins[0]	pass	mubi_false	234	1		T5	2	T61	1	T28	1
gen	non_zero_bins[0]	pass	mubi_true	159	1		T4	1	T30	1	T68	1
gen	non_zero_bins[1]	fail	mubi_false	149	1		T93	6	T95	5	T94	1
gen	non_zero_bins[1]	fail	mubi_true	141	1		T4	2	T5	2	T93	4
gen	non_zero_bins[1]	pass	mubi_false	175	1		T5	4	T93	1	T95	2
gen	non_zero_bins[1]	pass	mubi_true	127	1		T29	1	T93	5	T95	5
gen	zero	fail	mubi_false	760	1		T20	1	T5	13	T62	1
gen	zero	fail	mubi_true	190	1		T1	1	T17	1	T4	1
gen	zero	pass	mubi_false	772	1		T4	2	T5	13	T63	1
gen	zero	pass	mubi_true	199	1		T17	1	T14	1	T5	1
res	non_zero_bins[0]	fail	mubi_false	77	1		T5	2	T93	1	T95	3
res	non_zero_bins[0]	fail	mubi_true	91	1		T5	1	T63	1	T93	2
res	non_zero_bins[0]	pass	mubi_false	67	1		T95	1	T94	1	T287	1
res	non_zero_bins[0]	pass	mubi_true	85	1		T5	1	T93	1	T94	1
res	non_zero_bins[1]	fail	mubi_false	53	1		T93	3	T95	1	T288	1
res	non_zero_bins[1]	fail	mubi_true	63	1		T93	1	T8	1	T9	1
res	non_zero_bins[1]	pass	mubi_false	56	1		T93	1	T95	2	T96	1
res	non_zero_bins[1]	pass	mubi_true	66	1		T4	1	T28	1	T93	2
res	zero	fail	mubi_false	32	1		T257	1	T128	1	T289	2
res	zero	fail	mubi_true	36	1		T5	1	T93	1	T95	1
res	zero	pass	mubi_false	43	1		T29	1	T7	1	T290	2
res	zero	pass	mubi_true	37	1		T93	1	T109	2	T291	1
ins	non_zero_bins[0]	fail	mubi_false	227	1		T4	2	T5	3	T93	6
ins	non_zero_bins[0]	fail	mubi_true	190	1		T5	3	T93	8	T9	1
ins	non_zero_bins[0]	pass	mubi_false	217	1		T5	1	T93	4	T95	4
ins	non_zero_bins[0]	pass	mubi_true	210	1		T4	1	T5	3	T28	1
ins	non_zero_bins[1]	fail	mubi_false	166	1		T4	1	T5	1	T63	1
ins	non_zero_bins[1]	fail	mubi_true	143	1		T4	1	T19	1	T93	3
ins	non_zero_bins[1]	pass	mubi_false	143	1		T5	2	T93	5	T8	1
ins	non_zero_bins[1]	pass	mubi_true	150	1		T4	1	T5	1	T61	1
ins	zero	fail	mubi_false	805	1		T1	1	T20	1	T5	13
ins	zero	fail	mubi_true	169	1		T1	1	T5	1	T15	1
ins	zero	pass	mubi_false	759	1		T2	1	T3	1	T4	2
ins	zero	pass	mubi_true	179	1		T17	2	T14	1	T5	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded