Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00		94.44	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.89	100.00	100.00		94.44	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00		94.44	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00		94.44	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T17,T18,T20
1	1	0	1	Covered	T17,T18,T20
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T2,T17,T18

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T35,T72
1	1	Covered	T17,T18,T20

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T110,T76,T128
1	1	Covered	T2,T6,T8

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	51	94.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T6,T8,T9
AutoCaptGenCnt	162	Covered	T2,T6,T8
AutoCaptReseedCnt	160	Covered	T8,T9,T100
AutoDispatch	142	Covered	T2,T6,T8
AutoFirstAckWait	135	Covered	T2,T6,T8
AutoLoadIns	90	Covered	T2,T6,T8
AutoSendGenCmd	170	Covered	T6,T8,T9
AutoSendReseedCmd	184	Covered	T8,T9,T100
BootCaptGenCnt	106	Covered	T17,T18,T20
BootDone	126	Covered	T17,T18,T20
BootGenAckWait	116	Covered	T17,T18,T20
BootInsAckWait	102	Covered	T17,T18,T20
BootLoadGen	98	Covered	T17,T18,T20
BootLoadIns	88	Covered	T17,T18,T20
BootPulse	121	Covered	T17,T18,T20
BootSendGenCmd	111	Covered	T17,T18,T20
Error	206	Covered	T2,T25,T6
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T8,T9,T100
AutoAckWait->Error	206	Covered	T7,T129,T130
AutoAckWait->Idle	229	Covered	T110,T76,T128
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T6,T8,T9
AutoCaptGenCnt->Error	206	Covered	T2,T43,T131
AutoCaptGenCnt->Idle	229	Covered	T132,T133,T134
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T8,T9,T100
AutoCaptReseedCnt->Error	206	Not Covered
AutoCaptReseedCnt->Idle	229	Covered	T135,T136,T137
AutoDispatch->AutoCaptGenCnt	162	Covered	T2,T6,T8
AutoDispatch->AutoCaptReseedCnt	160	Covered	T8,T9,T100
AutoDispatch->Error	206	Covered	T138
AutoDispatch->Idle	157	Covered	T8,T9,T100
AutoFirstAckWait->AutoDispatch	142	Covered	T2,T6,T8
AutoFirstAckWait->Error	206	Covered	T139,T140,T141
AutoFirstAckWait->Idle	229	Covered	T142,T143,T144
AutoLoadIns->AutoFirstAckWait	135	Covered	T2,T6,T8
AutoLoadIns->Error	206	Covered	T145,T146,T147
AutoLoadIns->Idle	229	Covered	T148,T149,T150
AutoSendGenCmd->AutoAckWait	177	Covered	T6,T8,T9
AutoSendGenCmd->Error	206	Covered	T151,T87,T152
AutoSendGenCmd->Idle	229	Covered	T153,T154,T155
AutoSendReseedCmd->AutoAckWait	191	Covered	T8,T9,T100
AutoSendReseedCmd->Error	206	Not Covered
AutoSendReseedCmd->Idle	229	Covered	T110,T156,T157
BootCaptGenCnt->BootSendGenCmd	111	Covered	T17,T18,T20
BootCaptGenCnt->Error	206	Covered	T46,T158,T159
BootCaptGenCnt->Idle	229	Covered	T160,T161,T162
BootDone->Error	206	Covered	T47,T163,T164
BootDone->Idle	229	Covered	T17,T120,T126
BootGenAckWait->BootPulse	121	Covered	T17,T18,T20
BootGenAckWait->Error	206	Covered	T44
BootGenAckWait->Idle	229	Covered	T113,T121,T122
BootInsAckWait->BootCaptGenCnt	106	Covered	T17,T18,T20
BootInsAckWait->Error	206	Covered	T165,T48,T166
BootInsAckWait->Idle	229	Covered	T103,T167,T168
BootLoadGen->BootInsAckWait	102	Covered	T17,T18,T20
BootLoadGen->Error	206	Covered	T169
BootLoadGen->Idle	229	Covered	T170,T171
BootLoadIns->BootLoadGen	98	Covered	T17,T18,T20
BootLoadIns->Error	206	Covered	T172
BootLoadIns->Idle	229	Covered	T72,T69,T173
BootPulse->BootDone	126	Covered	T17,T18,T20
BootPulse->Error	206	Covered	T174,T175,T176
BootPulse->Idle	229	Covered	T35,T117,T123
BootSendGenCmd->BootGenAckWait	116	Covered	T17,T18,T20
BootSendGenCmd->Error	206	Not Covered
BootSendGenCmd->Idle	229	Covered	T101,T102,T177
Idle->AutoLoadIns	90	Covered	T2,T6,T8
Idle->BootLoadIns	88	Covered	T17,T18,T20
Idle->Error	206	Covered	T22,T23,T24
Idle->SWPortMode	93	Covered	T1,T3,T4
SWPortMode->Error	206	Covered	T12,T66,T67
SWPortMode->Idle	229	Covered	T4,T5,T93

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T101,T102,T103
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T6,T8
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T6,T8
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T6,T8
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T6,T8
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T100
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T6,T8,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T9,T100
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T100
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T6,T8
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T8,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T8,T100
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T100
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T100
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T100
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T6,T65

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	188159295	113606	0	0
FpvSecCmErrorStEscalate_A	188159295	114357	0	0
u_state_regs_A	188125233	187979997	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	113606	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	353	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	193	0	0
T65	0	300	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	574	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	114357	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	354	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	194	0	0
T65	0	301	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	575	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188125233	187979997	0	0
T1	1409	1327	0	0
T2	2270	2152	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0