Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T4,T18
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T117,T115,T116
AckPls->Error	99	Covered	T214,T215,T86
AckPls->Idle	85	Covered	T3,T4,T18
DataWait->AckPls	80	Covered	T3,T4,T18
DataWait->Disabled	107	Covered	T153,T216,T154
DataWait->Error	99	Covered	T2,T111,T217
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T4,T18
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T4,T18
DataWait	-	-	-	0	Covered	T2,T3,T4
AckPls	-	-	-	-	Covered	T3,T4,T18
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T66,T67,T78

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1317115065	809542	0	0
FpvSecCmErrorStEscalate_A	1317115065	814799	0	0
u_state_regs_A	1317081003	1316064351	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317115065	809542	0	0
T2	17598	7910	0	0
T3	6944	0	0	0
T4	52416	0	0	0
T6	0	2821	0	0
T7	0	4284	0	0
T12	0	4046	0	0
T13	0	7756	0	0
T14	12775	0	0	0
T17	7742	0	0	0
T18	9744	0	0	0
T19	11116	0	0	0
T20	10864	0	0	0
T25	3521	1701	0	0
T65	0	2450	0	0
T66	0	4598	0	0
T67	0	2876	0	0
T68	13601	0	0	0
T111	0	4368	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317115065	814799	0	0
T2	17598	7917	0	0
T3	6944	0	0	0
T4	52416	0	0	0
T6	0	2828	0	0
T7	0	4291	0	0
T12	0	4053	0	0
T13	0	7763	0	0
T14	12775	0	0	0
T17	7742	0	0	0
T18	9744	0	0	0
T19	11116	0	0	0
T20	10864	0	0	0
T25	3521	1708	0	0
T65	0	2457	0	0
T66	0	4605	0	0
T67	0	2883	0	0
T68	13601	0	0	0
T111	0	4375	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317081003	1316064351	0	0
T1	9863	9289	0	0
T2	17354	16528	0	0
T3	6944	6405	0	0
T4	52416	50246	0	0
T5	2632651	2632560	0	0
T14	12775	12075	0	0
T17	7742	7070	0	0
T18	9744	9093	0	0
T19	11116	10752	0	0
T20	10864	10423	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T19,T20
DataWait	75	Covered	T18,T19,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T19,T20
DataWait->AckPls	80	Covered	T18,T19,T20
DataWait->Disabled	107	Covered	T155,T177,T219
DataWait->Error	99	Covered	T176
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T18,T19,T20
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T18,T19,T20
Idle	-	1	0	-	Covered	T18,T19,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T18,T19,T20
DataWait	-	-	-	0	Covered	T18,T19,T20
AckPls	-	-	-	-	Covered	T18,T19,T20
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	115856	0	0
FpvSecCmErrorStEscalate_A	188159295	116607	0	0
u_state_regs_A	188159295	188014059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115856	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	116607	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T19,T20
DataWait	75	Covered	T17,T19,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17,T19,T20
DataWait->AckPls	80	Covered	T17,T19,T20
DataWait->Disabled	107	Covered	T133,T108,T122
DataWait->Error	99	Covered	T220,T159,T221
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T17,T19,T20
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T17,T19,T20
Idle	-	1	0	-	Covered	T17,T19,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T17,T19,T20
DataWait	-	-	-	0	Covered	T17,T19,T20
AckPls	-	-	-	-	Covered	T17,T19,T20
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	115856	0	0
FpvSecCmErrorStEscalate_A	188159295	116607	0	0
u_state_regs_A	188159295	188014059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115856	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	116607	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T20,T28
DataWait	75	Covered	T19,T20,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T20,T28
DataWait->AckPls	80	Covered	T19,T20,T28
DataWait->Disabled	107	Covered	T132,T222,T223
DataWait->Error	99	Covered	T46,T158,T174
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T19,T20,T28
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T19,T20,T28
Idle	-	1	0	-	Covered	T19,T20,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T19,T20,T28
DataWait	-	-	-	0	Covered	T19,T20,T28
AckPls	-	-	-	-	Covered	T19,T20,T28
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	115856	0	0
FpvSecCmErrorStEscalate_A	188159295	116607	0	0
u_state_regs_A	188159295	188014059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115856	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	116607	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T18,T19
DataWait	75	Covered	T1,T18,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T18,T19
DataWait->AckPls	80	Covered	T1,T18,T19
DataWait->Disabled	107	Covered	T162,T224
DataWait->Error	99	Covered	T47,T48
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T18,T19
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T18,T19
Idle	-	1	0	-	Covered	T1,T18,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T18,T19
DataWait	-	-	-	0	Covered	T1,T18,T19
AckPls	-	-	-	-	Covered	T1,T18,T19
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	115856	0	0
FpvSecCmErrorStEscalate_A	188159295	116607	0	0
u_state_regs_A	188159295	188014059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115856	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	116607	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T28,T29
DataWait	75	Covered	T19,T28,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T117
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T28,T29
DataWait->AckPls	80	Covered	T19,T28,T29
DataWait->Disabled	107	Covered	T225,T226
DataWait->Error	99	Covered	T44,T227,T130
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T19,T28,T29
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T19,T28,T29
Idle	-	1	0	-	Covered	T19,T28,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T19,T28,T29
DataWait	-	-	-	0	Covered	T19,T28,T29
AckPls	-	-	-	-	Covered	T19,T28,T29
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	115856	0	0
FpvSecCmErrorStEscalate_A	188159295	116607	0	0
u_state_regs_A	188159295	188014059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115856	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	116607	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T20,T28
DataWait	75	Covered	T19,T20,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T86
AckPls->Idle	85	Covered	T19,T20,T28
DataWait->AckPls	80	Covered	T19,T20,T28
DataWait->Disabled	107	Covered	T154,T102,T228
DataWait->Error	99	Covered	T217,T164,T229
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T19,T20,T28
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T2,T6,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T19,T20,T28
Idle	-	1	0	-	Covered	T19,T20,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T19,T20,T28
DataWait	-	-	-	0	Covered	T19,T20,T28
AckPls	-	-	-	-	Covered	T19,T20,T28
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	115856	0	0
FpvSecCmErrorStEscalate_A	188159295	116607	0	0
u_state_regs_A	188159295	188014059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115856	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	664	0	0
T67	0	418	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	116607	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	665	0	0
T67	0	419	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T35,T72

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T4,T14
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T25,T6
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T115,T116
AckPls->Error	99	Covered	T214,T215,T230
AckPls->Idle	85	Covered	T3,T4,T14
DataWait->AckPls	80	Covered	T3,T4,T14
DataWait->Disabled	107	Covered	T153,T216,T134
DataWait->Error	99	Covered	T2,T111,T43
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T72,T69,T218
EndPointClear->Error	99	Covered	T25,T65,T231
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T6,T12,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T4,T14
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T4,T14
DataWait	-	-	-	0	Covered	T2,T3,T4
AckPls	-	-	-	-	Covered	T3,T4,T14
Error	-	-	-	-	Covered	T2,T25,T6
default	-	-	-	-	Covered	T66,T67,T78

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T25,T6
0	1	Covered	T17,T35,T72
0	0	Covered	T1,T2,T3

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Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	188159295	114406	0	0
FpvSecCmErrorStEscalate_A	188159295	115157	0	0
u_state_regs_A	188125233	187979997	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	114406	0	0
T2	2514	1130	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	403	0	0
T7	0	612	0	0
T12	0	578	0	0
T13	0	1108	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	243	0	0
T65	0	350	0	0
T66	0	614	0	0
T67	0	368	0	0
T68	1943	0	0	0
T111	0	624	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	115157	0	0
T2	2514	1131	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	404	0	0
T7	0	613	0	0
T12	0	579	0	0
T13	0	1109	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	244	0	0
T65	0	351	0	0
T66	0	615	0	0
T67	0	369	0	0
T68	1943	0	0	0
T111	0	625	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188125233	187979997	0	0
T1	1409	1327	0	0
T2	2270	2152	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0