Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	677022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5837438

1

T1

51

T2

7

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1704703	1			T1	28		T2	5		T3	1
values[0x0]	2229838	1			T1	28		T2	3		T3	5
values[0x1]	2579919	1			T1	26		T2	8		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	330541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6183919

1

T1

60

T2

10

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24689	1			T25	2		T26	5		T109	3
valid_sources[0x01]	29011	1			T2	1		T14	1		T25	2
valid_sources[0x02]	25496	1			T4	2		T25	2		T26	1
valid_sources[0x03]	24381	1			T4	1		T19	3		T25	1
valid_sources[0x04]	24926	1			T25	2		T219	1		T153	2
valid_sources[0x05]	24622	1			T25	5		T151	2		T155	2
valid_sources[0x06]	25499	1			T4	1		T9	7		T25	2
valid_sources[0x07]	25737	1			T25	1		T151	3		T244	2
valid_sources[0x08]	24805	1			T109	1		T151	2		T153	3
valid_sources[0x09]	25197	1			T4	2		T19	1		T26	5
valid_sources[0x0a]	24604	1			T1	1		T4	1		T19	3
valid_sources[0x0b]	23664	1			T25	1		T26	3		T109	3
valid_sources[0x0c]	25160	1			T3	1		T25	1		T151	1
valid_sources[0x0d]	24983	1			T4	1		T19	1		T109	1
valid_sources[0x0e]	26193	1			T4	2		T19	1		T25	3
valid_sources[0x0f]	25933	1			T25	1		T109	1		T151	1
valid_sources[0x10]	26250	1			T25	1		T26	1		T109	1
valid_sources[0x11]	24631	1			T25	1		T26	6		T244	3
valid_sources[0x12]	24857	1			T21	16		T25	2		T109	1
valid_sources[0x13]	23235	1			T4	2		T14	1		T25	2
valid_sources[0x14]	24893	1			T25	4		T109	3		T151	3
valid_sources[0x15]	25358	1			T19	1		T25	3		T26	3
valid_sources[0x16]	26610	1			T4	1		T19	2		T26	3
valid_sources[0x17]	26047	1			T1	3		T25	2		T109	2
valid_sources[0x18]	24377	1			T4	1		T25	1		T26	3
valid_sources[0x19]	24407	1			T26	3		T219	1		T151	1
valid_sources[0x1a]	22725	1			T4	1		T25	1		T26	1
valid_sources[0x1b]	27322	1			T26	5		T109	2		T151	3
valid_sources[0x1c]	26708	1			T4	2		T5	1		T25	2
valid_sources[0x1d]	25563	1			T4	3		T25	1		T26	2
valid_sources[0x1e]	26018	1			T19	1		T25	3		T109	1
valid_sources[0x1f]	23565	1			T25	1		T26	3		T109	1
valid_sources[0x20]	23930	1			T4	2		T25	4		T26	2
valid_sources[0x21]	24305	1			T4	1		T25	2		T26	5
valid_sources[0x22]	26661	1			T4	1		T26	2		T109	2
valid_sources[0x23]	26167	1			T4	3		T5	223		T19	1
valid_sources[0x24]	24031	1			T25	2		T26	3		T244	2
valid_sources[0x25]	26429	1			T26	1		T109	1		T153	2
valid_sources[0x26]	25310	1			T3	1		T4	1		T25	2
valid_sources[0x27]	23990	1			T4	1		T26	2		T109	3
valid_sources[0x28]	26111	1			T4	1		T109	1		T151	3
valid_sources[0x29]	23411	1			T3	1		T26	1		T109	2
valid_sources[0x2a]	25825	1			T25	1		T26	2		T109	1
valid_sources[0x2b]	26483	1			T4	1		T20	28		T26	5
valid_sources[0x2c]	23704	1			T2	2		T4	2		T25	2
valid_sources[0x2d]	24302	1			T25	1		T26	3		T219	1
valid_sources[0x2e]	23003	1			T2	1		T4	1		T25	1
valid_sources[0x2f]	25368	1			T4	1		T19	4		T25	2
valid_sources[0x30]	26953	1			T19	5		T151	3		T244	1
valid_sources[0x31]	25918	1			T4	3		T5	1		T25	2
valid_sources[0x32]	23184	1			T25	1		T26	1		T219	2
valid_sources[0x33]	25846	1			T25	1		T26	1		T109	1
valid_sources[0x34]	26214	1			T4	1		T19	3		T25	1
valid_sources[0x35]	27260	1			T3	1		T26	3		T151	5
valid_sources[0x36]	25352	1			T1	3		T4	1		T25	3
valid_sources[0x37]	28987	1			T25	1		T109	1		T151	1
valid_sources[0x38]	25240	1			T25	3		T26	1		T27	3
valid_sources[0x39]	26169	1			T5	1		T26	2		T244	2
valid_sources[0x3a]	25558	1			T25	3		T109	1		T151	1
valid_sources[0x3b]	24633	1			T19	1		T25	1		T26	4
valid_sources[0x3c]	23070	1			T2	1		T25	3		T155	3
valid_sources[0x3d]	22746	1			T25	1		T109	2		T151	1
valid_sources[0x3e]	24817	1			T25	3		T26	1		T219	1
valid_sources[0x3f]	24815	1			T25	3		T219	2		T151	8
valid_sources[0x40]	25423	1			T25	1		T109	2		T151	4
valid_sources[0x41]	25564	1			T25	1		T26	1		T109	1
valid_sources[0x42]	26802	1			T4	3		T25	1		T26	2
valid_sources[0x43]	26421	1			T26	2		T27	8		T109	1
valid_sources[0x44]	23214	1			T4	2		T26	1		T109	1
valid_sources[0x45]	24915	1			T3	1		T4	1		T5	1
valid_sources[0x46]	24856	1			T1	4		T25	3		T109	1
valid_sources[0x47]	26712	1			T4	2		T19	1		T14	1
valid_sources[0x48]	25759	1			T4	2		T25	2		T26	3
valid_sources[0x49]	25829	1			T4	1		T14	1		T26	2
valid_sources[0x4a]	25526	1			T4	2		T26	2		T219	1
valid_sources[0x4b]	26272	1			T26	3		T109	1		T219	1
valid_sources[0x4c]	24276	1			T26	1		T27	1		T151	3
valid_sources[0x4d]	25600	1			T4	1		T26	3		T244	2
valid_sources[0x4e]	28330	1			T25	3		T26	1		T152	7
valid_sources[0x4f]	27280	1			T4	1		T19	1		T25	2
valid_sources[0x50]	22872	1			T25	2		T26	6		T109	2
valid_sources[0x51]	24862	1			T25	1		T26	1		T151	5
valid_sources[0x52]	25523	1			T4	1		T25	1		T26	2
valid_sources[0x53]	24152	1			T1	1		T3	2		T19	3
valid_sources[0x54]	26269	1			T219	1		T151	1		T244	2
valid_sources[0x55]	27849	1			T25	1		T26	2		T151	3
valid_sources[0x56]	25994	1			T2	1		T4	2		T25	2
valid_sources[0x57]	24915	1			T4	1		T26	2		T109	1
valid_sources[0x58]	25159	1			T4	1		T25	2		T26	1
valid_sources[0x59]	27224	1			T4	4		T20	11		T25	1
valid_sources[0x5a]	24941	1			T25	1		T109	1		T155	2
valid_sources[0x5b]	26341	1			T25	2		T26	1		T109	1
valid_sources[0x5c]	25207	1			T4	1		T25	1		T26	2
valid_sources[0x5d]	26048	1			T25	1		T26	2		T153	4
valid_sources[0x5e]	27062	1			T25	3		T26	2		T244	3
valid_sources[0x5f]	26297	1			T25	3		T109	2		T219	2
valid_sources[0x60]	24064	1			T26	1		T151	2		T244	2
valid_sources[0x61]	25213	1			T2	1		T25	2		T151	4
valid_sources[0x62]	26008	1			T25	2		T26	1		T156	2
valid_sources[0x63]	25471	1			T9	8		T25	1		T26	1
valid_sources[0x64]	26580	1			T25	1		T26	2		T109	2
valid_sources[0x65]	27437	1			T4	2		T26	1		T151	1
valid_sources[0x66]	23079	1			T4	2		T14	1		T25	1
valid_sources[0x67]	26740	1			T109	1		T151	4		T155	2
valid_sources[0x68]	25329	1			T109	2		T219	1		T155	1
valid_sources[0x69]	26014	1			T3	1		T25	2		T26	1
valid_sources[0x6a]	27051	1			T26	1		T109	2		T153	3
valid_sources[0x6b]	25131	1			T4	4		T5	1		T26	3
valid_sources[0x6c]	25978	1			T4	1		T19	2		T26	4
valid_sources[0x6d]	24546	1			T25	2		T26	3		T151	5
valid_sources[0x6e]	22986	1			T26	4		T109	1		T244	2
valid_sources[0x6f]	26046	1			T19	1		T25	3		T26	2
valid_sources[0x70]	24038	1			T25	2		T26	3		T151	3
valid_sources[0x71]	27528	1			T2	2		T26	1		T27	19
valid_sources[0x72]	27599	1			T19	3		T25	2		T26	2
valid_sources[0x73]	24752	1			T25	2		T26	2		T219	2
valid_sources[0x74]	24564	1			T4	3		T14	1		T25	1
valid_sources[0x75]	26512	1			T25	2		T151	6		T244	2
valid_sources[0x76]	26127	1			T109	1		T151	1		T153	1
valid_sources[0x77]	25257	1			T26	1		T109	2		T151	2
valid_sources[0x78]	25623	1			T25	1		T109	2		T244	2
valid_sources[0x79]	25244	1			T19	1		T25	1		T26	3
valid_sources[0x7a]	25967	1			T19	2		T25	1		T109	1
valid_sources[0x7b]	25061	1			T4	1		T20	13		T21	3
valid_sources[0x7c]	23029	1			T4	3		T19	8		T25	1
valid_sources[0x7d]	25592	1			T25	2		T26	1		T109	2
valid_sources[0x7e]	25555	1			T9	3		T14	1		T25	1
valid_sources[0x7f]	26589	1			T4	1		T25	2		T26	1
valid_sources[0x80]	25627	1			T26	1		T219	1		T151	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1463993

1

T1

1

T2

1

T4

2

values[0x0]

all_enables

biggest_size

2186696

1

T1

27

T2

3

T5

27

values[0x1]

all_enables

biggest_size

2186749

1

T1

23

T2

3

T3

1