Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2460	1		T1	4	T5	2	T19	1
non_zero_bins[1]	1786	1		T1	2	T11	1	T54	2
zero	7775	1		T1	2	T2	3	T5	11

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	486	1		T5	1	T82	13	T96	7
uni	3326	1		T1	1	T5	4	T19	1
gen	3615	1		T1	4	T2	1	T5	4
res	808	1		T1	2	T19	1	T9	2
ins	3786	1		T1	1	T2	2	T5	4

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8044

mubi_true

3977

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6018

pass

6003

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	52	1		T82	1	T96	1	T294	2
upd	non_zero_bins[0]	fail	mubi_true	68	1		T82	3	T96	1	T98	1
upd	non_zero_bins[0]	pass	mubi_false	48	1		T96	1	T100	1	T294	1
upd	non_zero_bins[0]	pass	mubi_true	64	1		T82	2	T96	2	T100	1
upd	non_zero_bins[1]	fail	mubi_false	42	1		T82	1	T96	1	T99	2
upd	non_zero_bins[1]	fail	mubi_true	48	1		T82	2	T98	1	T295	2
upd	non_zero_bins[1]	pass	mubi_false	43	1		T82	3	T96	1	T97	2
upd	non_zero_bins[1]	pass	mubi_true	38	1		T98	1	T296	1	T297	2
upd	zero	fail	mubi_false	15	1		T294	1	T298	2	T299	1
upd	zero	fail	mubi_true	23	1		T82	1	T295	1	T299	1
upd	zero	pass	mubi_false	22	1		T295	1	T300	1	T299	1
upd	zero	pass	mubi_true	23	1		T5	1	T99	1	T295	1
uni	zero	fail	mubi_false	1223	1		T19	1	T11	1	T54	1
uni	zero	fail	mubi_true	449	1		T5	1	T54	2	T55	1
uni	zero	pass	mubi_false	1182	1		T1	1	T5	2	T9	1
uni	zero	pass	mubi_true	472	1		T5	1	T54	1	T82	10
gen	non_zero_bins[0]	fail	mubi_false	207	1		T1	2	T19	1	T11	2
gen	non_zero_bins[0]	fail	mubi_true	235	1		T10	1	T82	5	T96	5
gen	non_zero_bins[0]	pass	mubi_false	202	1		T1	2	T11	3	T10	2
gen	non_zero_bins[0]	pass	mubi_true	246	1		T5	1	T9	1	T82	4
gen	non_zero_bins[1]	fail	mubi_false	142	1		T11	1	T82	4	T96	4
gen	non_zero_bins[1]	fail	mubi_true	175	1		T58	2	T82	2	T96	4
gen	non_zero_bins[1]	pass	mubi_false	175	1		T71	1	T82	3	T96	1
gen	non_zero_bins[1]	pass	mubi_true	171	1		T58	1	T82	1	T96	1
gen	zero	fail	mubi_false	816	1		T5	2	T19	1	T54	3
gen	zero	fail	mubi_true	198	1		T9	2	T28	1	T29	1
gen	zero	pass	mubi_false	851	1		T2	1	T5	1	T20	1
gen	zero	pass	mubi_true	197	1		T9	1	T82	1	T96	3
res	non_zero_bins[0]	fail	mubi_false	115	1		T11	1	T29	1	T82	1
res	non_zero_bins[0]	fail	mubi_true	88	1		T9	1	T56	1	T82	1
res	non_zero_bins[0]	pass	mubi_false	96	1		T11	1	T82	3	T96	1
res	non_zero_bins[0]	pass	mubi_true	105	1		T9	1	T54	1	T10	2
res	non_zero_bins[1]	fail	mubi_false	71	1		T1	1	T96	2	T102	1
res	non_zero_bins[1]	fail	mubi_true	52	1		T82	2	T96	1	T97	1
res	non_zero_bins[1]	pass	mubi_false	52	1		T1	1	T96	2	T102	1
res	non_zero_bins[1]	pass	mubi_true	66	1		T97	1	T99	1	T295	3
res	zero	fail	mubi_false	45	1		T19	1	T96	1	T78	1
res	zero	fail	mubi_true	34	1		T58	2	T97	1	T295	1
res	zero	pass	mubi_false	47	1		T82	1	T78	1	T296	1
res	zero	pass	mubi_true	37	1		T295	1	T294	1	T301	2
ins	non_zero_bins[0]	fail	mubi_false	224	1		T9	1	T82	6	T96	4
ins	non_zero_bins[0]	fail	mubi_true	243	1		T5	1	T11	1	T82	8
ins	non_zero_bins[0]	pass	mubi_false	232	1		T54	1	T55	1	T71	1
ins	non_zero_bins[0]	pass	mubi_true	235	1		T82	4	T96	4	T296	1
ins	non_zero_bins[1]	fail	mubi_false	196	1		T82	2	T96	4	T98	1
ins	non_zero_bins[1]	fail	mubi_true	178	1		T54	1	T10	1	T82	3
ins	non_zero_bins[1]	pass	mubi_false	172	1		T82	4	T96	7	T296	1
ins	non_zero_bins[1]	pass	mubi_true	165	1		T54	1	T55	1	T82	1
ins	zero	fail	mubi_false	890	1		T5	2	T21	1	T14	1
ins	zero	fail	mubi_true	189	1		T2	1	T14	1	T82	4
ins	zero	pass	mubi_false	884	1		T5	1	T54	3	T55	1
ins	zero	pass	mubi_true	178	1		T1	1	T2	1	T19	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded