Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T5,T19
DataWait	75	Covered	T1,T5,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T88,T110,T111
AckPls->Idle	85	Covered	T1,T5,T19
DataWait->AckPls	80	Covered	T1,T5,T19
DataWait->Disabled	107	Covered	T73,T79,T68
DataWait->Error	99	Covered	T38,T39,T112
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T1,T5,T19
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T6

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T1,T5,T19
Idle	-	1	0	-	Covered	T1,T2,T5
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T1,T5,T19
DataWait	-	-	-	0	Covered	T1,T5,T19
AckPls	-	-	-	-	Covered	T1,T5,T19
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T4,T6,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1541202866	957982	0	0
FpvSecCmErrorStEscalate_A	1541202866	963953	0	0
u_state_regs_A	1541166212	1540104599	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541202866	957982	0	0
T2	4515	2534	0	0
T3	8183	0	0	0
T4	13482	8245	0	0
T5	54383	0	0	0
T6	10717	5830	0	0
T7	0	6118	0	0
T8	0	8253	0	0
T9	13027	0	0	0
T14	20601	8022	0	0
T15	0	2436	0	0
T19	7623	0	0	0
T20	10584	0	0	0
T21	7462	0	0	0
T38	0	1344	0	0
T60	0	7637	0	0
T113	0	2009	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541202866	963953	0	0
T2	4515	2541	0	0
T3	8183	0	0	0
T4	13482	8252	0	0
T5	54383	0	0	0
T6	10717	5837	0	0
T7	0	6125	0	0
T8	0	8260	0	0
T9	13027	0	0	0
T14	20601	8029	0	0
T15	0	2443	0	0
T19	7623	0	0	0
T20	10584	0	0	0
T21	7462	0	0	0
T38	0	1351	0	0
T60	0	7644	0	0
T113	0	2016	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541166212	1540104599	0	0
T1	13062	12523	0	0
T2	4400	3553	0	0
T3	8183	7553	0	0
T4	13302	11958	0	0
T5	54383	51240	0	0
T9	13027	12460	0	0
T14	19454	18467	0	0
T19	7623	7196	0	0
T20	10584	10192	0	0
T21	7407	6322	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T28,T29
DataWait	75	Covered	T11,T28,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T11,T28,T29
DataWait->AckPls	80	Covered	T11,T28,T29
DataWait->Disabled	107	Covered	T114,T115
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T11,T28,T29
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T11,T28,T29
Idle	-	1	0	-	Covered	T11,T28,T29
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T11,T28,T29
DataWait	-	-	-	0	Covered	T11,T28,T29
AckPls	-	-	-	-	Covered	T11,T28,T29
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	137176	0	0
FpvSecCmErrorStEscalate_A	220171838	138029	0	0
u_state_regs_A	220171838	220020179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	137176	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1185	0	0
T5	7769	0	0	0
T6	1531	840	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	138029	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1186	0	0
T5	7769	0	0	0
T6	1531	841	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T11,T28
DataWait	75	Covered	T1,T11,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T11,T28
DataWait->AckPls	80	Covered	T1,T11,T28
DataWait->Disabled	107	Covered	T116,T117,T118
DataWait->Error	99	Covered	T119,T120,T121
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T1,T11,T28
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T1,T11,T28
Idle	-	1	0	-	Covered	T1,T11,T28
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T1,T11,T28
DataWait	-	-	-	0	Covered	T1,T11,T28
AckPls	-	-	-	-	Covered	T1,T11,T28
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	137176	0	0
FpvSecCmErrorStEscalate_A	220171838	138029	0	0
u_state_regs_A	220171838	220020179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	137176	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1185	0	0
T5	7769	0	0	0
T6	1531	840	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	138029	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1186	0	0
T5	7769	0	0	0
T6	1531	841	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T11,T28
DataWait	75	Covered	T1,T11,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T11,T28
DataWait->AckPls	80	Covered	T1,T11,T28
DataWait->Disabled	107	Covered	T79,T122,T123
DataWait->Error	99	Covered	T124,T125,T126
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T1,T11,T28
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T1,T11,T28
Idle	-	1	0	-	Covered	T1,T11,T28
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T1,T11,T28
DataWait	-	-	-	0	Covered	T1,T11,T28
AckPls	-	-	-	-	Covered	T1,T11,T28
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	137176	0	0
FpvSecCmErrorStEscalate_A	220171838	138029	0	0
u_state_regs_A	220171838	220020179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	137176	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1185	0	0
T5	7769	0	0	0
T6	1531	840	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	138029	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1186	0	0
T5	7769	0	0	0
T6	1531	841	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T11,T28
DataWait	75	Covered	T1,T11,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T11,T28
DataWait->AckPls	80	Covered	T1,T11,T28
DataWait->Disabled	107	Covered	T75,T127,T128
DataWait->Error	99	Covered	T129,T130,T131
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T1,T11,T28
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T1,T11,T28
Idle	-	1	0	-	Covered	T1,T11,T28
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T1,T11,T28
DataWait	-	-	-	0	Covered	T1,T11,T28
AckPls	-	-	-	-	Covered	T1,T11,T28
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	137176	0	0
FpvSecCmErrorStEscalate_A	220171838	138029	0	0
u_state_regs_A	220171838	220020179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	137176	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1185	0	0
T5	7769	0	0	0
T6	1531	840	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	138029	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1186	0	0
T5	7769	0	0	0
T6	1531	841	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T29,T30
DataWait	75	Covered	T28,T29,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T29,T30
DataWait->AckPls	80	Covered	T28,T29,T30
DataWait->Disabled	107	Covered	T30,T132
DataWait->Error	99	Covered	T6,T7,T133
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T28,T29,T30
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T28,T29,T30
Idle	-	1	0	-	Covered	T28,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T28,T29,T30
DataWait	-	-	-	0	Covered	T28,T29,T30
AckPls	-	-	-	-	Covered	T28,T29,T30
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	137176	0	0
FpvSecCmErrorStEscalate_A	220171838	138029	0	0
u_state_regs_A	220171838	220020179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	137176	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1185	0	0
T5	7769	0	0	0
T6	1531	840	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	138029	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1186	0	0
T5	7769	0	0	0
T6	1531	841	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T5,T19,T9
DataWait	75	Covered	T5,T19,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T111
AckPls->Idle	85	Covered	T5,T19,T9
DataWait->AckPls	80	Covered	T5,T19,T9
DataWait->Disabled	107	Covered	T134,T135,T136
DataWait->Error	99	Covered	T38,T39,T112
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T22,T41,T137
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T5,T19,T9
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T14,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T5,T19,T9
Idle	-	1	0	-	Covered	T2,T5,T19
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T5,T19,T9
DataWait	-	-	-	0	Covered	T5,T19,T9
AckPls	-	-	-	-	Covered	T5,T19,T9
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T4,T6,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	134926	0	0
FpvSecCmErrorStEscalate_A	220171838	135779	0	0
u_state_regs_A	220135184	219983525	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	134926	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1135	0	0
T5	7769	0	0	0
T6	1531	790	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	135779	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1136	0	0
T5	7769	0	0	0
T6	1531	791	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220135184	219983525	0	0
T1	1866	1789	0	0
T2	530	409	0	0
T3	1169	1079	0	0
T4	1746	1554	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	1796	1655	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1011	856	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T30,T73

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T28,T29
DataWait	75	Covered	T14,T11,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T4
Error	99	Covered	T2,T4,T14
Idle	68	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T88,T110
AckPls->Idle	85	Covered	T11,T28,T29
DataWait->AckPls	80	Covered	T11,T28,T29
DataWait->Disabled	107	Covered	T73,T68,T138
DataWait->Error	99	Covered	T14,T113,T139
Disabled->EndPointClear	63	Covered	T1,T2,T4
Disabled->Error	99	Covered	T22,T23,T24
EndPointClear->Disabled	107	Covered	T98,T77,T74
EndPointClear->Error	99	Covered	T4,T22,T41
EndPointClear->Idle	68	Covered	T1,T2,T4
Idle->DataWait	75	Covered	T14,T11,T28
Idle->Disabled	107	Covered	T5,T21,T54
Idle->Error	99	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T4
Idle	-	1	1	-	Covered	T11,T28,T29
Idle	-	1	0	-	Covered	T14,T11,T28
Idle	-	0	-	-	Covered	T1,T2,T4
DataWait	-	-	-	1	Covered	T11,T28,T29
DataWait	-	-	-	0	Covered	T14,T11,T28
AckPls	-	-	-	-	Covered	T11,T28,T29
Error	-	-	-	-	Covered	T2,T4,T14
default	-	-	-	-	Covered	T22,T23,T24

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T14
0	1	Covered	T21,T30,T73
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220171838	137176	0	0
FpvSecCmErrorStEscalate_A	220171838	138029	0	0
u_state_regs_A	220171838	220020179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	137176	0	0
T2	645	362	0	0
T3	1169	0	0	0
T4	1926	1185	0	0
T5	7769	0	0	0
T6	1531	840	0	0
T7	0	874	0	0
T8	0	1179	0	0
T9	1861	0	0	0
T14	2943	1146	0	0
T15	0	348	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	192	0	0
T60	0	1091	0	0
T113	0	287	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	138029	0	0
T2	645	363	0	0
T3	1169	0	0	0
T4	1926	1186	0	0
T5	7769	0	0	0
T6	1531	841	0	0
T7	0	875	0	0
T8	0	1180	0	0
T9	1861	0	0	0
T14	2943	1147	0	0
T15	0	349	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T38	0	193	0	0
T60	0	1092	0	0
T113	0	288	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0