Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 0 49 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 0 12 100.00 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 4030 1 T1 2 T3 1 T7 1
auto[RES] 859 1 T10 2 T11 1 T5 12
auto[GEN] 3862 1 T1 1 T3 1 T7 1
auto[UPD] 581 1 T5 14 T27 1 T33 1
auto[UNI] 3630 1 T1 2 T3 1 T10 1


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4466 1 T1 3 T10 3 T11 5
no_cmd_data 8496 1 T1 2 T3 3 T7 2


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 11872 1 T1 5 T3 3 T10 4
reseed_cmd 297 1 T10 1 T11 1 T12 1
generate_cmd 295 1 T10 1 T11 1 T12 1
boot_gen_cmd 249 1 T7 1 T15 3 T27 1
boot_ins_cmd 249 1 T7 1 T15 3 T27 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 4053 1 T1 3 T7 1 T10 3
false 8909 1 T1 2 T3 3 T7 1


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1150 1 T1 2 T7 1 T10 3
one 1978 1 T3 1 T7 1 T10 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 11193 1 T1 5 T3 3 T10 2
boot_mode 714 1 T7 2 T15 6 T27 4
auto_mode 1055 1 T10 4 T11 4 T12 4


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 125 1 T1 1 T11 1 T20 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 62 1 T27 1 T33 1 T63 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 113 1 T26 1 T67 1 T31 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 43 1 T10 1 T48 1 T276 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 21 1 T97 1 T346 1 T347 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 93 1 T11 1 T12 1 T6 2
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 30 1 T26 1 T31 1 T51 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 7 1 T348 1 T349 1 T350 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 61 1 T27 1 T63 1 T97 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 29 1 T10 1 T276 1 T237 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1517 1 T3 1 T4 1 T5 21
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 3 1 T351 1 T352 1 T353 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 60 1 T6 1 T13 1 T29 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 761 1 T1 1 T20 2 T5 12
auto[INS] some_cmd_data true boot_mode sw_cmd_req 9 1 T63 1 T347 1 T59 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 82 1 T11 1 T12 1 T67 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 782 1 T1 1 T5 24 T32 1
auto[INS] some_cmd_data false boot_mode sw_cmd_req 15 1 T318 1 T346 1 T351 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 78 1 T26 1 T31 1 T29 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 200 1 T5 4 T92 3 T94 1
auto[INS] no_cmd_data true boot_mode sw_cmd_req 2 1 T354 1 T355 1 - -
auto[INS] no_cmd_data true auto_mode sw_cmd_req 68 1 T10 1 T17 1 T18 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1724 1 T3 1 T4 1 T5 27
auto[INS] no_cmd_data false boot_mode sw_cmd_req 4 1 T356 1 T335 1 T357 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 153 1 T7 1 T15 2 T27 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 56 1 T6 1 T13 1 T8 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 211 1 T5 6 T92 3 T94 2
auto[RES] some_cmd_data true boot_mode sw_cmd_req 10 1 T277 1 T358 1 T285 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 96 1 T10 1 T11 1 T6 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 209 1 T5 4 T92 1 T94 1
auto[RES] some_cmd_data false boot_mode sw_cmd_req 13 1 T97 1 T34 1 T282 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 107 1 T12 1 T6 1 T29 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 41 1 T5 2 T98 2 T271 1
auto[RES] no_cmd_data true boot_mode sw_cmd_req 7 1 T288 1 T348 1 T359 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 30 1 T39 1 T43 1 T279 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 51 1 T92 1 T96 1 T360 1
auto[RES] no_cmd_data false boot_mode sw_cmd_req 2 1 T340 1 T330 1 - -
auto[RES] no_cmd_data false auto_mode reseed_cmd 64 1 T6 1 T31 1 T29 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 424 1 T5 10 T32 1 T317 1
auto[UPD] some_cmd_data boot_mode sw_cmd_req 25 1 T33 1 T30 1 T361 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 107 1 T5 4 T94 2 T93 1
auto[UPD] no_cmd_data boot_mode sw_cmd_req 6 1 T27 1 T76 1 T349 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3577 1 T1 2 T3 1 T10 1
auto[UNI] boot_mode sw_cmd_req 30 1 T63 1 T318 1 T346 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 284 1 T10 1 T11 1 T12 1
auto[RES] auto_mode sw_cmd_req 18 1 T10 1 T48 1 T276 1
auto[GEN] auto_mode sw_cmd_req 119 1 T17 2 T18 2 T26 1
auto[UPD] auto_mode sw_cmd_req 19 1 T69 1 T74 1 T362 1
auto[UNI] auto_mode sw_cmd_req 23 1 T11 1 T12 1 T363 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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