Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	661015	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5687505

1

T1

22

T2

4

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1658369	1			T1	176		T2	1		T3	32
values[0x0]	2174014	1			T1	11		T2	6		T3	4
values[0x1]	2516137	1			T1	14		T2	5		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	321530	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6026990

1

T1

82

T2

6

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25150	1			T5	538		T24	1		T201	1
valid_sources[0x01]	26588	1			T1	2		T5	584		T6	5
valid_sources[0x02]	24822	1			T5	610		T6	1		T25	1
valid_sources[0x03]	26622	1			T1	2		T5	587		T40	1
valid_sources[0x04]	25178	1			T1	1		T3	1		T5	599
valid_sources[0x05]	26708	1			T5	547		T24	2		T201	13
valid_sources[0x06]	26814	1			T5	622		T6	4		T193	4
valid_sources[0x07]	23520	1			T1	2		T5	561		T12	1
valid_sources[0x08]	27128	1			T1	3		T5	606		T6	5
valid_sources[0x09]	25273	1			T5	578		T201	4		T202	1
valid_sources[0x0a]	23759	1			T20	2		T5	567		T6	2
valid_sources[0x0b]	24509	1			T1	1		T5	589		T202	1
valid_sources[0x0c]	24681	1			T5	548		T6	7		T25	1
valid_sources[0x0d]	24206	1			T5	525		T6	2		T121	11
valid_sources[0x0e]	25843	1			T1	3		T5	554		T12	1
valid_sources[0x0f]	25826	1			T1	1		T5	592		T41	3
valid_sources[0x10]	24201	1			T20	1		T5	564		T6	3
valid_sources[0x11]	24476	1			T1	1		T11	12		T5	562
valid_sources[0x12]	25202	1			T1	2		T5	585		T6	5
valid_sources[0x13]	24538	1			T1	2		T5	555		T12	1
valid_sources[0x14]	24365	1			T5	602		T6	1		T40	1
valid_sources[0x15]	24422	1			T1	1		T10	2		T5	533
valid_sources[0x16]	24600	1			T1	2		T5	586		T6	1
valid_sources[0x17]	25878	1			T5	619		T6	4		T201	1
valid_sources[0x18]	24146	1			T5	585		T12	1		T6	8
valid_sources[0x19]	27188	1			T5	530		T12	1		T41	2
valid_sources[0x1a]	24056	1			T4	3		T5	555		T12	1
valid_sources[0x1b]	24999	1			T5	551		T12	1		T6	2
valid_sources[0x1c]	24797	1			T1	1		T5	598		T24	3
valid_sources[0x1d]	25114	1			T1	1		T20	3		T5	616
valid_sources[0x1e]	24512	1			T1	2		T5	539		T6	2
valid_sources[0x1f]	25257	1			T5	580		T25	2		T201	10
valid_sources[0x20]	23713	1			T5	590		T12	1		T6	1
valid_sources[0x21]	24876	1			T1	2		T5	546		T6	2
valid_sources[0x22]	24511	1			T1	2		T5	555		T6	10
valid_sources[0x23]	23928	1			T1	2		T5	596		T6	1
valid_sources[0x24]	26007	1			T1	1		T20	8		T5	578
valid_sources[0x25]	23819	1			T20	5		T5	570		T6	5
valid_sources[0x26]	21920	1			T11	1		T5	512		T12	2
valid_sources[0x27]	24422	1			T5	528		T6	4		T202	1
valid_sources[0x28]	25287	1			T5	562		T6	1		T193	2
valid_sources[0x29]	23626	1			T1	2		T5	587		T193	4
valid_sources[0x2a]	24278	1			T1	2		T10	7		T5	564
valid_sources[0x2b]	23522	1			T5	542		T121	1		T193	4
valid_sources[0x2c]	23281	1			T1	1		T3	1		T11	9
valid_sources[0x2d]	25178	1			T5	536		T6	7		T25	1
valid_sources[0x2e]	26455	1			T1	1		T20	1		T5	546
valid_sources[0x2f]	25729	1			T5	559		T6	8		T40	3
valid_sources[0x30]	24366	1			T5	538		T121	1		T193	3
valid_sources[0x31]	25881	1			T5	534		T202	1		T193	4
valid_sources[0x32]	26018	1			T1	1		T20	1		T5	599
valid_sources[0x33]	23520	1			T1	1		T10	1		T5	640
valid_sources[0x34]	27199	1			T1	1		T5	573		T6	1
valid_sources[0x35]	23106	1			T20	2		T5	563		T12	2
valid_sources[0x36]	25257	1			T1	3		T5	646		T12	1
valid_sources[0x37]	25264	1			T5	565		T6	2		T121	2
valid_sources[0x38]	25518	1			T5	553		T202	1		T193	5
valid_sources[0x39]	23614	1			T1	3		T5	541		T6	4
valid_sources[0x3a]	22241	1			T1	1		T3	37		T11	8
valid_sources[0x3b]	25640	1			T2	2		T5	538		T24	1
valid_sources[0x3c]	26857	1			T1	1		T4	3		T5	621
valid_sources[0x3d]	25088	1			T1	1		T5	577		T120	114
valid_sources[0x3e]	23280	1			T1	1		T11	2		T5	556
valid_sources[0x3f]	22954	1			T1	2		T5	570		T6	1
valid_sources[0x40]	23850	1			T11	8		T5	611		T40	3
valid_sources[0x41]	24495	1			T20	3		T5	612		T6	3
valid_sources[0x42]	24260	1			T1	3		T7	1		T5	585
valid_sources[0x43]	22698	1			T1	1		T5	570		T201	18
valid_sources[0x44]	24424	1			T1	1		T5	533		T6	4
valid_sources[0x45]	26018	1			T5	613		T6	1		T201	18
valid_sources[0x46]	24817	1			T1	1		T5	533		T6	4
valid_sources[0x47]	24194	1			T1	2		T5	569		T12	1
valid_sources[0x48]	26817	1			T1	3		T5	637		T24	1
valid_sources[0x49]	24945	1			T1	2		T5	596		T41	2
valid_sources[0x4a]	25053	1			T20	1		T5	556		T40	1
valid_sources[0x4b]	26712	1			T5	563		T6	10		T24	2
valid_sources[0x4c]	24715	1			T5	505		T6	1		T121	1
valid_sources[0x4d]	23807	1			T1	1		T5	547		T6	1
valid_sources[0x4e]	25322	1			T5	582		T6	4		T41	1
valid_sources[0x4f]	22358	1			T1	1		T10	1		T5	603
valid_sources[0x50]	23744	1			T1	1		T5	581		T6	7
valid_sources[0x51]	24141	1			T1	1		T5	578		T12	1
valid_sources[0x52]	25251	1			T1	1		T5	570		T12	1
valid_sources[0x53]	25360	1			T1	2		T5	572		T25	1
valid_sources[0x54]	25509	1			T5	542		T6	1		T201	2
valid_sources[0x55]	24995	1			T1	2		T11	1		T5	531
valid_sources[0x56]	24675	1			T1	2		T5	544		T6	4
valid_sources[0x57]	25867	1			T5	534		T6	2		T202	1
valid_sources[0x58]	25433	1			T5	596		T6	1		T25	1
valid_sources[0x59]	22904	1			T1	1		T5	577		T6	12
valid_sources[0x5a]	23352	1			T20	1		T5	581		T24	1
valid_sources[0x5b]	24547	1			T5	554		T201	16		T121	20
valid_sources[0x5c]	26765	1			T1	2		T4	6		T5	623
valid_sources[0x5d]	23464	1			T1	1		T20	1		T5	539
valid_sources[0x5e]	24768	1			T1	1		T5	571		T6	7
valid_sources[0x5f]	24485	1			T5	641		T6	2		T25	1
valid_sources[0x60]	23019	1			T1	1		T5	532		T6	9
valid_sources[0x61]	24616	1			T1	2		T5	519		T202	1
valid_sources[0x62]	25364	1			T1	1		T11	5		T5	567
valid_sources[0x63]	24555	1			T10	1		T5	562		T6	2
valid_sources[0x64]	25077	1			T1	3		T5	607		T40	2
valid_sources[0x65]	24945	1			T1	2		T5	522		T24	1
valid_sources[0x66]	24082	1			T1	1		T5	572		T12	1
valid_sources[0x67]	24532	1			T1	3		T5	568		T12	2
valid_sources[0x68]	25885	1			T5	569		T6	2		T25	1
valid_sources[0x69]	25582	1			T1	1		T11	4		T5	564
valid_sources[0x6a]	24463	1			T20	2		T5	565		T202	3
valid_sources[0x6b]	23933	1			T10	3		T5	545		T25	2
valid_sources[0x6c]	23326	1			T5	506		T12	1		T6	1
valid_sources[0x6d]	26804	1			T1	2		T5	513		T6	1
valid_sources[0x6e]	24572	1			T1	1		T10	2		T11	1
valid_sources[0x6f]	24817	1			T1	1		T10	13		T5	598
valid_sources[0x70]	25225	1			T5	536		T6	1		T40	1
valid_sources[0x71]	25392	1			T5	627		T6	1		T25	1
valid_sources[0x72]	24395	1			T5	576		T6	9		T201	10
valid_sources[0x73]	24577	1			T5	676		T193	2		T170	2
valid_sources[0x74]	26422	1			T5	626		T6	5		T193	2
valid_sources[0x75]	26198	1			T1	1		T5	544		T12	1
valid_sources[0x76]	22718	1			T5	571		T6	4		T193	4
valid_sources[0x77]	23411	1			T5	556		T6	6		T41	1
valid_sources[0x78]	25241	1			T5	597		T6	1		T202	1
valid_sources[0x79]	25264	1			T1	1		T20	2		T5	594
valid_sources[0x7a]	24629	1			T1	1		T5	586		T6	9
valid_sources[0x7b]	22661	1			T5	573		T6	1		T233	1
valid_sources[0x7c]	23966	1			T1	1		T5	591		T6	7
valid_sources[0x7d]	24405	1			T11	17		T5	544		T6	1
valid_sources[0x7e]	26063	1			T2	5		T5	610		T6	5
valid_sources[0x7f]	26630	1			T10	1		T11	2		T5	568
valid_sources[0x80]	25021	1			T1	1		T5	590		T201	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1428757

1

T1

2

T2

1

T3

2

values[0x0]

all_enables

biggest_size

2131363

1

T1

9

T2

2

T3

2

values[0x1]

all_enables

biggest_size

2127385

1

T1

11

T2

1

T3

1