Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2510	1		T1	3	T11	2	T20	1
non_zero_bins[1]	1860	1		T10	2	T11	8	T5	39
zero	8210	1		T1	2	T3	3	T7	4

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	538	1		T5	14	T33	1	T51	1
uni	3473	1		T1	2	T3	1	T5	67
gen	3806	1		T1	1	T3	1	T7	2
res	822	1		T10	2	T11	2	T5	12
ins	3941	1		T1	2	T3	1	T7	2

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8545

mubi_true

4035

T10

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6200

pass

6380

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	66	1		T5	1	T94	1	T98	2
upd	non_zero_bins[0]	fail	mubi_true	79	1		T5	2	T33	1	T92	1
upd	non_zero_bins[0]	pass	mubi_false	56	1		T5	1	T94	1	T98	1
upd	non_zero_bins[0]	pass	mubi_true	53	1		T5	3	T92	1	T94	1
upd	non_zero_bins[1]	fail	mubi_false	53	1		T5	1	T51	1	T271	1
upd	non_zero_bins[1]	fail	mubi_true	35	1		T5	1	T92	1	T94	1
upd	non_zero_bins[1]	pass	mubi_false	55	1		T94	1	T272	1	T273	1
upd	non_zero_bins[1]	pass	mubi_true	33	1		T5	1	T274	1	T98	1
upd	zero	fail	mubi_false	32	1		T5	3	T94	1	T96	1
upd	zero	fail	mubi_true	24	1		T5	1	T94	1	T98	1
upd	zero	pass	mubi_false	29	1		T93	1	T272	2	T275	2
upd	zero	pass	mubi_true	23	1		T98	1	T271	1	T96	1
uni	zero	fail	mubi_false	1242	1		T5	25	T12	1	T13	1
uni	zero	fail	mubi_true	452	1		T5	9	T50	1	T92	8
uni	zero	pass	mubi_false	1299	1		T1	1	T3	1	T5	28
uni	zero	pass	mubi_true	480	1		T1	1	T5	5	T50	2
gen	non_zero_bins[0]	fail	mubi_false	212	1		T5	6	T12	1	T26	1
gen	non_zero_bins[0]	fail	mubi_true	261	1		T1	1	T5	4	T33	1
gen	non_zero_bins[0]	pass	mubi_false	219	1		T5	5	T12	2	T26	1
gen	non_zero_bins[0]	pass	mubi_true	228	1		T5	4	T93	1	T98	4
gen	non_zero_bins[1]	fail	mubi_false	166	1		T11	4	T5	3	T50	1
gen	non_zero_bins[1]	fail	mubi_true	160	1		T5	4	T92	2	T98	1
gen	non_zero_bins[1]	pass	mubi_false	172	1		T11	3	T5	4	T92	1
gen	non_zero_bins[1]	pass	mubi_true	177	1		T5	3	T92	2	T94	3
gen	zero	fail	mubi_false	869	1		T3	1	T10	1	T4	1
gen	zero	fail	mubi_true	207	1		T7	2	T15	1	T17	2
gen	zero	pass	mubi_false	921	1		T10	1	T5	10	T27	1
gen	zero	pass	mubi_true	214	1		T12	1	T18	1	T64	1
res	non_zero_bins[0]	fail	mubi_false	91	1		T29	1	T276	1	T98	1
res	non_zero_bins[0]	fail	mubi_true	101	1		T11	1	T5	3	T13	1
res	non_zero_bins[0]	pass	mubi_false	102	1		T5	1	T29	2	T48	1
res	non_zero_bins[0]	pass	mubi_true	91	1		T11	1	T26	2	T13	1
res	non_zero_bins[1]	fail	mubi_false	68	1		T5	1	T94	1	T96	1
res	non_zero_bins[1]	fail	mubi_true	49	1		T10	1	T5	2	T277	1
res	non_zero_bins[1]	pass	mubi_false	77	1		T5	2	T12	2	T93	1
res	non_zero_bins[1]	pass	mubi_true	73	1		T10	1	T5	1	T67	1
res	zero	fail	mubi_false	40	1		T29	1	T69	2	T278	1
res	zero	fail	mubi_true	47	1		T5	1	T39	2	T279	2
res	zero	pass	mubi_false	43	1		T31	2	T29	1	T92	1
res	zero	pass	mubi_true	40	1		T5	1	T39	2	T98	2
ins	non_zero_bins[0]	fail	mubi_false	244	1		T5	9	T32	1	T50	1
ins	non_zero_bins[0]	fail	mubi_true	240	1		T20	1	T5	1	T29	1
ins	non_zero_bins[0]	pass	mubi_false	248	1		T1	1	T5	6	T48	1
ins	non_zero_bins[0]	pass	mubi_true	219	1		T1	1	T5	4	T12	1
ins	non_zero_bins[1]	fail	mubi_false	182	1		T5	5	T26	1	T31	1
ins	non_zero_bins[1]	fail	mubi_true	176	1		T11	1	T5	2	T67	1
ins	non_zero_bins[1]	pass	mubi_false	185	1		T5	4	T29	1	T50	1
ins	non_zero_bins[1]	pass	mubi_true	199	1		T5	5	T39	2	T51	1
ins	zero	fail	mubi_false	916	1		T4	1	T5	15	T33	1
ins	zero	fail	mubi_true	188	1		T10	1	T5	2	T15	1
ins	zero	pass	mubi_false	958	1		T3	1	T7	2	T5	12
ins	zero	pass	mubi_true	186	1		T5	2	T17	1	T18	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded