Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	100.00		96.30	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	99.26	100.00	100.00		96.30	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	100.00		96.30	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	100.00		96.30	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T7,T15,T27
1	1	0	1	Covered	T7,T15,T27
1	1	1	0	Covered	T1,T3,T10
1	1	1	1	Covered	T7,T10,T11

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T7,T28,T108
1	1	Covered	T7,T15,T27

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T29,T39,T37
1	1	Covered	T10,T11,T12

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	52	96.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T10,T11,T12
AutoCaptGenCnt	162	Covered	T10,T11,T12
AutoCaptReseedCnt	160	Covered	T10,T11,T12
AutoDispatch	142	Covered	T10,T11,T12
AutoFirstAckWait	135	Covered	T10,T11,T12
AutoLoadIns	90	Covered	T10,T11,T12
AutoSendGenCmd	170	Covered	T10,T11,T12
AutoSendReseedCmd	184	Covered	T10,T11,T12
BootCaptGenCnt	106	Covered	T7,T15,T27
BootDone	126	Covered	T7,T15,T27
BootGenAckWait	116	Covered	T7,T15,T27
BootInsAckWait	102	Covered	T7,T15,T27
BootLoadGen	98	Covered	T7,T15,T27
BootLoadIns	88	Covered	T7,T15,T27
BootPulse	121	Covered	T7,T15,T27
BootSendGenCmd	111	Covered	T7,T15,T27
Error	206	Covered	T6,T15,T64
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T3,T10

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T10,T11,T12
AutoAckWait->Error	206	Covered	T43,T81,T123
AutoAckWait->Idle	229	Covered	T29,T39,T37
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T10,T11,T12
AutoCaptGenCnt->Error	206	Covered	T124
AutoCaptGenCnt->Idle	229	Covered	T125,T126,T127
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T10,T11,T12
AutoCaptReseedCnt->Error	206	Covered	T128,T129
AutoCaptReseedCnt->Idle	229	Covered	T39,T130,T131
AutoDispatch->AutoCaptGenCnt	162	Covered	T10,T11,T12
AutoDispatch->AutoCaptReseedCnt	160	Covered	T10,T11,T12
AutoDispatch->Error	206	Not Covered
AutoDispatch->Idle	157	Covered	T10,T11,T12
AutoFirstAckWait->AutoDispatch	142	Covered	T10,T11,T12
AutoFirstAckWait->Error	206	Covered	T132
AutoFirstAckWait->Idle	229	Covered	T37,T133,T134
AutoLoadIns->AutoFirstAckWait	135	Covered	T10,T11,T12
AutoLoadIns->Error	206	Covered	T66,T135,T136
AutoLoadIns->Idle	229	Covered	T137,T138,T139
AutoSendGenCmd->AutoAckWait	177	Covered	T10,T11,T12
AutoSendGenCmd->Error	206	Covered	T8,T140,T141
AutoSendGenCmd->Idle	229	Covered	T29,T142,T143
AutoSendReseedCmd->AutoAckWait	191	Covered	T10,T11,T12
AutoSendReseedCmd->Error	206	Covered	T144
AutoSendReseedCmd->Idle	229	Covered	T145,T113,T146
BootCaptGenCnt->BootSendGenCmd	111	Covered	T7,T15,T27
BootCaptGenCnt->Error	206	Covered	T147
BootCaptGenCnt->Idle	229	Covered	T148,T149
BootDone->Error	206	Covered	T15,T16,T47
BootDone->Idle	229	Covered	T7,T68,T110
BootGenAckWait->BootPulse	121	Covered	T7,T15,T27
BootGenAckWait->Error	206	Covered	T150
BootGenAckWait->Idle	229	Covered	T108,T80,T111
BootInsAckWait->BootCaptGenCnt	106	Covered	T7,T15,T27
BootInsAckWait->Error	206	Covered	T151,T152,T153
BootInsAckWait->Idle	229	Covered	T28,T100,T154
BootLoadGen->BootInsAckWait	102	Covered	T7,T15,T27
BootLoadGen->Error	206	Not Covered
BootLoadGen->Idle	229	Covered	T155,T156,T157
BootLoadIns->BootLoadGen	98	Covered	T7,T15,T27
BootLoadIns->Error	206	Covered	T64,T158,T159
BootLoadIns->Idle	229	Covered	T160,T161,T162
BootPulse->BootDone	126	Covered	T7,T15,T27
BootPulse->Error	206	Covered	T163,T164
BootPulse->Idle	229	Covered	T115,T118,T109
BootSendGenCmd->BootGenAckWait	116	Covered	T7,T15,T27
BootSendGenCmd->Error	206	Covered	T65,T44,T46
BootSendGenCmd->Idle	229	Covered	T73,T165,T166
Idle->AutoLoadIns	90	Covered	T10,T11,T12
Idle->BootLoadIns	88	Covered	T7,T15,T27
Idle->Error	206	Covered	T21,T22,T23
Idle->SWPortMode	93	Covered	T1,T3,T10
SWPortMode->Error	206	Covered	T167,T168,T45
SWPortMode->Idle	229	Covered	T4,T5,T50

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T28,T73,T100
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T27
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T11,T12
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T11,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T11,T12,T26
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T11,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T11,T12
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T9,T52

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	225776907	134808	0	0
FpvSecCmErrorStEscalate_A	225776907	135742	0	0
u_state_regs_A	225729110	225567431	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	134808	0	0
T6	2289	1045	0	0
T8	0	1021	0	0
T9	0	314	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	158	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	135742	0	0
T6	2289	1046	0	0
T8	0	1022	0	0
T9	0	315	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	159	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225729110	225567431	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	651	467	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0