Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T10
DataWait	75	Covered	T3,T7,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T115,T118,T113
AckPls->Error	99	Covered	T107,T85,T234
AckPls->Idle	85	Covered	T3,T7,T10
DataWait->AckPls	80	Covered	T3,T7,T10
DataWait->Disabled	107	Covered	T73,T154,T235
DataWait->Error	99	Covered	T15,T65,T8
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T3,T7,T10
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T65,T8

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T3,T7,T10
Idle	-	1	0	-	Covered	T3,T7,T10
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T3,T7,T10
DataWait	-	-	-	0	Covered	T3,T7,T10
AckPls	-	-	-	-	Covered	T3,T7,T10
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T64,T65,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1580438349	956906	0	0
FpvSecCmErrorStEscalate_A	1580438349	963444	0	0
u_state_regs_A	1580390552	1579258799	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580438349	956906	0	0
T6	16023	7665	0	0
T8	0	7147	0	0
T9	0	2548	0	0
T13	9191	0	0	0
T15	20181	7784	0	0
T16	0	2996	0	0
T28	6958	0	0	0
T31	25081	0	0	0
T52	0	1456	0	0
T63	14371	0	0	0
T64	7833	4640	0	0
T65	7854	4220	0	0
T66	0	4073	0	0
T67	43295	0	0	0
T77	6489	0	0	0
T167	0	2575	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580438349	963444	0	0
T6	16023	7672	0	0
T8	0	7154	0	0
T9	0	2555	0	0
T13	9191	0	0	0
T15	20181	7791	0	0
T16	0	3003	0	0
T28	6958	0	0	0
T31	25081	0	0	0
T52	0	1463	0	0
T63	14371	0	0	0
T64	7833	4647	0	0
T65	7854	4227	0	0
T66	0	4080	0	0
T67	43295	0	0	0
T77	6489	0	0	0
T167	0	2582	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1580390552	1579258799	0	0
T1	8372	7763	0	0
T2	8330	7763	0	0
T3	5607	5152	0	0
T4	4641	3353	0	0
T5	2833348	2833264	0	0
T7	6426	5817	0	0
T10	26558	26166	0	0
T11	16849	16268	0	0
T12	10871	10269	0	0
T20	12054	11431	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T18,T26
DataWait	75	Covered	T11,T18,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T11,T18,T26
DataWait->AckPls	80	Covered	T11,T18,T26
DataWait->Disabled	107	Covered	T126
DataWait->Error	99	Covered	T238,T58
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T11,T18,T26
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T65,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T11,T18,T26
Idle	-	1	0	-	Covered	T11,T18,T26
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T11,T18,T26
DataWait	-	-	-	0	Covered	T11,T18,T26
AckPls	-	-	-	-	Covered	T11,T18,T26
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	136958	0	0
FpvSecCmErrorStEscalate_A	225776907	137892	0	0
u_state_regs_A	225776907	225615228	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136958	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	137892	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T11,T30
DataWait	75	Covered	T1,T11,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T11,T30
DataWait->AckPls	80	Covered	T1,T11,T30
DataWait->Disabled	107	Covered	T80,T239,T149
DataWait->Error	99	Covered	T16,T163,T240
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T1,T11,T30
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T65,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T1,T11,T30
Idle	-	1	0	-	Covered	T1,T11,T30
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T1,T11,T30
DataWait	-	-	-	0	Covered	T1,T11,T30
AckPls	-	-	-	-	Covered	T1,T11,T30
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	136958	0	0
FpvSecCmErrorStEscalate_A	225776907	137892	0	0
u_state_regs_A	225776907	225615228	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136958	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	137892	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T10,T11
DataWait	75	Covered	T3,T10,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T107,T234,T241
AckPls->Idle	85	Covered	T3,T10,T11
DataWait->AckPls	80	Covered	T3,T10,T11
DataWait->Disabled	107	Covered	T154,T148,T242
DataWait->Error	99	Covered	T15,T9,T43
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T237,T21
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T3,T10,T11
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T8,T16,T52

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T3,T10,T11
Idle	-	1	0	-	Covered	T3,T10,T11
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T3,T10,T11
DataWait	-	-	-	0	Covered	T3,T10,T11
AckPls	-	-	-	-	Covered	T3,T10,T11
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T64,T65,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	135158	0	0
FpvSecCmErrorStEscalate_A	225776907	136092	0	0
u_state_regs_A	225729110	225567431	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	135158	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	620	0	0
T65	1122	560	0	0
T66	0	539	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	325	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136092	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	621	0	0
T65	1122	561	0	0
T66	0	540	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	326	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225729110	225567431	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	651	467	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T11,T27
DataWait	75	Covered	T7,T11,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T243
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T11,T27
DataWait->AckPls	80	Covered	T7,T11,T27
DataWait->Disabled	107	Covered	T235,T244,T245
DataWait->Error	99	Covered	T65,T141,T246
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T7,T11,T27
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T8,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T7,T11,T27
Idle	-	1	0	-	Covered	T7,T11,T27
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T7,T11,T27
DataWait	-	-	-	0	Covered	T7,T11,T27
AckPls	-	-	-	-	Covered	T7,T11,T27
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	136958	0	0
FpvSecCmErrorStEscalate_A	225776907	137892	0	0
u_state_regs_A	225776907	225615228	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136958	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	137892	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T17,T31
DataWait	75	Covered	T11,T17,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T118
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T11,T17,T31
DataWait->AckPls	80	Covered	T11,T17,T31
DataWait->Disabled	107	Covered	T247,T166,T248
DataWait->Error	99	Covered	T132,T249
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T11,T17,T31
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T65,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T11,T17,T31
Idle	-	1	0	-	Covered	T11,T17,T31
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T11,T17,T31
DataWait	-	-	-	0	Covered	T11,T17,T31
AckPls	-	-	-	-	Covered	T11,T17,T31
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	136958	0	0
FpvSecCmErrorStEscalate_A	225776907	137892	0	0
u_state_regs_A	225776907	225615228	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136958	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	137892	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T20,T27
DataWait	75	Covered	T11,T20,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T113
AckPls->Error	99	Covered	T250,T251
AckPls->Idle	85	Covered	T11,T20,T27
DataWait->AckPls	80	Covered	T11,T20,T27
DataWait->Disabled	107	Covered	T73,T142,T143
DataWait->Error	99	Covered	T8,T252,T253
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T11,T20,T27
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T65,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T11,T20,T27
Idle	-	1	0	-	Covered	T11,T20,T27
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T11,T20,T27
DataWait	-	-	-	0	Covered	T11,T20,T27
AckPls	-	-	-	-	Covered	T11,T20,T27
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	136958	0	0
FpvSecCmErrorStEscalate_A	225776907	137892	0	0
u_state_regs_A	225776907	225615228	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136958	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	137892	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T4,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T29,T30
DataWait	75	Covered	T28,T29,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T7
Error	99	Covered	T6,T15,T64
Idle	68	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T115
AckPls->Error	99	Covered	T85,T254
AckPls->Idle	85	Covered	T28,T29,T30
DataWait->AckPls	80	Covered	T28,T29,T30
DataWait->Disabled	107	Covered	T165,T255,T256
DataWait->Error	99	Covered	T46,T150,T257
Disabled->EndPointClear	63	Covered	T1,T3,T7
Disabled->Error	99	Covered	T21,T22,T23
EndPointClear->Disabled	107	Covered	T93,T236,T160
EndPointClear->Error	99	Covered	T6,T64,T237
EndPointClear->Idle	68	Covered	T1,T3,T7
Idle->DataWait	75	Covered	T28,T29,T30
Idle->Disabled	107	Covered	T7,T4,T5
Idle->Error	99	Covered	T15,T65,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T7
Idle	-	1	1	-	Covered	T28,T29,T30
Idle	-	1	0	-	Covered	T28,T29,T30
Idle	-	0	-	-	Covered	T1,T3,T7
DataWait	-	-	-	1	Covered	T28,T29,T30
DataWait	-	-	-	0	Covered	T28,T29,T30
AckPls	-	-	-	-	Covered	T28,T29,T30
Error	-	-	-	-	Covered	T6,T15,T64
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T15,T64
0	1	Covered	T7,T4,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	225776907	136958	0	0
FpvSecCmErrorStEscalate_A	225776907	137892	0	0
u_state_regs_A	225776907	225615228	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	136958	0	0
T6	2289	1095	0	0
T8	0	1021	0	0
T9	0	364	0	0
T13	1313	0	0	0
T15	2883	1112	0	0
T16	0	428	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	208	0	0
T63	2053	0	0	0
T64	1119	670	0	0
T65	1122	610	0	0
T66	0	589	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	375	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	137892	0	0
T6	2289	1096	0	0
T8	0	1022	0	0
T9	0	365	0	0
T13	1313	0	0	0
T15	2883	1113	0	0
T16	0	429	0	0
T28	994	0	0	0
T31	3583	0	0	0
T52	0	209	0	0
T63	2053	0	0	0
T64	1119	671	0	0
T65	1122	611	0	0
T66	0	590	0	0
T67	6185	0	0	0
T77	927	0	0	0
T167	0	376	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0