SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
edn_alert_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 5 | 0 | 5 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_recov_alert_cg | 5 | 0 | 5 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 5 | 0 | 5 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[edn_enable_field_alert] | 13 | 1 | T16 | 1 | T270 | 1 | T271 | 1 | ||||
auto[boot_req_mode_field_alert] | 5 | 1 | T272 | 1 | T273 | 1 | T274 | 1 | ||||
auto[auto_req_mode_field_alert] | 12 | 1 | T18 | 1 | T92 | 1 | T275 | 1 | ||||
auto[cmd_fifo_rst_field_alert] | 20 | 1 | T17 | 1 | T276 | 1 | T112 | 1 | ||||
auto[edn_bus_cmp_alert] | 50 | 1 | T16 | 1 | T17 | 1 | T18 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |