Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 0 49 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 0 12 100.00 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3834 1 T1 1 T2 1 T3 1
auto[RES] 843 1 T1 2 T6 3 T9 1
auto[GEN] 3668 1 T1 2 T2 2 T3 1
auto[UPD] 489 1 T2 1 T21 1 T36 12
auto[UNI] 3424 1 T1 1 T2 1 T20 1


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4184 1 T1 5 T2 2 T22 3
no_cmd_data 8074 1 T1 1 T2 3 T3 2


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 11114 1 T1 4 T2 3 T3 2
reseed_cmd 318 1 T1 1 T6 3 T9 1
generate_cmd 318 1 T1 1 T6 3 T9 1
boot_gen_cmd 254 1 T2 1 T21 1 T31 1
boot_ins_cmd 254 1 T2 1 T21 1 T31 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 3883 1 T1 3 T2 2 T22 1
false 8375 1 T1 3 T2 3 T3 2


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1147 1 T1 5 T2 3 T21 1
one 1926 1 T3 1 T4 1 T20 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 10437 1 T1 2 T2 1 T3 2
boot_mode 746 1 T2 4 T21 4 T31 5
auto_mode 1075 1 T1 4 T6 7 T9 4


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 120 1 T1 1 T23 1 T9 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 57 1 T2 1 T30 1 T40 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 110 1 T1 1 T6 1 T9 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 43 1 T22 1 T359 1 T62 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 24 1 T77 1 T78 1 T322 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 111 1 T61 1 T42 1 T114 2
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 27 1 T41 1 T87 1 T360 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 11 1 T295 1 T361 1 T362 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 75 1 T2 1 T31 1 T30 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 29 1 T6 1 T8 1 T120 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1431 1 T3 1 T4 1 T20 1
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 8 1 T21 1 T31 1 T363 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 68 1 T6 1 T7 1 T8 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 741 1 T36 13 T33 1 T58 7
auto[INS] some_cmd_data true boot_mode sw_cmd_req 16 1 T31 1 T295 1 T364 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 74 1 T9 1 T41 2 T93 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 754 1 T22 2 T23 1 T36 13
auto[INS] some_cmd_data false boot_mode sw_cmd_req 18 1 T30 1 T78 1 T322 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 69 1 T1 1 T9 1 T42 2
auto[INS] no_cmd_data true sw_mode sw_cmd_req 173 1 T36 3 T58 1 T107 1
auto[INS] no_cmd_data true boot_mode sw_cmd_req 2 1 T304 1 T365 1 - -
auto[INS] no_cmd_data true auto_mode sw_cmd_req 64 1 T16 1 T17 1 T18 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1593 1 T3 1 T4 1 T20 1
auto[INS] no_cmd_data false boot_mode sw_cmd_req 2 1 T366 1 T332 1 - -
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 152 1 T2 1 T21 1 T79 2
auto[INS] no_cmd_data false auto_mode sw_cmd_req 74 1 T6 1 T7 1 T8 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 182 1 T58 4 T106 1 T323 1
auto[RES] some_cmd_data true boot_mode sw_cmd_req 11 1 T39 1 T40 1 T90 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 100 1 T1 1 T6 2 T7 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 199 1 T36 3 T58 2 T110 1
auto[RES] some_cmd_data false boot_mode sw_cmd_req 16 1 T77 1 T367 1 T368 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 118 1 T7 1 T8 1 T61 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 47 1 T36 2 T63 1 T106 1
auto[RES] no_cmd_data true boot_mode sw_cmd_req 3 1 T369 1 T370 1 T371 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 27 1 T9 1 T8 1 T114 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 46 1 T36 1 T107 1 T106 1
auto[RES] no_cmd_data false boot_mode sw_cmd_req 1 1 T372 1 - - - -
auto[RES] no_cmd_data false auto_mode reseed_cmd 73 1 T6 1 T7 1 T8 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 363 1 T36 10 T75 1 T58 2
auto[UPD] some_cmd_data boot_mode sw_cmd_req 23 1 T2 1 T325 1 T373 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 87 1 T36 2 T58 2 T38 1
auto[UPD] no_cmd_data boot_mode sw_cmd_req 8 1 T21 1 T374 1 T44 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3373 1 T1 1 T2 1 T20 1
auto[UNI] boot_mode sw_cmd_req 38 1 T31 1 T30 1 T78 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 281 1 T1 1 T6 1 T9 2
auto[RES] auto_mode sw_cmd_req 20 1 T1 1 T61 1 T87 1
auto[GEN] auto_mode sw_cmd_req 117 1 T16 2 T17 2 T18 2
auto[UPD] auto_mode sw_cmd_req 8 1 T11 1 T375 1 T376 1
auto[UNI] auto_mode sw_cmd_req 13 1 T12 1 T298 1 T306 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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