Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	614722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5142931

1

T1

65

T2

11

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1518121	1			T1	63		T2	33		T3	15
values[0x0]	1966738	1			T1	40		T2	9		T3	6
values[0x1]	2272794	1			T1	25		T2	4		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	304968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5452685

1

T1

85

T2

25

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21676	1			T22	3		T46	4		T136	1
valid_sources[0x01]	22109	1			T22	1		T23	1		T45	4
valid_sources[0x02]	21454	1			T1	1		T27	2		T46	3
valid_sources[0x03]	22174	1			T2	1		T27	2		T45	1
valid_sources[0x04]	23895	1			T5	1		T142	14		T152	1
valid_sources[0x05]	22248	1			T2	2		T27	13		T46	3
valid_sources[0x06]	22041	1			T1	2		T3	3		T46	1
valid_sources[0x07]	21347	1			T45	2		T46	2		T138	2
valid_sources[0x08]	21116	1			T2	1		T27	3		T138	1
valid_sources[0x09]	22308	1			T1	3		T27	3		T45	1
valid_sources[0x0a]	21947	1			T45	3		T46	2		T232	1
valid_sources[0x0b]	22500	1			T27	1		T46	2		T232	1
valid_sources[0x0c]	22972	1			T1	1		T46	3		T136	1
valid_sources[0x0d]	23066	1			T46	2		T136	1		T232	2
valid_sources[0x0e]	22627	1			T5	3		T45	1		T46	3
valid_sources[0x0f]	23141	1			T1	1		T46	4		T139	1
valid_sources[0x10]	22612	1			T45	2		T46	6		T136	1
valid_sources[0x11]	22010	1			T27	1		T45	7		T46	3
valid_sources[0x12]	21916	1			T4	3		T22	1		T27	2
valid_sources[0x13]	20628	1			T23	1		T5	1		T46	3
valid_sources[0x14]	21659	1			T27	1		T46	1		T136	1
valid_sources[0x15]	22843	1			T22	1		T27	1		T45	2
valid_sources[0x16]	22619	1			T27	3		T45	1		T232	1
valid_sources[0x17]	22202	1			T23	1		T27	1		T46	3
valid_sources[0x18]	23860	1			T27	3		T45	1		T46	1
valid_sources[0x19]	22493	1			T1	2		T4	1		T23	1
valid_sources[0x1a]	21667	1			T27	1		T48	40		T46	3
valid_sources[0x1b]	25225	1			T1	3		T27	2		T45	3
valid_sources[0x1c]	21647	1			T46	2		T232	3		T152	1
valid_sources[0x1d]	22252	1			T46	2		T136	1		T232	1
valid_sources[0x1e]	23192	1			T1	1		T45	1		T46	4
valid_sources[0x1f]	22772	1			T1	7		T21	10		T27	3
valid_sources[0x20]	22788	1			T1	7		T27	1		T232	1
valid_sources[0x21]	23247	1			T1	1		T21	2		T46	2
valid_sources[0x22]	22735	1			T1	2		T23	1		T5	2
valid_sources[0x23]	22315	1			T1	2		T22	1		T23	1
valid_sources[0x24]	23263	1			T1	2		T2	1		T22	1
valid_sources[0x25]	22764	1			T22	1		T46	5		T232	2
valid_sources[0x26]	24143	1			T5	1		T136	2		T232	1
valid_sources[0x27]	23966	1			T1	1		T3	15		T22	1
valid_sources[0x28]	21132	1			T2	1		T23	1		T5	1
valid_sources[0x29]	21828	1			T27	1		T46	1		T232	1
valid_sources[0x2a]	21729	1			T1	1		T27	2		T29	7
valid_sources[0x2b]	21291	1			T4	1		T23	1		T27	4
valid_sources[0x2c]	22549	1			T22	1		T27	2		T45	1
valid_sources[0x2d]	22788	1			T27	2		T45	2		T46	1
valid_sources[0x2e]	22605	1			T1	2		T22	1		T46	5
valid_sources[0x2f]	23013	1			T1	2		T46	1		T232	4
valid_sources[0x30]	22347	1			T22	1		T27	2		T46	4
valid_sources[0x31]	23335	1			T27	2		T46	2		T138	2
valid_sources[0x32]	22056	1			T23	1		T46	5		T136	1
valid_sources[0x33]	22008	1			T45	4		T46	2		T138	1
valid_sources[0x34]	22386	1			T46	2		T137	1		T139	4
valid_sources[0x35]	24007	1			T1	2		T27	3		T46	1
valid_sources[0x36]	21243	1			T5	1		T45	1		T46	2
valid_sources[0x37]	22661	1			T1	1		T27	1		T136	1
valid_sources[0x38]	22181	1			T136	4		T232	2		T139	5
valid_sources[0x39]	21487	1			T1	1		T45	3		T47	1
valid_sources[0x3a]	20850	1			T45	1		T46	5		T232	2
valid_sources[0x3b]	22048	1			T22	1		T27	1		T46	2
valid_sources[0x3c]	22355	1			T27	4		T45	2		T46	3
valid_sources[0x3d]	21406	1			T20	1		T23	1		T27	1
valid_sources[0x3e]	22994	1			T45	2		T46	3		T232	1
valid_sources[0x3f]	22726	1			T46	4		T152	3		T143	4
valid_sources[0x40]	21285	1			T136	3		T138	2		T142	6
valid_sources[0x41]	24059	1			T2	1		T4	1		T45	1
valid_sources[0x42]	23125	1			T4	4		T23	1		T27	3
valid_sources[0x43]	22095	1			T23	1		T45	4		T46	1
valid_sources[0x44]	21780	1			T1	1		T22	1		T27	2
valid_sources[0x45]	23331	1			T19	3		T46	1		T232	1
valid_sources[0x46]	22576	1			T27	1		T45	3		T46	4
valid_sources[0x47]	24142	1			T27	2		T45	1		T46	1
valid_sources[0x48]	21851	1			T23	1		T45	1		T46	3
valid_sources[0x49]	23346	1			T19	16		T45	4		T46	1
valid_sources[0x4a]	22780	1			T1	2		T22	1		T27	1
valid_sources[0x4b]	21776	1			T1	1		T23	2		T46	1
valid_sources[0x4c]	21820	1			T4	1		T27	3		T45	1
valid_sources[0x4d]	21135	1			T1	1		T45	6		T46	2
valid_sources[0x4e]	22431	1			T23	2		T27	2		T46	1
valid_sources[0x4f]	23292	1			T2	2		T45	2		T46	1
valid_sources[0x50]	22384	1			T22	1		T27	2		T136	1
valid_sources[0x51]	22668	1			T2	1		T27	6		T46	1
valid_sources[0x52]	23478	1			T1	1		T22	1		T23	1
valid_sources[0x53]	21585	1			T2	1		T20	1		T27	1
valid_sources[0x54]	22384	1			T22	1		T136	1		T232	2
valid_sources[0x55]	22550	1			T1	1		T2	1		T23	2
valid_sources[0x56]	22184	1			T2	1		T45	1		T233	3
valid_sources[0x57]	23505	1			T1	1		T27	2		T45	1
valid_sources[0x58]	23245	1			T46	5		T232	2		T152	2
valid_sources[0x59]	23146	1			T5	2		T45	6		T46	3
valid_sources[0x5a]	21683	1			T22	1		T27	4		T46	4
valid_sources[0x5b]	22111	1			T23	1		T27	2		T45	1
valid_sources[0x5c]	22705	1			T45	6		T46	1		T233	6
valid_sources[0x5d]	23051	1			T5	1		T27	3		T45	3
valid_sources[0x5e]	23702	1			T1	2		T46	2		T136	1
valid_sources[0x5f]	22501	1			T1	1		T22	1		T45	1
valid_sources[0x60]	22787	1			T46	5		T232	3		T152	1
valid_sources[0x61]	22258	1			T23	1		T27	1		T45	1
valid_sources[0x62]	21268	1			T2	1		T46	2		T232	1
valid_sources[0x63]	21420	1			T2	1		T21	3		T22	1
valid_sources[0x64]	22967	1			T22	1		T27	2		T46	2
valid_sources[0x65]	22711	1			T1	2		T27	2		T45	1
valid_sources[0x66]	22397	1			T22	1		T27	1		T46	6
valid_sources[0x67]	22846	1			T2	1		T27	2		T46	3
valid_sources[0x68]	22255	1			T27	2		T46	2		T136	1
valid_sources[0x69]	21951	1			T5	1		T27	1		T46	2
valid_sources[0x6a]	23583	1			T1	1		T27	3		T45	4
valid_sources[0x6b]	21812	1			T27	3		T136	1		T232	1
valid_sources[0x6c]	23018	1			T1	1		T23	1		T27	1
valid_sources[0x6d]	22753	1			T1	1		T45	1		T29	75
valid_sources[0x6e]	23496	1			T22	1		T27	4		T45	3
valid_sources[0x6f]	22262	1			T2	1		T23	1		T27	4
valid_sources[0x70]	23461	1			T23	2		T136	1		T138	1
valid_sources[0x71]	22707	1			T4	1		T45	3		T46	4
valid_sources[0x72]	21722	1			T27	1		T46	2		T232	2
valid_sources[0x73]	21898	1			T27	1		T45	4		T46	2
valid_sources[0x74]	23396	1			T27	1		T45	3		T46	5
valid_sources[0x75]	22927	1			T27	4		T46	2		T138	1
valid_sources[0x76]	24282	1			T22	1		T23	3		T46	1
valid_sources[0x77]	22444	1			T21	2		T22	1		T45	4
valid_sources[0x78]	21850	1			T27	3		T45	3		T46	2
valid_sources[0x79]	22279	1			T1	1		T27	3		T45	1
valid_sources[0x7a]	22236	1			T1	3		T23	1		T46	3
valid_sources[0x7b]	22944	1			T1	1		T27	1		T45	8
valid_sources[0x7c]	20796	1			T2	1		T27	1		T45	1
valid_sources[0x7d]	22192	1			T1	4		T23	1		T45	2
valid_sources[0x7e]	23192	1			T27	3		T45	1		T46	3
valid_sources[0x7f]	22033	1			T27	2		T45	1		T46	4
valid_sources[0x80]	21275	1			T2	2		T23	1		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1291304

1

T1

2

T2

1

T3

3

values[0x0]

all_enables

biggest_size

1926861

1

T1

39

T2

8

T3

4

values[0x1]

all_enables

biggest_size

1924766

1

T1

24

T2

2

T3

2