Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2371	1		T1	1	T2	2	T22	3
non_zero_bins[1]	1750	1		T1	4	T9	3	T36	23
zero	7723	1		T2	3	T3	2	T4	2

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	465	1		T2	1	T21	1	T36	12
uni	3284	1		T2	1	T20	1	T21	1
gen	3585	1		T1	2	T2	2	T3	1
res	756	1		T1	2	T9	2	T36	6
ins	3754	1		T1	1	T2	1	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8050

mubi_true

3794

T22

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5930

pass

5914

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	52	1		T36	1	T106	1	T111	1
upd	non_zero_bins[0]	fail	mubi_true	58	1		T36	3	T106	1	T111	2
upd	non_zero_bins[0]	pass	mubi_false	68	1		T113	1	T317	1	T318	3
upd	non_zero_bins[0]	pass	mubi_true	40	1		T2	1	T36	1	T107	1
upd	non_zero_bins[1]	fail	mubi_false	43	1		T36	1	T106	1	T113	1
upd	non_zero_bins[1]	fail	mubi_true	36	1		T36	2	T58	1	T106	1
upd	non_zero_bins[1]	pass	mubi_false	42	1		T36	1	T75	1	T58	1
upd	non_zero_bins[1]	pass	mubi_true	35	1		T36	1	T111	1	T319	1
upd	zero	fail	mubi_false	27	1		T36	1	T58	2	T38	1
upd	zero	fail	mubi_true	23	1		T36	1	T62	1	T106	1
upd	zero	pass	mubi_false	18	1		T21	1	T108	1	T320	1
upd	zero	pass	mubi_true	23	1		T317	1	T319	1	T321	1
uni	zero	fail	mubi_false	1167	1		T2	1	T22	1	T23	1
uni	zero	fail	mubi_true	487	1		T31	1	T36	6	T76	1
uni	zero	pass	mubi_false	1172	1		T20	1	T21	1	T22	1
uni	zero	pass	mubi_true	458	1		T36	9	T33	1	T58	5
gen	non_zero_bins[0]	fail	mubi_false	211	1		T36	4	T58	1	T110	1
gen	non_zero_bins[0]	fail	mubi_true	230	1		T22	1	T36	1	T75	1
gen	non_zero_bins[0]	pass	mubi_false	249	1		T2	1	T36	3	T33	1
gen	non_zero_bins[0]	pass	mubi_true	198	1		T23	1	T36	1	T58	2
gen	non_zero_bins[1]	fail	mubi_false	148	1		T1	1	T58	1	T107	1
gen	non_zero_bins[1]	fail	mubi_true	163	1		T36	2	T58	1	T106	3
gen	non_zero_bins[1]	pass	mubi_false	160	1		T1	1	T9	3	T36	3
gen	non_zero_bins[1]	pass	mubi_true	155	1		T322	1	T110	1	T38	1
gen	zero	fail	mubi_false	831	1		T21	2	T5	1	T80	1
gen	zero	fail	mubi_true	184	1		T79	1	T16	1	T36	3
gen	zero	pass	mubi_false	880	1		T3	1	T4	1	T20	1
gen	zero	pass	mubi_true	176	1		T2	1	T31	1	T16	1
res	non_zero_bins[0]	fail	mubi_false	91	1		T58	1	T61	2	T63	1
res	non_zero_bins[0]	fail	mubi_true	76	1		T10	1	T323	1	T111	1
res	non_zero_bins[0]	pass	mubi_false	80	1		T58	1	T93	3	T108	3
res	non_zero_bins[0]	pass	mubi_true	94	1		T58	1	T39	1	T10	1
res	non_zero_bins[1]	fail	mubi_false	71	1		T36	2	T77	1	T110	1
res	non_zero_bins[1]	fail	mubi_true	64	1		T1	2	T58	3	T106	1
res	non_zero_bins[1]	pass	mubi_false	70	1		T36	1	T42	2	T89	1
res	non_zero_bins[1]	pass	mubi_true	59	1		T87	2	T117	2	T319	1
res	zero	fail	mubi_false	30	1		T114	1	T106	1	T324	1
res	zero	fail	mubi_true	36	1		T9	1	T36	1	T63	1
res	zero	pass	mubi_false	37	1		T36	1	T107	1	T319	1
res	zero	pass	mubi_true	48	1		T9	1	T36	1	T106	1
ins	non_zero_bins[0]	fail	mubi_false	239	1		T36	7	T33	1	T110	1
ins	non_zero_bins[0]	fail	mubi_true	239	1		T31	1	T9	1	T36	5
ins	non_zero_bins[0]	pass	mubi_false	210	1		T1	1	T22	2	T23	1
ins	non_zero_bins[0]	pass	mubi_true	236	1		T36	3	T33	1	T58	2
ins	non_zero_bins[1]	fail	mubi_false	181	1		T36	2	T58	2	T78	1
ins	non_zero_bins[1]	fail	mubi_true	153	1		T36	2	T110	2	T63	1
ins	non_zero_bins[1]	pass	mubi_false	191	1		T36	3	T107	1	T322	1
ins	non_zero_bins[1]	pass	mubi_true	179	1		T36	3	T58	2	T107	1
ins	zero	fail	mubi_false	919	1		T3	1	T4	1	T21	1
ins	zero	fail	mubi_true	171	1		T31	1	T36	1	T34	1
ins	zero	pass	mubi_false	863	1		T2	1	T20	1	T79	1
ins	zero	pass	mubi_true	173	1		T79	1	T16	1	T36	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded