Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.31	100.00	85.94			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T2,T21,T31
1	1	0	1	Covered	T2,T21,T31
1	1	1	0	Covered	T1,T3,T4
1	1	1	1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T116,T88,T85
1	1	Covered	T2,T21,T31

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T42,T93,T89
1	1	Covered	T1,T6,T9

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T116,T60,T42

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	54	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T1,T9,T7
AutoCaptGenCnt	162	Covered	T1,T9,T7
AutoCaptReseedCnt	160	Covered	T1,T9,T61
AutoDispatch	142	Covered	T1,T9,T7
AutoFirstAckWait	135	Covered	T1,T9,T7
AutoLoadIns	90	Covered	T1,T6,T9
AutoSendGenCmd	170	Covered	T1,T9,T7
AutoSendReseedCmd	184	Covered	T1,T9,T61
BootCaptGenCnt	106	Covered	T2,T21,T31
BootDone	126	Covered	T2,T21,T31
BootGenAckWait	116	Covered	T2,T21,T31
BootInsAckWait	102	Covered	T2,T21,T31
BootLoadGen	98	Covered	T2,T21,T31
BootLoadIns	88	Covered	T2,T21,T31
BootPulse	121	Covered	T2,T21,T31
BootSendGenCmd	111	Covered	T2,T21,T31
Error	206	Covered	T3,T4,T5
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T1,T9,T61
AutoAckWait->Error	206	Covered	T7,T172,T173
AutoAckWait->Idle	229	Covered	T42,T93,T89
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T1,T9,T7
AutoCaptGenCnt->Error	206	Covered	T67,T174,T175
AutoCaptGenCnt->Idle	229	Covered	T176,T177,T178
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T1,T9,T61
AutoCaptReseedCnt->Error	206	Covered	T179
AutoCaptReseedCnt->Idle	229	Covered	T180,T128,T181
AutoDispatch->AutoCaptGenCnt	162	Covered	T1,T9,T7
AutoDispatch->AutoCaptReseedCnt	160	Covered	T1,T9,T61
AutoDispatch->Error	206	Covered	T182,T96,T183
AutoDispatch->Idle	157	Covered	T1,T9,T61
AutoFirstAckWait->AutoDispatch	142	Covered	T1,T9,T7
AutoFirstAckWait->Error	206	Covered	T15,T53,T184
AutoFirstAckWait->Idle	229	Covered	T185,T186,T187
AutoLoadIns->AutoFirstAckWait	135	Covered	T1,T9,T7
AutoLoadIns->Error	206	Covered	T188,T189,T190
AutoLoadIns->Idle	229	Covered	T191,T192,T193
AutoSendGenCmd->AutoAckWait	177	Covered	T1,T9,T7
AutoSendGenCmd->Error	206	Covered	T8,T120,T194
AutoSendGenCmd->Idle	229	Covered	T42,T195,T196
AutoSendReseedCmd->AutoAckWait	191	Covered	T1,T9,T61
AutoSendReseedCmd->Error	206	Covered	T55,T197,T198
AutoSendReseedCmd->Idle	229	Covered	T199,T200,T201
BootCaptGenCnt->BootSendGenCmd	111	Covered	T2,T21,T31
BootCaptGenCnt->Error	206	Covered	T34
BootCaptGenCnt->Idle	229	Covered	T85,T202,T203
BootDone->Error	206	Covered	T50,T204,T205
BootDone->Idle	229	Covered	T122,T133,T130
BootGenAckWait->BootPulse	121	Covered	T2,T21,T31
BootGenAckWait->Error	206	Covered	T206,T207
BootGenAckWait->Idle	229	Covered	T121,T131,T127
BootInsAckWait->BootCaptGenCnt	106	Covered	T2,T21,T31
BootInsAckWait->Error	206	Covered	T208,T209,T210
BootInsAckWait->Idle	229	Covered	T116,T88,T211
BootLoadGen->BootInsAckWait	102	Covered	T2,T21,T31
BootLoadGen->Error	206	Covered	T212,T213
BootLoadGen->Idle	229	Covered	T214,T215,T216
BootLoadIns->BootLoadGen	98	Covered	T2,T21,T31
BootLoadIns->Error	206	Covered	T14,T217,T218
BootLoadIns->Idle	229	Covered	T219,T220,T221
BootPulse->BootDone	126	Covered	T2,T21,T31
BootPulse->Error	206	Covered	T56,T222
BootPulse->Idle	229	Covered	T123,T223,T224
BootSendGenCmd->BootGenAckWait	116	Covered	T2,T21,T31
BootSendGenCmd->Error	206	Covered	T225,T226
BootSendGenCmd->Idle	229	Covered	T227,T228
Idle->AutoLoadIns	90	Covered	T1,T6,T9
Idle->BootLoadIns	88	Covered	T2,T21,T31
Idle->Error	206	Covered	T24,T25,T26
Idle->SWPortMode	93	Covered	T1,T3,T4
SWPortMode->Error	206	Covered	T13,T229,T230
SWPortMode->Idle	229	Covered	T36,T58,T107

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T116,T88,T85
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T31
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T9,T7
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T6,T9
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T9,T7
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T9,T7
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T9,T61
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T9,T7
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T9,T61
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T9,T61
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T9,T7
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T7
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T9,T7
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T61
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T61
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T61,T42
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T5
0	1	Covered	T116,T60,T42
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	194453532	131892	0	0
FpvSecCmErrorStEscalate_A	194453532	132655	0	0
u_state_regs_A	194414587	194266854	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	131892	0	0
T3	1730	905	0	0
T4	921	353	0	0
T5	1848	1038	0	0
T6	1923	1034	0	0
T7	0	610	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	360	0	0
T79	1582	260	0	0
T80	0	1053	0	0
T81	0	1050	0	0
T82	0	1088	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	132655	0	0
T3	1730	906	0	0
T4	921	354	0	0
T5	1848	1039	0	0
T6	1923	1035	0	0
T7	0	611	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	361	0	0
T79	1582	261	0	0
T80	0	1054	0	0
T81	0	1051	0	0
T82	0	1089	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194414587	194266854	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1572	1441	0	0
T4	759	619	0	0
T5	1736	1595	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0