Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	136	1			T3	1		T38	1		T37	1
auto_req_mode	129	1			T2	1		T10	1		T11	1
sw_mode	2561	1			T1	1		T32	1		T39	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

277

1

T1

1

T2

1

T3

1

single

109

1

T40

1

T37

1

T69

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1025	1			T1	1		T3	1		T32	1
auto[2]	74	1			T196	36		T230	1		T200	1
auto[3]	243	1			T5	69		T199	1		T231	1
auto[4]	162	1			T232	1		T233	1		T234	1
auto[5]	146	1			T198	45		T235	1		T236	3
auto[6]	52	1			T12	1		T76	1		T237	1
auto[7]	1124	1			T2	1		T10	1		T38	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	80	1			T3	1		T37	1		T79	1
auto[1]	auto_req_mode	80	1			T113	1		T86	1		T116	1
auto[1]	sw_mode	865	1			T1	1		T32	1		T39	1
auto[2]	boot_req_mode	6	1			T200	1		T238	1		T239	1
auto[2]	auto_req_mode	3	1			T240	1		T241	1		T242	1
auto[2]	sw_mode	65	1			T196	36		T230	1		T243	1
auto[3]	boot_req_mode	4	1			T199	1		T244	1		T245	1
auto[3]	auto_req_mode	1	1			T246	1		-	-		-	-
auto[3]	sw_mode	238	1			T5	69		T231	1		T247	59
auto[4]	boot_req_mode	6	1			T234	1		T248	1		T249	1
auto[4]	auto_req_mode	3	1			T250	1		T251	1		T252	1
auto[4]	sw_mode	153	1			T232	1		T233	1		T253	43
auto[5]	boot_req_mode	2	1			T254	1		T255	1		-	-
auto[5]	auto_req_mode	1	1			T235	1		-	-		-	-
auto[5]	sw_mode	143	1			T198	45		T236	3		T256	1
auto[6]	boot_req_mode	2	1			T257	1		T258	1		-	-
auto[6]	auto_req_mode	5	1			T12	1		T237	1		T259	1
auto[6]	sw_mode	45	1			T76	1		T260	42		T261	1
auto[7]	boot_req_mode	36	1			T38	1		T33	1		T57	1
auto[7]	auto_req_mode	36	1			T2	1		T10	1		T11	1
auto[7]	sw_mode	1052	1			T45	1		T68	10		T54	68