Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 49 0 49 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 13 0 13 100.00 100 1 1 0
cr_instantiate_intended 13 0 13 100.00 100 1 1 0
cr_reseed_intended 12 0 12 100.00 100 1 1 0
cr_update_intended 4 0 4 100.00 100 1 1 0
cr_uninstantiate_intended 2 0 2 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3586 1 T1 1 T2 1 T3 1
auto[RES] 758 1 T1 1 T2 1 T32 1
auto[GEN] 3473 1 T1 1 T2 3 T3 1
auto[UPD] 484 1 T10 1 T5 16 T6 12
auto[UNI] 3203 1 T1 1 T2 1 T32 1


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 3897 1 T1 2 T2 3 T32 3
no_cmd_data 7607 1 T1 2 T2 3 T3 2


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 10401 1 T1 4 T2 4 T32 4
reseed_cmd 302 1 T2 1 T10 1 T11 1
generate_cmd 301 1 T2 1 T10 1 T11 1
boot_gen_cmd 250 1 T3 1 T38 1 T37 1
boot_ins_cmd 250 1 T3 1 T38 1 T37 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 3637 1 T1 1 T2 2 T32 1
false 7867 1 T1 3 T2 4 T3 2


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1126 1 T1 2 T2 5 T3 1
one 1840 1 T3 1 T32 2 T39 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 9752 1 T1 4 T2 2 T32 4
boot_mode 716 1 T3 2 T38 4 T37 2
auto_mode 1036 1 T2 4 T10 4 T16 3


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 127 1 T1 1 T2 1 T10 1
auto[GEN] some_cmd_data multiple boot_mode sw_cmd_req 63 1 T38 1 T33 1 T57 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 116 1 T2 1 T10 1 T41 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 41 1 T32 1 T34 1 T262 1
auto[GEN] some_cmd_data one boot_mode sw_cmd_req 20 1 T263 1 T264 1 T265 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 103 1 T11 1 T7 2 T12 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 29 1 T45 1 T113 1 T266 1
auto[GEN] no_cmd_data multiple boot_mode sw_cmd_req 8 1 T43 1 T267 1 T268 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 66 1 T38 1 T33 1 T57 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 19 1 T117 1 T269 1 T270 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1373 1 T39 1 T4 1 T5 29
auto[GEN] no_cmd_data one boot_mode sw_cmd_req 3 1 T271 1 T272 1 T273 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 63 1 T7 1 T8 1 T9 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 13 0 13 100.00
Automatically Generated Cross Bins 13 0 13 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 671 1 T32 1 T5 27 T45 1
auto[INS] some_cmd_data true boot_mode sw_cmd_req 12 1 T263 1 T274 1 T265 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 63 1 T11 1 T113 1 T13 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 686 1 T5 18 T45 1 T6 12
auto[INS] some_cmd_data false boot_mode sw_cmd_req 9 1 T85 1 T207 1 T200 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 70 1 T2 1 T10 1 T41 2
auto[INS] no_cmd_data true sw_mode sw_cmd_req 155 1 T40 1 T5 3 T6 2
auto[INS] no_cmd_data true boot_mode sw_cmd_req 2 1 T275 1 T276 1 - -
auto[INS] no_cmd_data true auto_mode sw_cmd_req 71 1 T16 1 T17 1 T86 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1532 1 T1 1 T39 1 T4 1
auto[INS] no_cmd_data false boot_mode sw_cmd_req 5 1 T62 1 T249 1 T277 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 142 1 T3 1 T57 1 T118 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 60 1 T7 1 T12 1 T8 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 165 1 T1 1 T5 3 T6 4
auto[RES] some_cmd_data true boot_mode sw_cmd_req 18 1 T38 1 T199 1 T234 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 102 1 T10 1 T7 1 T113 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 161 1 T32 1 T40 1 T5 5
auto[RES] some_cmd_data false boot_mode sw_cmd_req 13 1 T278 1 T201 1 T271 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 98 1 T41 1 T8 1 T86 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 36 1 T54 2 T69 1 T82 1
auto[RES] no_cmd_data true boot_mode sw_cmd_req 3 1 T264 1 T279 1 T280 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 28 1 T2 1 T12 1 T116 2
auto[RES] no_cmd_data false sw_mode sw_cmd_req 40 1 T5 2 T6 2 T68 1
auto[RES] no_cmd_data false boot_mode sw_cmd_req 2 1 T272 1 T281 1 - -
auto[RES] no_cmd_data false auto_mode reseed_cmd 74 1 T11 1 T7 2 T8 2


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 359 1 T5 14 T6 11 T54 10
auto[UPD] some_cmd_data boot_mode sw_cmd_req 23 1 T33 1 T57 1 T36 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 80 1 T5 2 T6 1 T54 2
auto[UPD] no_cmd_data boot_mode sw_cmd_req 7 1 T282 1 T283 1 T284 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3158 1 T1 1 T2 1 T32 1
auto[UNI] boot_mode sw_cmd_req 28 1 T263 1 T85 1 T274 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 264 1 T2 1 T10 1 T16 1
auto[RES] auto_mode sw_cmd_req 18 1 T113 1 T13 1 T285 1
auto[GEN] auto_mode sw_cmd_req 119 1 T2 1 T16 2 T17 2
auto[UPD] auto_mode sw_cmd_req 15 1 T10 1 T12 1 T286 1
auto[UNI] auto_mode sw_cmd_req 17 1 T11 1 T287 1 T204 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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