Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	602053	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5196452

1

T19

7

T20

235

T21

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1518406	1			T19	11		T20	284		T21	11
values[0x0]	1986210	1			T19	4		T20	96		T21	6
values[0x1]	2293889	1			T19	7		T20	128		T21	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	294919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5503586

1

T19

10

T20

324

T21

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22192	1			T20	5		T23	3		T26	4
valid_sources[0x01]	24391	1			T20	1		T133	1		T146	1
valid_sources[0x02]	22304	1			T20	2		T22	1		T24	1
valid_sources[0x03]	23283	1			T20	2		T25	2		T26	4
valid_sources[0x04]	21344	1			T20	2		T180	13		T168	1
valid_sources[0x05]	22776	1			T20	4		T26	1		T131	30
valid_sources[0x06]	24048	1			T24	3		T26	1		T135	5
valid_sources[0x07]	23126	1			T20	1		T24	4		T26	9
valid_sources[0x08]	21376	1			T20	1		T26	1		T135	3
valid_sources[0x09]	21779	1			T20	2		T24	1		T28	1
valid_sources[0x0a]	22068	1			T20	2		T24	1		T26	9
valid_sources[0x0b]	22295	1			T20	1		T153	128		T168	2
valid_sources[0x0c]	21285	1			T26	12		T27	2		T133	4
valid_sources[0x0d]	23788	1			T26	9		T165	1		T133	3
valid_sources[0x0e]	22638	1			T20	1		T24	1		T129	3
valid_sources[0x0f]	23453	1			T20	4		T24	4		T26	1
valid_sources[0x10]	23225	1			T20	4		T24	1		T26	8
valid_sources[0x11]	21679	1			T20	1		T130	7		T144	2
valid_sources[0x12]	22712	1			T20	2		T24	1		T28	1
valid_sources[0x13]	22825	1			T26	2		T133	2		T144	1
valid_sources[0x14]	21847	1			T20	1		T22	1		T26	3
valid_sources[0x15]	22522	1			T22	2		T26	1		T180	1
valid_sources[0x16]	22312	1			T20	1		T180	3		T130	15
valid_sources[0x17]	22676	1			T20	4		T26	6		T129	1
valid_sources[0x18]	21815	1			T20	1		T26	5		T129	2
valid_sources[0x19]	20823	1			T20	2		T21	1		T24	1
valid_sources[0x1a]	21756	1			T24	4		T165	1		T133	3
valid_sources[0x1b]	21970	1			T20	1		T24	2		T26	1
valid_sources[0x1c]	23310	1			T20	1		T24	1		T180	3
valid_sources[0x1d]	21266	1			T20	1		T26	3		T27	4
valid_sources[0x1e]	22560	1			T20	3		T23	1		T168	1
valid_sources[0x1f]	21292	1			T26	2		T180	2		T130	15
valid_sources[0x20]	22242	1			T20	5		T21	2		T24	3
valid_sources[0x21]	23647	1			T20	5		T24	7		T26	9
valid_sources[0x22]	24285	1			T20	4		T22	1		T26	6
valid_sources[0x23]	21914	1			T20	3		T24	1		T26	2
valid_sources[0x24]	23278	1			T20	2		T26	6		T153	128
valid_sources[0x25]	23989	1			T20	2		T21	1		T23	1
valid_sources[0x26]	24957	1			T20	1		T26	1		T180	5
valid_sources[0x27]	21265	1			T20	1		T24	2		T26	1
valid_sources[0x28]	21430	1			T180	5		T161	2		T133	3
valid_sources[0x29]	22072	1			T20	1		T26	3		T27	1
valid_sources[0x2a]	23136	1			T26	2		T180	2		T169	2
valid_sources[0x2b]	23534	1			T20	7		T26	4		T129	3
valid_sources[0x2c]	23779	1			T24	1		T168	1		T129	1
valid_sources[0x2d]	22362	1			T20	5		T24	1		T26	3
valid_sources[0x2e]	19395	1			T20	3		T24	1		T26	2
valid_sources[0x2f]	23247	1			T26	1		T180	1		T166	68
valid_sources[0x30]	22233	1			T20	2		T22	1		T24	1
valid_sources[0x31]	23656	1			T20	2		T129	3		T161	1
valid_sources[0x32]	21793	1			T20	1		T22	2		T26	1
valid_sources[0x33]	22427	1			T20	3		T22	1		T26	1
valid_sources[0x34]	22522	1			T24	7		T26	1		T135	3
valid_sources[0x35]	23463	1			T20	2		T24	7		T26	4
valid_sources[0x36]	22301	1			T20	1		T27	1		T129	1
valid_sources[0x37]	23121	1			T20	4		T26	2		T135	2
valid_sources[0x38]	24329	1			T20	3		T25	1		T28	1
valid_sources[0x39]	22653	1			T20	3		T26	6		T135	3
valid_sources[0x3a]	25275	1			T20	2		T27	1		T28	1
valid_sources[0x3b]	21118	1			T20	5		T24	4		T135	4
valid_sources[0x3c]	22047	1			T20	2		T24	4		T26	8
valid_sources[0x3d]	23025	1			T20	3		T26	8		T27	1
valid_sources[0x3e]	20918	1			T20	1		T26	1		T27	1
valid_sources[0x3f]	24032	1			T135	2		T180	4		T129	1
valid_sources[0x40]	23319	1			T20	1		T22	1		T26	2
valid_sources[0x41]	22774	1			T20	1		T24	5		T135	2
valid_sources[0x42]	21151	1			T20	2		T180	2		T130	3
valid_sources[0x43]	22974	1			T20	2		T23	1		T24	4
valid_sources[0x44]	21197	1			T19	22		T20	1		T22	1
valid_sources[0x45]	21853	1			T20	2		T22	1		T23	1
valid_sources[0x46]	23687	1			T20	4		T26	2		T135	2
valid_sources[0x47]	22677	1			T20	2		T24	1		T26	1
valid_sources[0x48]	23616	1			T20	3		T26	1		T129	1
valid_sources[0x49]	23587	1			T20	1		T26	1		T27	1
valid_sources[0x4a]	24168	1			T20	5		T24	5		T26	2
valid_sources[0x4b]	21809	1			T20	1		T162	10		T165	1
valid_sources[0x4c]	23148	1			T20	3		T26	1		T180	4
valid_sources[0x4d]	23678	1			T20	3		T22	2		T25	2
valid_sources[0x4e]	25000	1			T20	2		T26	1		T182	3
valid_sources[0x4f]	20926	1			T24	4		T26	2		T180	1
valid_sources[0x50]	23059	1			T20	3		T23	1		T24	2
valid_sources[0x51]	23276	1			T20	1		T23	1		T24	1
valid_sources[0x52]	23153	1			T20	1		T23	2		T26	1
valid_sources[0x53]	22146	1			T20	2		T22	1		T26	5
valid_sources[0x54]	20719	1			T20	2		T22	1		T23	1
valid_sources[0x55]	21814	1			T20	2		T24	2		T26	2
valid_sources[0x56]	23552	1			T20	3		T21	1		T25	1
valid_sources[0x57]	23094	1			T20	1		T26	1		T129	3
valid_sources[0x58]	22077	1			T20	1		T21	1		T24	4
valid_sources[0x59]	23633	1			T20	1		T24	3		T163	1
valid_sources[0x5a]	24858	1			T28	2		T135	4		T180	7
valid_sources[0x5b]	23955	1			T20	1		T26	3		T131	24
valid_sources[0x5c]	22659	1			T20	3		T22	1		T24	3
valid_sources[0x5d]	20957	1			T24	3		T180	7		T168	1
valid_sources[0x5e]	22599	1			T26	8		T28	1		T133	2
valid_sources[0x5f]	24037	1			T20	1		T24	2		T26	2
valid_sources[0x60]	22588	1			T20	3		T25	1		T180	1
valid_sources[0x61]	21074	1			T20	2		T24	2		T26	5
valid_sources[0x62]	24180	1			T20	2		T26	7		T28	3
valid_sources[0x63]	22308	1			T20	3		T26	1		T168	3
valid_sources[0x64]	23682	1			T20	6		T26	6		T128	40
valid_sources[0x65]	24522	1			T20	5		T26	3		T180	1
valid_sources[0x66]	22273	1			T20	2		T24	3		T129	3
valid_sources[0x67]	20774	1			T20	3		T22	2		T24	3
valid_sources[0x68]	22822	1			T20	1		T26	8		T133	1
valid_sources[0x69]	21861	1			T20	3		T24	4		T135	3
valid_sources[0x6a]	22875	1			T20	4		T24	1		T26	1
valid_sources[0x6b]	23100	1			T20	1		T21	1		T24	5
valid_sources[0x6c]	21830	1			T20	1		T26	3		T180	3
valid_sources[0x6d]	20628	1			T20	3		T21	1		T26	1
valid_sources[0x6e]	23295	1			T20	5		T24	3		T26	1
valid_sources[0x6f]	23992	1			T20	1		T26	5		T28	2
valid_sources[0x70]	22284	1			T20	2		T27	1		T180	1
valid_sources[0x71]	22091	1			T20	8		T26	1		T27	1
valid_sources[0x72]	20300	1			T20	2		T26	6		T180	1
valid_sources[0x73]	23829	1			T20	1		T26	1		T135	10
valid_sources[0x74]	21682	1			T20	1		T23	1		T135	1
valid_sources[0x75]	24128	1			T20	2		T24	5		T26	2
valid_sources[0x76]	23019	1			T20	4		T26	3		T180	1
valid_sources[0x77]	23530	1			T20	2		T24	3		T26	1
valid_sources[0x78]	23279	1			T20	3		T166	25		T133	1
valid_sources[0x79]	22485	1			T20	3		T21	1		T23	1
valid_sources[0x7a]	21526	1			T20	5		T21	2		T24	2
valid_sources[0x7b]	23048	1			T20	1		T129	5		T130	24
valid_sources[0x7c]	22895	1			T20	1		T23	2		T26	2
valid_sources[0x7d]	23132	1			T20	1		T22	2		T26	2
valid_sources[0x7e]	22477	1			T20	1		T21	1		T24	2
valid_sources[0x7f]	21925	1			T20	1		T24	4		T133	5
valid_sources[0x80]	24231	1			T20	3		T26	2		T129	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1303841

1

T19

4

T20

89

T21

5

values[0x0]

all_enables

biggest_size

1947312

1

T19

2

T20

66

T21

1

values[0x1]

all_enables

biggest_size

1945299

1

T19

1

T20

80

T21

1