Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2230	1		T1	2	T2	3	T32	1
non_zero_bins[1]	1639	1		T32	2	T10	2	T38	1
zero	7260	1		T1	2	T2	2	T3	4

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	447	1		T5	16	T6	12	T54	12
uni	3060	1		T1	1	T32	1	T39	1
gen	3449	1		T1	1	T2	2	T3	2
res	678	1		T1	1	T2	2	T32	1
ins	3495	1		T1	1	T2	1	T3	2

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

7534

mubi_true

3595

T32

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5577

pass

5552

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	45	1		T5	1	T6	1	T103	3
upd	non_zero_bins[0]	fail	mubi_true	53	1		T5	2	T6	2	T54	1
upd	non_zero_bins[0]	pass	mubi_false	47	1		T5	1	T6	1	T54	2
upd	non_zero_bins[0]	pass	mubi_true	47	1		T5	1	T54	1	T58	1
upd	non_zero_bins[1]	fail	mubi_false	42	1		T5	3	T6	1	T54	2
upd	non_zero_bins[1]	fail	mubi_true	42	1		T5	2	T6	2	T196	1
upd	non_zero_bins[1]	pass	mubi_false	42	1		T5	2	T6	2	T54	2
upd	non_zero_bins[1]	pass	mubi_true	44	1		T5	2	T6	2	T54	2
upd	zero	fail	mubi_false	18	1		T5	1	T197	1	T198	1
upd	zero	fail	mubi_true	29	1		T82	1	T35	1	T58	1
upd	zero	pass	mubi_false	19	1		T6	1	T82	2	T103	1
upd	zero	pass	mubi_true	19	1		T5	1	T54	2	T196	1
uni	zero	fail	mubi_false	1112	1		T32	1	T39	1	T38	1
uni	zero	fail	mubi_true	389	1		T5	15	T6	12	T68	1
uni	zero	pass	mubi_false	1099	1		T1	1	T5	35	T6	19
uni	zero	pass	mubi_true	460	1		T5	12	T45	1	T6	8
gen	non_zero_bins[0]	fail	mubi_false	222	1		T1	1	T2	1	T32	1
gen	non_zero_bins[0]	fail	mubi_true	221	1		T40	1	T5	8	T6	4
gen	non_zero_bins[0]	pass	mubi_false	216	1		T2	1	T5	7	T6	4
gen	non_zero_bins[0]	pass	mubi_true	190	1		T5	3	T6	2	T54	3
gen	non_zero_bins[1]	fail	mubi_false	171	1		T5	1	T82	3	T12	3
gen	non_zero_bins[1]	fail	mubi_true	159	1		T38	1	T5	4	T6	2
gen	non_zero_bins[1]	pass	mubi_false	148	1		T5	2	T54	2	T55	1
gen	non_zero_bins[1]	pass	mubi_true	168	1		T10	2	T5	1	T6	1
gen	zero	fail	mubi_false	794	1		T5	21	T6	22	T68	2
gen	zero	fail	mubi_true	191	1		T37	1	T5	3	T45	1
gen	zero	pass	mubi_false	796	1		T3	2	T39	1	T5	10
gen	zero	pass	mubi_true	173	1		T38	1	T5	2	T54	3
res	non_zero_bins[0]	fail	mubi_false	98	1		T40	1	T6	1	T54	1
res	non_zero_bins[0]	fail	mubi_true	87	1		T1	1	T10	1	T6	2
res	non_zero_bins[0]	pass	mubi_false	69	1		T5	3	T82	1	T83	1
res	non_zero_bins[0]	pass	mubi_true	77	1		T10	1	T38	1	T6	1
res	non_zero_bins[1]	fail	mubi_false	49	1		T5	2	T82	3	T103	2
res	non_zero_bins[1]	fail	mubi_true	60	1		T5	3	T6	1	T82	1
res	non_zero_bins[1]	pass	mubi_false	49	1		T32	1	T82	1	T58	1
res	non_zero_bins[1]	pass	mubi_true	49	1		T54	1	T34	1	T82	1
res	zero	fail	mubi_false	31	1		T68	1	T11	1	T54	1
res	zero	fail	mubi_true	32	1		T2	1	T54	2	T197	1
res	zero	pass	mubi_false	39	1		T5	2	T6	2	T11	1
res	zero	pass	mubi_true	38	1		T2	1	T69	1	T82	1
ins	non_zero_bins[0]	fail	mubi_false	223	1		T10	1	T5	6	T45	1
ins	non_zero_bins[0]	fail	mubi_true	200	1		T5	7	T6	4	T68	1
ins	non_zero_bins[0]	pass	mubi_false	215	1		T2	1	T5	6	T6	3
ins	non_zero_bins[0]	pass	mubi_true	220	1		T5	11	T45	1	T6	3
ins	non_zero_bins[1]	fail	mubi_false	144	1		T5	5	T6	2	T54	2
ins	non_zero_bins[1]	fail	mubi_true	146	1		T5	3	T6	5	T54	7
ins	non_zero_bins[1]	pass	mubi_false	166	1		T5	1	T6	3	T54	6
ins	non_zero_bins[1]	pass	mubi_true	160	1		T32	1	T5	5	T6	3
ins	zero	fail	mubi_false	848	1		T3	1	T39	1	T5	15
ins	zero	fail	mubi_true	171	1		T38	1	T37	1	T5	2
ins	zero	pass	mubi_false	832	1		T1	1	T3	1	T5	20
ins	zero	pass	mubi_true	170	1		T40	1	T5	1	T16	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded